| /external/libvpx/libvpx/vpx_dsp/mips/ |
| D | itrans32_dspr2.c | 36 int load1, load2, load3, load4; in idct32_rows_dspr2() local
147 : [load1] "=&r"(load1), [load2] "=&r"(load2), [load3] "=&r"(load3), in idct32_rows_dspr2()
207 : [load1] "=&r"(load1), [load2] "=&r"(load2), [load3] "=&r"(load3), in idct32_rows_dspr2()
267 : [load1] "=&r"(load1), [load2] "=&r"(load2), [load3] "=&r"(load3), in idct32_rows_dspr2()
323 : [load1] "=&r"(load1), [load2] "=&r"(load2), [load3] "=&r"(load3), in idct32_rows_dspr2()
379 : [load1] "=&r"(load1), [load2] "=&r"(load2), [load3] "=&r"(load3), in idct32_rows_dspr2()
435 : [load1] "=&r"(load1), [load2] "=&r"(load2), [load3] "=&r"(load3), in idct32_rows_dspr2()
661 : [load1] "=&r"(load1), [load2] "=&r"(load2), [load3] "=&r"(load3), in idct32_rows_dspr2()
720 : [load1] "=&r"(load1), [load2] "=&r"(load2), [load3] "=&r"(load3), in idct32_rows_dspr2()
874 [load2] "=&r"(load2), [temp2] "=&r"(temp2), [load3] "=&r"(load3), in idct32_rows_dspr2()
[all …]
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| D | itrans32_cols_dspr2.c | 32 int load1, load2, load3, load4; in vpx_idct32_cols_add_blk_dspr2() local
103 : [load1] "=&r"(load1), [load2] "=&r"(load2), [load3] "=&r"(load3), in vpx_idct32_cols_add_blk_dspr2()
163 : [load1] "=&r"(load1), [load2] "=&r"(load2), [load3] "=&r"(load3), in vpx_idct32_cols_add_blk_dspr2()
223 : [load1] "=&r"(load1), [load2] "=&r"(load2), [load3] "=&r"(load3), in vpx_idct32_cols_add_blk_dspr2()
279 : [load1] "=&r"(load1), [load2] "=&r"(load2), [load3] "=&r"(load3), in vpx_idct32_cols_add_blk_dspr2()
335 : [load1] "=&r"(load1), [load2] "=&r"(load2), [load3] "=&r"(load3), in vpx_idct32_cols_add_blk_dspr2()
391 : [load1] "=&r"(load1), [load2] "=&r"(load2), [load3] "=&r"(load3), in vpx_idct32_cols_add_blk_dspr2()
617 : [load1] "=&r"(load1), [load2] "=&r"(load2), [load3] "=&r"(load3), in vpx_idct32_cols_add_blk_dspr2()
676 : [load1] "=&r"(load1), [load2] "=&r"(load2), [load3] "=&r"(load3), in vpx_idct32_cols_add_blk_dspr2()
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| D | convolve2_vert_dspr2.c | 30 uint32_t load1, load2; in convolve_bi_vert_4_dspr2() local
98 : [load1] "=&r"(load1), [load2] "=&r"(load2), [p1] "=&r"(p1), in convolve_bi_vert_4_dspr2()
120 uint32_t load1, load2; in convolve_bi_vert_64_dspr2() local
188 : [load1] "=&r"(load1), [load2] "=&r"(load2), [p1] "=&r"(p1), in convolve_bi_vert_64_dspr2()
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| D | convolve2_avg_dspr2.c | 30 uint32_t load1, load2; in convolve_bi_avg_vert_4_dspr2() local
105 : [load1] "=&r"(load1), [load2] "=&r"(load2), [p1] "=&r"(p1), in convolve_bi_avg_vert_4_dspr2()
129 uint32_t load1, load2; in convolve_bi_avg_vert_64_dspr2() local
205 : [load1] "=&r"(load1), [load2] "=&r"(load2), [p1] "=&r"(p1), in convolve_bi_avg_vert_64_dspr2()
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| D | convolve8_vert_dspr2.c | 30 uint32_t load1, load2, load3, load4; in convolve_vert_4_dspr2() local
152 : [load1] "=&r"(load1), [load2] "=&r"(load2), [load3] "=&r"(load3), in convolve_vert_4_dspr2()
178 uint32_t load1, load2, load3, load4; in convolve_vert_64_dspr2() local
301 : [load1] "=&r"(load1), [load2] "=&r"(load2), [load3] "=&r"(load3), in convolve_vert_64_dspr2()
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| D | convolve8_avg_dspr2.c | 30 uint32_t load1, load2, load3, load4; in convolve_avg_vert_4_dspr2() local
160 : [load1] "=&r"(load1), [load2] "=&r"(load2), [load3] "=&r"(load3), in convolve_avg_vert_4_dspr2()
186 uint32_t load1, load2, load3, load4; in convolve_avg_vert_64_dspr2() local
317 : [load1] "=&r"(load1), [load2] "=&r"(load2), [load3] "=&r"(load3), in convolve_avg_vert_64_dspr2()
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| D | itrans16_dspr2.c | 25 int load1, load2, load3, load4, load5, load6, load7, load8; in idct16_rows_dspr2() local
67 : [load1] "=&r"(load1), [load2] "=&r"(load2), [load3] "=&r"(load3), in idct16_rows_dspr2()
189 : [load1] "=&r"(load1), [load2] "=&r"(load2), [load3] "=&r"(load3), in idct16_rows_dspr2()
400 int load1, load2, load3, load4, load5, load6, load7, load8; in idct16_cols_add_blk_dspr2() local
452 : [load1] "=&r"(load1), [load2] "=&r"(load2), [load3] "=&r"(load3), in idct16_cols_add_blk_dspr2()
574 : [load1] "=&r"(load1), [load2] "=&r"(load2), [load3] "=&r"(load3), in idct16_cols_add_blk_dspr2()
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| /external/llvm/test/Transforms/SLPVectorizer/X86/ |
| D | propagate_ir_flags.ll | 19 %load2 = load i32, i32* %idx2, align 4
24 %op2 = lshr exact i32 %load2, 1
45 %load2 = load i32, i32* %idx2, align 4
50 %op2 = lshr i32 %load2, 1
71 %load2 = load i32, i32* %idx2, align 4
76 %op2 = add nsw i32 %load2, 1
97 %load2 = load i32, i32* %idx2, align 4
102 %op2 = add nsw i32 %load2, 1
123 %load2 = load i32, i32* %idx2, align 4
128 %op2 = add nuw i32 %load2, 1
[all …]
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| D | pr27163.ll | 12 %load2 = load i64, i64* %gep2, align 8
14 store i64 %load2, i64* %gep2, align 8
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| /external/llvm/test/CodeGen/AArch64/ |
| D | ldst-opt.ll | 286 %pre.struct.i32* %load2) nounwind {
295 %gep2 = getelementptr inbounds %pre.struct.i32, %pre.struct.i32* %load2, i64 0, i32 2
304 %pre.struct.i64* %load2) nounwind {
313 %gep2 = getelementptr inbounds %pre.struct.i64, %pre.struct.i64* %load2, i64 0, i32 2
322 %pre.struct.i128* %load2) nounwind {
331 %gep2 = getelementptr inbounds %pre.struct.i128, %pre.struct.i128* %load2, i64 0, i32 2
340 %pre.struct.float* %load2) nounwind {
349 %gep2 = getelementptr inbounds %pre.struct.float, %pre.struct.float* %load2, i64 0, i32 2
358 %pre.struct.double* %load2) nounwind {
367 %gep2 = getelementptr inbounds %pre.struct.double, %pre.struct.double* %load2, i64 0, i32 2
[all …]
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| D | arm64-vabs.ll | 38 %load2 = load <16 x i8>, <16 x i8>* %B
40 …%tmp2 = shufflevector <16 x i8> %load2, <16 x i8> undef, <8 x i32> <i32 8, i32 9, i32 10, i32 11, …
50 %load2 = load <8 x i16>, <8 x i16>* %B
52 … %tmp2 = shufflevector <8 x i16> %load2, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
62 %load2 = load <4 x i32>, <4 x i32>* %B
64 %tmp2 = shufflevector <4 x i32> %load2, <4 x i32> undef, <2 x i32> <i32 2, i32 3>
104 %load2 = load <16 x i8>, <16 x i8>* %B
106 …%tmp2 = shufflevector <16 x i8> %load2, <16 x i8> undef, <8 x i32> <i32 8, i32 9, i32 10, i32 11, …
117 %load2 = load <8 x i16>, <8 x i16>* %B
119 %tmp2 = shufflevector <8 x i16> %load2, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
[all …]
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| D | free-zext.ll | 63 %phi = phi i32 [ %load1, %bb1 ], [ %load2, %loop ]
66 %load2 = load i32, i32* %ptr2, align 4
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| D | arm64-vmul.ll | 88 %load2 = load <8 x i16>, <8 x i16>* %B
90 %tmp2 = shufflevector <8 x i16> %load2, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
99 %load2 = load <4 x i32>, <4 x i32>* %B
101 %tmp2 = shufflevector <4 x i32> %load2, <4 x i32> undef, <2 x i32> <i32 2, i32 3>
329 %load2 = load <8 x i16>, <8 x i16>* %B
332 %tmp2 = shufflevector <8 x i16> %load2, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
342 %load2 = load <4 x i32>, <4 x i32>* %B
345 %tmp2 = shufflevector <4 x i32> %load2, <4 x i32> undef, <2 x i32> <i32 2, i32 3>
377 %load2 = load <8 x i16>, <8 x i16>* %B
380 %tmp2 = shufflevector <8 x i16> %load2, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
[all …]
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| /external/llvm/test/Transforms/LoadCombine/ |
| D | load-combine-aa.ll | 15 %load2 = load i32, i32* %arrayidx1, align 4
16 %conv2 = zext i32 %load2 to i64
33 %load2 = load i32, i32* %arrayidx1, align 4
34 %conv2 = zext i32 %load2 to i64
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| D | load-combine-assume.ll | 18 %load2 = load i32, i32* %arrayidx1, align 4
20 %conv2 = zext i32 %load2 to i64
38 %load2 = load i32, i32* %arrayidx1, align 4
39 %conv2 = zext i32 %load2 to i64
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| /external/llvm/test/CodeGen/X86/ |
| D | addr-mode-matcher.ll | 31 ; %load2 = (load (shl (and %xor, 255), 2))
36 %load2 = load i32, i32* %tmp1708, align 4
38 %tmp1710 = or i32 %load2, %a
42 ; node becomes identical to %load2. CSE replaces %load1 which leaves its
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| D | add-nsw-sext.ll | 160 %load2 = load i32, i32* %gep2, align 4
162 %add3 = add i32 %load1, %load2
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| /external/llvm/test/Transforms/CodeGenPrepare/AArch64/ |
| D | free-zext.ll | 18 %load2 = load i32, i32* %ptr2, align 4
23 %phi = phi i32 [ %load1, %bb1 ], [ %load2, %bb2 ]
70 %phi = phi i32 [ %load1, %bb1 ], [ %load2, %loop ]
77 %load2 = load i32, i32* %addr, align 4
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| /external/llvm/test/CodeGen/SPARC/ |
| D | select-mask.ll | 13 %bf.load2 = load i8, i8* %this, align 4
14 %bf.cast5 = trunc i8 %bf.load2 to i1
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| /external/llvm/test/CodeGen/ARM/ |
| D | neon_cmp.ll | 8 %wide.load2 = load <2 x double>, <2 x double>* %b, align 4
11 %v1 = fcmp olt <2 x double> %wide.load, %wide.load2
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| /external/llvm/test/CodeGen/PowerPC/ |
| D | indexed-load.ll | 18 %bf.load2.i.i = load i40, i40* %0, align 4
19 %bf.clear7.i.i = and i40 %bf.load2.i.i, -8589934592
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| /external/mesa3d/src/compiler/nir/ |
| D | nir_instr_set.c | 328 nir_load_const_instr *load2 = nir_instr_as_load_const(instr2); in nir_instrs_equal() local
330 if (load1->def.num_components != load2->def.num_components) in nir_instrs_equal()
333 if (load1->def.bit_size != load2->def.bit_size) in nir_instrs_equal()
336 return memcmp(load1->value.f32, load2->value.f32, in nir_instrs_equal()
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| /external/llvm/test/Instrumentation/AddressSanitizer/ |
| D | experiment-call.ll | 16 define void @load2(i16* %p) sanitize_address {
20 ; CHECK-LABEL: define void @load2
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| D | experiment.ll | 16 define void @load2(i16* %p) sanitize_address {
20 ; CHECK-LABEL: define void @load2
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| /external/bart/docs/notebooks/thermal/ |
| D | Thermal.ipynb | 174 "result = t.getStatement(\"((IN:load0 + IN:load1 + IN:load2 + IN:load3) == 0) \\\n",
182 "result = t.getStatement(\"((IN:load0 + IN:load1 + IN:load2 + IN:load3) == 0) \\\n",
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