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/external/libhevc/common/arm64/
Dihevc_sao_edge_offset_class0.s161 …mov v28.b[15], w11 //II Iteration vsetq_lane_u8(pu1_src_left[ht - row], pu1_c…
169 …EXT v28.16b, v28.16b , v26.16b,#15 //II Iteration pu1_cur_row_tmp = vextq_u8(pu1_cur_row…
174 cmhi v30.16b, v26.16b , v28.16b //II vcgtq_u8(pu1_cur_row, pu1_cur_row_tmp)
180 cmhi v0.16b, v28.16b , v26.16b //II vcltq_u8(pu1_cur_row, pu1_cur_row_tmp)
181 …mov v28.b[0], w11 //II pu1_cur_row_tmp = vsetq_lane_u8(pu1_src_cpy[16], pu1_…
189 …EXT v28.16b, v26.16b , v28.16b,#1 //II pu1_cur_row_tmp = vextq_u8(pu1_cur_row, pu1_cur_r…
203 cmhi v30.16b, v26.16b , v28.16b //II vcgtq_u8(pu1_cur_row, pu1_cur_row_tmp)
205 cmhi v0.16b, v28.16b , v26.16b //II vcltq_u8(pu1_cur_row, pu1_cur_row_tmp)
213 ADD v28.16b, v2.16b , v20.16b //II edge_idx = vaddq_s8(const_2, sign_left)
214 ADD v28.16b, v28.16b , v22.16b //II edge_idx = vaddq_s8(edge_idx, sign_right)
[all …]
Dihevc_sao_edge_offset_class0_chroma.s184 …mov v28.h[7], w11 //II vsetq_lane_u16(pu1_src_left[ht - row], pu1_cur_row_tm…
192 …EXT v28.16b, v28.16b , v30.16b,#14 //II pu1_cur_row_tmp = vextq_u8(pu1_cur_row_tmp, pu1_…
195 cmhi v26.16b, v30.16b , v28.16b //II vcgtq_u8(pu1_cur_row, pu1_cur_row_tmp)
198 cmhi v24.16b, v28.16b , v30.16b //II vcltq_u8(pu1_cur_row, pu1_cur_row_tmp)
206 …mov v28.b[0], w11 //II pu1_cur_row_tmp = vsetq_lane_u8(pu1_src_cpy[16], pu1_…
213 …mov v28.b[1], w11 //II pu1_cur_row_tmp = vsetq_lane_u8(pu1_src_cpy[17], pu1_…
216 …EXT v28.16b, v30.16b , v28.16b,#2 //II pu1_cur_row_tmp = vextq_u8(pu1_cur_row, pu1_cur_r…
225 cmhi v26.16b, v30.16b , v28.16b //II vcgtq_u8(pu1_cur_row, pu1_cur_row_tmp)
227 cmhi v24.16b, v28.16b , v30.16b //II vcltq_u8(pu1_cur_row, pu1_cur_row_tmp)
281 …Uxtl v28.8h, v30.8b //II pi2_tmp_cur_row.val[0] = vreinterpretq_s16_u16(vmovl_…
[all …]
Dihevc_inter_pred_chroma_vert_w16inp.s200 smull v28.4s, v1.4h, v16.4h //vmull_s16(src_tmp2, coeff_0)
203 smlal v28.4s, v2.4h, v17.4h
205 smlal v28.4s, v3.4h, v18.4h
207 smlal v28.4s, v4.4h, v19.4h
221 sqshrn v28.4h, v28.4s,#6 //right shift
236 sqrshrun v28.8b, v28.8h,#6 //rounding shift
244 st1 {v28.s}[0],[x9],x3 //stores the loaded value
252 smull v28.4s, v1.4h, v16.4h //vmull_s16(src_tmp2, coeff_0)
253 smlal v28.4s, v2.4h, v17.4h
254 smlal v28.4s, v3.4h, v18.4h
[all …]
Dihevc_sao_edge_offset_class1_chroma.s152 …LD1 {v28.16b},[x11],#16 //pu1_top_row = vld1q_u8(pu1_src_top_cpy || pu1_src - src_…
159 cmhi v5.16b, v3.16b , v28.16b //vcgtq_u8(pu1_cur_row, pu1_top_row)
162 cmhi v19.16b, v28.16b , v3.16b //vcltq_u8(pu1_cur_row, pu1_top_row)
187 …Uxtl2 v28.8h, v18.16b //II pi2_tmp_cur_row.val[1] = vreinterpretq_s16_u16(vmovl_…
197 …SUB v28.16b, v24.16b , v22.16b //II sign_down = vreinterpretq_s8_u8(vsubq_u8(cmp_lt, cmp…
205 NEG v16.16b, v28.16b //II sign_up = vnegq_s8(sign_down)
207 ADD v22.16b, v22.16b , v28.16b //II edge_idx = vaddq_s8(edge_idx, sign_down)
227 …Uxtl2 v28.8h, v3.16b //pi2_tmp_cur_row.val[1] = vreinterpretq_s16_u16(vmovl_u8(…
231 …SADDW v28.8h, v28.8h , v17.8b //pi2_tmp_cur_row.val[1] = vaddw_s8(pi2_tmp_cur_row.val[1]…
233 …SMAX v28.8h, v28.8h , v2.8h //pi2_tmp_cur_row.val[1] = vmaxq_s16(pi2_tmp_cur_row.val[1…
[all …]
Dihevc_itrans_recon_16x16.s257 smull v28.4s, v6.4h, v1.h[1] //// y1 * sin3(part of b2)
262 smlal v28.4s, v7.4h, v3.h[3] //// y1 * sin3 - y3 * cos1(part of b2)
284 smlsl v28.4s, v8.4h, v1.h[3]
290 smlsl v28.4s, v9.4h, v0.h[3]
333 smlsl v28.4s, v6.4h, v3.h[1] //// y1 * sin3(part of b2)
338 smlal v28.4s, v7.4h, v2.h[1] //// y1 * sin3 - y3 * cos1(part of b2)
345 smlal v28.4s, v8.4h, v0.h[1]
351 smlal v28.4s, v9.4h, v2.h[3]
390 add v14.4s, v16.4s , v28.4s
391 sub v26.4s, v16.4s , v28.4s
[all …]
Dihevc_inter_pred_chroma_vert_w16inp_w16out.s199 smull v28.4s, v1.4h, v16.4h //vmull_s16(src_tmp2, coeff_0)
204 smlal v28.4s, v2.4h, v17.4h
205 smlal v28.4s, v3.4h, v18.4h
207 smlal v28.4s, v4.4h, v19.4h
219 sqshrn v28.4h, v28.4s,#6 //right shift
241 st1 {v28.2s},[x9],x3 //stores the loaded value
248 smull v28.4s, v1.4h, v16.4h //vmull_s16(src_tmp2, coeff_0)
249 smlal v28.4s, v2.4h, v17.4h
250 smlal v28.4s, v3.4h, v18.4h
251 smlal v28.4s, v4.4h, v19.4h
[all …]
Dihevc_inter_pred_chroma_vert.s245 umull v28.8h, v6.8b, v1.8b //mul_res 2
248 umlsl v28.8h, v5.8b, v0.8b
251 umlal v28.8h, v7.8b, v2.8b
253 umlsl v28.8h, v16.8b, v3.8b
264 sqrshrun v28.8b, v28.8h,#6
278 st1 {v28.8b},[x7],x3 //stores the loaded value
304 umull v28.8h, v6.8b, v1.8b //mul_res 2
307 umlsl v28.8h, v5.8b, v0.8b
310 umlal v28.8h, v7.8b, v2.8b
315 umlsl v28.8h, v16.8b, v3.8b
[all …]
Dihevc_intra_pred_chroma_planar.s198 umull v28.8h, v5.8b, v0.8b
201 umlal v28.8h, v6.8b, v11.8b
205 umlal v28.8h, v31.8b, v4.8b
207 umlal v28.8h, v25.8b, v1.8b
215 add v28.8h, v28.8h , v16.8h
217 sshl v28.8h, v28.8h, v14.8h
230 xtn v13.8b, v28.8h
268 umull v28.8h, v18.8b, v0.8b
271 umlal v28.8h, v19.8b, v11.8b
275 umlal v28.8h, v25.8b, v1.8b
[all …]
Dihevc_itrans_recon_8x8.s196 smull v28.4s, v6.4h, v1.h[1] //// y1 * sin3(part of b2)
204 smlsl v28.4s, v7.4h, v0.h[1] //// y1 * sin3 - y3 * cos1(part of b2)
236 smlal v28.4s, v14.4h, v1.h[3] //// y1 * sin3 - y3 * cos1 + y5 * sin1(part of b2)
247 …smlal v28.4s, v15.4h, v0.h[3] //// b2 = y1 * sin3 - y3 * cos1 + y5 * sin1 + y7 * cos3(pa…
258 add v24.4s, v22.4s , v28.4s //// a2 + b2(part of x2)
259 sub v22.4s, v22.4s , v28.4s //// a2 - b2(part of x5)
261 add v28.4s, v18.4s , v26.4s //// a1 + b1(part of x1)
271 sqrshrn v6.4h, v28.4s,#shift_stage1_idct //// x1 = (a1 + b1 + rnd) >> 7(shift_stage1_idct)
306 smull v28.4s, v6.4h, v1.h[1] //// y1 * sin3(part of b2)
311 smlsl v28.4s, v7.4h, v0.h[1] //// y1 * sin3 - y3 * cos1(part of b2)
[all …]
Dihevc_itrans_recon_32x32.s218 smull v28.4s, v8.4h, v1.h[1] //// y1 * sin3(part of b2)
223 smlal v28.4s, v9.4h, v3.h[3] //// y1 * sin3 - y3 * cos1(part of b2)
258 smlal v28.4s, v14.4h, v6.h[1]
264 smlsl v28.4s, v15.4h, v7.h[1]
288 smlsl v28.4s, v8.4h, v4.h[3] //// y1 * sin3(part of b2)
293 smlsl v28.4s, v9.4h, v2.h[1] //// y1 * sin3 - y3 * cos1(part of b2)
332 smlsl v28.4s, v14.4h, v0.h[1]
338 smlsl v28.4s, v15.4h, v2.h[3]
364 smlsl v28.4s, v8.4h, v5.h[1] //// y1 * sin3(part of b2)
369 smlsl v28.4s, v9.4h, v7.h[3] //// y1 * sin3 - y3 * cos1(part of b2)
[all …]
/external/libavc/common/armv8/
Dih264_intra_pred_luma_16x16_av8.s499 shl v28.8h, v4.8h, #3
503 sub v30.8h, v30.8h , v28.8h
505 add v28.8h, v30.8h , v6.8h
506 add v26.8h, v28.8h , v0.8h
507 add v28.8h, v28.8h , v2.8h
509 sqrshrun v21.8b, v28.8h, #5
511 add v28.8h, v28.8h , v6.8h
514 sqrshrun v23.8b, v28.8h, #5
516 add v28.8h, v28.8h , v6.8h
519 sqrshrun v21.8b, v28.8h, #5
[all …]
Dih264_inter_pred_luma_horz_hpel_vert_hpel_av8.s95 movi v28.8h, #0x14 // Filter coeff 20 into Q13
117 mla v18.8h, v20.8h , v28.8h
121 mla v20.8h, v24.8h , v28.8h
127 mla v22.8h, v24.8h , v28.8h
140 smlal v26.4s, v0.4h, v28.4h
144 smlal2 v23.4s, v0.8h, v28.8h
165 smlal v26.4s, v25.4h, v28.4h
169 smlal2 v22.4s, v25.8h, v28.8h
198 mla v18.8h, v20.8h , v28.8h
202 mla v20.8h, v24.8h , v28.8h
[all …]
Dih264_inter_pred_filters_luma_horz_av8.s136 ext v28.8b, v5.8b , v6.8b, #5 ////extract a[5] (column1,row1)
139 uaddl v14.8h, v28.8b, v5.8b //// a0 + a5 (column1,row1)
144 ext v28.8b, v5.8b , v6.8b, #2 ////extract a[2] (column1,row1)
147 umlal v14.8h, v28.8b, v1.8b //// a0 + a5 + 20a2 (column1,row1)
152 ext v28.8b, v5.8b , v6.8b, #3 ////extract a[3] (column1,row1)
155 umlal v14.8h, v28.8b, v1.8b //// a0 + a5 + 20a2 + 20a3 (column1,row1)
160 ext v28.8b, v5.8b , v6.8b, #1 ////extract a[1] (column1,row1)
163 umlsl v14.8h, v28.8b, v0.8b //// a0 + a5 + 20a2 + 20a3 - 5a1 (column1,row1)
168 ext v28.8b, v5.8b , v6.8b, #4 ////extract a[4] (column1,row1)
171 umlsl v14.8h, v28.8b, v0.8b //// a0 + a5 + 20a2 + 20a3 - 5a1 - 5a4 (column1,row1)
[all …]
Dih264_inter_pred_luma_horz_qpel_vert_hpel_av8.s156 movi v28.8h, #0x14 // Filter coeff 20 into Q13
179 mla v18.8h, v20.8h , v28.8h
183 mla v20.8h, v24.8h , v28.8h
189 mla v22.8h, v24.8h , v28.8h
203 smlal v26.4s, v0.4h, v28.4h
207 smlal2 v22.4s, v0.8h, v28.8h
228 smlal v26.4s, v18.4h, v28.4h
232 smlal2 v22.4s, v18.8h, v28.8h
266 mla v18.8h, v20.8h , v28.8h
270 mla v20.8h, v24.8h , v28.8h
[all …]
Dih264_inter_pred_luma_horz_qpel_av8.s144 ext v28.8b, v5.8b , v6.8b , #5
147 uaddl v14.8h, v28.8b, v5.8b //// a0 + a5 (column1,row1)
152 ext v28.8b, v5.8b , v6.8b , #2
155 umlal v14.8h, v28.8b, v1.8b //// a0 + a5 + 20a2 (column1,row1)
160 ext v28.8b, v5.8b , v6.8b , #3
163 umlal v14.8h, v28.8b, v1.8b //// a0 + a5 + 20a2 + 20a3 (column1,row1)
168 ext v28.8b, v5.8b , v6.8b , #1
171 umlsl v14.8h, v28.8b, v0.8b //// a0 + a5 + 20a2 + 20a3 - 5a1 (column1,row1)
176 ext v28.8b, v5.8b , v6.8b , #4
179 umlsl v14.8h, v28.8b, v0.8b //// a0 + a5 + 20a2 + 20a3 - 5a1 - 5a4 (column1,row1)
[all …]
Dih264_inter_pred_chroma_av8.s141 dup v28.8b, w10
159 umull v20.8h, v0.8b, v28.8b
167 umull v22.8h, v1.8b, v28.8b
175 umull v24.8h, v5.8b, v28.8b
183 umull v16.8h, v6.8b, v28.8b
190 umull v20.8h, v10.8b, v28.8b
195 umull v24.8h, v11.8b, v28.8b
202 umull v20.8h, v0.8b, v28.8b
208 umull v22.8h, v1.8b, v28.8b
221 umull v24.8h, v5.8b, v28.8b
[all …]
Dih264_inter_pred_luma_horz_qpel_vert_qpel_av8.s168 uaddl v28.8h, v18.8b, v23.8b
169 umlal v28.8h, v20.8b, v30.8b
170 umlal v28.8h, v21.8b, v30.8b
171 umlsl v28.8h, v19.8b, v31.8b
172 umlsl v28.8h, v22.8b, v31.8b
179 sqrshrun v28.8b, v28.8h, #5
209 urhadd v28.16b, v28.16b , v26.16b
216 st1 {v28.2s, v29.2s}, [x1], x3 // store row 0
221 uaddl v28.8h, v18.8b, v23.8b
222 umlal v28.8h, v20.8b, v30.8b
[all …]
Dih264_deblk_luma_av8.s125 uabd v28.16b, v10.16b, v6.16b
132 cmhi v20.16b, v16.16b , v28.16b //Q10=(Ap<Beta)
139 usubl v28.8h, v8.8b, v2.8b //Q14 = (p1 - q1)L
144 add v24.8h, v24.8h , v28.8h //
156 uaddl v28.8h, v17.8b, v11.8b //
164 sub v28.8h, v28.8h , v26.8h //Q14,Q5 = [p2 + (p0+q0+1)>>1] - (p1<<1)
168 sqshrn v29.8b, v28.8h, #1 //
169 sqshrn v28.8b, v10.8h, #1 //Q14 = i_macro_p1
170 mov v28.d[1], v29.d[0]
174 smin v28.16b, v28.16b , v14.16b //Q14 = min(C0,i_macro_p1)
[all …]
/external/libavc/encoder/armv8/
Dih264e_half_pel_av8.s113 ext v28.8b, v5.8b , v6.8b , #5
116 uaddl v14.8h, v28.8b, v5.8b //// a0 + a5 (column1,row1)
126 ext v28.8b, v5.8b , v6.8b , #2
129 umlal v14.8h, v28.8b, v1.8b //// a0 + a5 + 20a2 (column1,row1)
139 ext v28.8b, v5.8b , v6.8b , #3
142 umlal v14.8h, v28.8b, v1.8b //// a0 + a5 + 20a2 + 20a3 (column1,row1)
152 ext v28.8b, v5.8b , v6.8b , #1
155 umlsl v14.8h, v28.8b, v0.8b //// a0 + a5 + 20a2 + 20a3 - 5a1 (column1,row1)
165 ext v28.8b, v5.8b , v6.8b , #4
168 umlsl v14.8h, v28.8b, v0.8b //// a0 + a5 + 20a2 + 20a3 - 5a1 - 5a4 (column1,row1)
[all …]
/external/llvm/test/CodeGen/SystemZ/
Dvec-cmp-06.ll8 ; CHECK: vfcedb %v24, %v26, %v28
18 ; CHECK-DAG: vfchdb [[REG1:%v[0-9]+]], %v28, %v26
19 ; CHECK-DAG: vfchdb [[REG2:%v[0-9]+]], %v26, %v28
30 ; CHECK: vfchdb %v24, %v26, %v28
40 ; CHECK: vfchedb %v24, %v26, %v28
50 ; CHECK: vfchedb %v24, %v28, %v26
60 ; CHECK: vfchdb %v24, %v28, %v26
70 ; CHECK-DAG: vfchdb [[REG1:%v[0-9]+]], %v28, %v26
71 ; CHECK-DAG: vfchdb [[REG2:%v[0-9]+]], %v26, %v28
82 ; CHECK: vfcedb [[REG:%v[0-9]+]], %v26, %v28
[all …]
Dvec-cmp-02.ll8 ; CHECK: vceqh %v24, %v26, %v28
18 ; CHECK: vceqh [[REG:%v[0-9]+]], %v26, %v28
29 ; CHECK: vchh %v24, %v26, %v28
39 ; CHECK: vchh [[REG:%v[0-9]+]], %v28, %v26
50 ; CHECK: vchh [[REG:%v[0-9]+]], %v26, %v28
61 ; CHECK: vchh %v24, %v28, %v26
71 ; CHECK: vchlh %v24, %v26, %v28
81 ; CHECK: vchlh [[REG:%v[0-9]+]], %v28, %v26
92 ; CHECK: vchlh [[REG:%v[0-9]+]], %v26, %v28
103 ; CHECK: vchlh %v24, %v28, %v26
[all …]
Dvec-cmp-01.ll8 ; CHECK: vceqb %v24, %v26, %v28
18 ; CHECK: vceqb [[REG:%v[0-9]+]], %v26, %v28
29 ; CHECK: vchb %v24, %v26, %v28
39 ; CHECK: vchb [[REG:%v[0-9]+]], %v28, %v26
50 ; CHECK: vchb [[REG:%v[0-9]+]], %v26, %v28
61 ; CHECK: vchb %v24, %v28, %v26
71 ; CHECK: vchlb %v24, %v26, %v28
81 ; CHECK: vchlb [[REG:%v[0-9]+]], %v28, %v26
92 ; CHECK: vchlb [[REG:%v[0-9]+]], %v26, %v28
103 ; CHECK: vchlb %v24, %v28, %v26
[all …]
Dvec-cmp-04.ll8 ; CHECK: vceqg %v24, %v26, %v28
18 ; CHECK: vceqg [[REG:%v[0-9]+]], %v26, %v28
29 ; CHECK: vchg %v24, %v26, %v28
39 ; CHECK: vchg [[REG:%v[0-9]+]], %v28, %v26
50 ; CHECK: vchg [[REG:%v[0-9]+]], %v26, %v28
61 ; CHECK: vchg %v24, %v28, %v26
71 ; CHECK: vchlg %v24, %v26, %v28
81 ; CHECK: vchlg [[REG:%v[0-9]+]], %v28, %v26
92 ; CHECK: vchlg [[REG:%v[0-9]+]], %v26, %v28
103 ; CHECK: vchlg %v24, %v28, %v26
[all …]
Dvec-cmp-03.ll8 ; CHECK: vceqf %v24, %v26, %v28
18 ; CHECK: vceqf [[REG:%v[0-9]+]], %v26, %v28
29 ; CHECK: vchf %v24, %v26, %v28
39 ; CHECK: vchf [[REG:%v[0-9]+]], %v28, %v26
50 ; CHECK: vchf [[REG:%v[0-9]+]], %v26, %v28
61 ; CHECK: vchf %v24, %v28, %v26
71 ; CHECK: vchlf %v24, %v26, %v28
81 ; CHECK: vchlf [[REG:%v[0-9]+]], %v28, %v26
92 ; CHECK: vchlf [[REG:%v[0-9]+]], %v26, %v28
103 ; CHECK: vchlf %v24, %v28, %v26
[all …]
/external/vixl/test/test-trace-reference/
Dlog-vregs29 # v28: 0x404783f4425f16c34042d6a1420a4396
67 # v28: 0x00000000000000000000000000000016
88 # v28: 0x00000000000000000000000000000000
98 # v28: 0x00000000000000000000000000000000 (d28: 0.00000)
168 # v28: 0x00000000000000004034000000000000 (d28: 20.0000)
215 # v28: 0x00000000000000004034000000000000
257 # v28: 0x0000000000000000ffffffffffffffff
277 # v28: 0x00000000000000000000000000000000
317 # v28: 0x0000000000000000ffffffffffffffff
326 # v28: 0x00000000000000000000000000000000
[all …]

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