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Searched refs:vclt (Results 1 – 25 of 27) sorted by relevance

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/external/llvm/test/MC/ARM/
Dneon-cmp-encoding.s107 vclt.s8 d16, d16, #0
113 @ CHECK: vclt.s8 d16, d16, #0 @ encoding: [0x20,0x02,0xf1,0xf3]
116 vclt.s8 q12, q13, q3
117 vclt.s16 q12, q13, q3
118 vclt.s32 q12, q13, q3
119 vclt.u8 q12, q13, q3
120 vclt.u16 q12, q13, q3
121 vclt.u32 q12, q13, q3
122 vclt.f32 q12, q13, q3
124 vclt.s8 d12, d13, d3
[all …]
Dfullfp16-neon.s130 vclt.f16 d2, d3, d4
131 vclt.f16 q2, q3, q4
137 vclt.f16 d2, d3, #0
138 vclt.f16 q2, q3, #0
139 @ ARM: vclt.f16 d2, d3, #0 @ encoding: [0x03,0x26,0xb5,0xf3]
140 @ ARM: vclt.f16 q2, q3, #0 @ encoding: [0x46,0x46,0xb5,0xf3]
141 @ THUMB: vclt.f16 d2, d3, #0 @ encoding: [0xb5,0xff,0x03,0x26]
142 @ THUMB: vclt.f16 q2, q3, #0 @ encoding: [0xb5,0xff,0x46,0x46]
Dfullfp16-neon-neg.s96 vclt.f16 d2, d3, d4
97 vclt.f16 q2, q3, q4
101 vclt.f16 d2, d3, #0
102 vclt.f16 q2, q3, #0
Dneon-bitwise-encoding.s304 vclt.s16 q5, #0
305 vclt.s16 d5, #0
/external/libavc/common/arm/
Dih264_deblk_chroma_a9.s193 vclt.u8 q4, q4, q11 @|p0-q0| < alpha ?
194 vclt.u8 q5, q5, q12 @|q1-q0| < beta ?
195 vclt.u8 q6, q6, q12 @|p1-p0| < beta ?
395 vclt.u8 q4, q4, q11 @|p0-q0| < alpha ?
397 vclt.u8 q5, q5, q12 @|q1-q0| < beta ?
399 vclt.u8 q6, q6, q12 @|p1-p0| < beta ?
522 vclt.u8 d4, d4, d11 @|p0-q0| < alpha ?
523 vclt.u8 d5, d5, d12 @|q1-q0| < beta ?
524 vclt.u8 d6, d6, d12 @|p1-p0| < beta ?
606 vclt.u8 d4, d4, d11 @|p0-q0| < alpha ?
[all …]
Dih264_resi_trans_quant_a9.s192 vclt.s16 q2, q12, #0 @Get the sign of row 1 blk 1
195 vclt.s16 q3, q13, #0 @Get the sign of row 2 blk 1
387 vclt.s16 q2, q12, #0 @Get the sign of row 1 blk 1
390 vclt.s16 q3, q13, #0 @Get the sign of row 2 blk 1
531 vclt.s16 q3, q0, #0 @get the sign row 1,2
532 vclt.s16 q4, q1, #0
648 vclt.s32 q4, q0, #0 @get the sign row 1,2
650 vclt.s32 q5, q1, #0
Dih264_deblk_luma_a9.s258 vclt.u8 q11, q11, q1 @Aq < Beta
259 vclt.u8 q10, q6, q10 @(ABS(p0 - q0) <((Alpha >>2) + 2))
/external/arm-neon-tests/
Dref_vclt.c26 #define INSN_NAME vclt
DAndroid.mk26 vcgt vclt vbsl vshl vldX vdup_lane vrshrn_n vqdmull_lane \
DMakefile.gcc47 vcgt vclt vbsl vshl vldX vdup_lane vrshrn_n vqdmull_lane \
DMakefile41 vcgt vclt vbsl vshl vldX vdup_lane vrshrn_n vqdmull_lane \
/external/swiftshader/third_party/LLVM/test/MC/ARM/
Dneon-cmp-encoding.s107 vclt.s8 d16, d16, #0
113 @ CHECK: vclt.s8 d16, d16, #0 @ encoding: [0x20,0x02,0xf1,0xf3]
/external/llvm/test/MC/Disassembler/ARM/
Dfullfp16-neon-arm.txt89 # CHECK: vclt.f16 d2, d3, #0
90 # CHECK: vclt.f16 q2, q3, #0
Dfullfp16-neon-thumb.txt89 # CHECK: vclt.f16 d2, d3, #0
90 # CHECK: vclt.f16 q2, q3, #0
/external/libmpeg2/common/arm/
Dideint_cac_a9.s208 vclt.u32 d0, d21, d20
/external/swiftshader/third_party/LLVM/test/CodeGen/ARM/
Dvcgt.ll193 ;CHECK: vclt.s8
/external/llvm/test/CodeGen/ARM/
Dvcgt.ll193 ;CHECK: vclt.s8
/external/vixl/src/aarch32/
Dassembler-aarch32.h4076 void vclt(Condition cond,
4081 void vclt(DataType dt, DRegister rd, DRegister rm, const DOperand& operand) { in vclt() function
4082 vclt(al, dt, rd, rm, operand); in vclt()
4085 void vclt(Condition cond,
4090 void vclt(DataType dt, QRegister rd, QRegister rm, const QOperand& operand) { in vclt() function
4091 vclt(al, dt, rd, rm, operand); in vclt()
4094 void vclt(
4096 void vclt(DataType dt, DRegister rd, DRegister rn, DRegister rm) { in vclt() function
4097 vclt(al, dt, rd, rn, rm); in vclt()
4100 void vclt(
[all …]
Ddisasm-aarch32.h1509 void vclt(Condition cond,
1515 void vclt(Condition cond,
1521 void vclt(
1524 void vclt(
Dassembler-aarch32.cc14598 void Assembler::vclt(Condition cond, in vclt() function in vixl::aarch32::Assembler
14635 Delegate(kVclt, &Assembler::vclt, cond, dt, rd, rm, operand); in vclt()
14638 void Assembler::vclt(Condition cond, in vclt() function in vixl::aarch32::Assembler
14675 Delegate(kVclt, &Assembler::vclt, cond, dt, rd, rm, operand); in vclt()
14678 void Assembler::vclt( in vclt() function in vixl::aarch32::Assembler
14722 Delegate(kVclt, &Assembler::vclt, cond, dt, rd, rn, rm); in vclt()
14725 void Assembler::vclt( in vclt() function in vixl::aarch32::Assembler
14769 Delegate(kVclt, &Assembler::vclt, cond, dt, rd, rn, rm); in vclt()
Dmacro-assembler-aarch32.h6191 vclt(cond, dt, rd, rm, operand); in Vclt()
6209 vclt(cond, dt, rd, rm, operand); in Vclt()
6224 vclt(cond, dt, rd, rn, rm); in Vclt()
6239 vclt(cond, dt, rd, rn, rm); in Vclt()
Ddisasm-aarch32.cc4283 void Disassembler::vclt(Condition cond, in vclt() function in vixl::aarch32::Disassembler
4297 void Disassembler::vclt(Condition cond, in vclt() function in vixl::aarch32::Disassembler
4311 void Disassembler::vclt( in vclt() function in vixl::aarch32::Disassembler
4322 void Disassembler::vclt( in vclt() function in vixl::aarch32::Disassembler
27354 vclt(CurrentCond(), in DecodeT32()
27383 vclt(CurrentCond(), in DecodeT32()
41726 vclt(al, in DecodeA32()
41753 vclt(al, in DecodeA32()
/external/clang/include/clang/Basic/
Darm_neon.td557 def VCLT : SOpInst<"vclt", "udd", "csifUcUsUiQcQsQiQfQUcQUsQUi", OP_LT>;
1005 def CFMLT : SOpInst<"vclt", "udd", "lUldQdQlQUl", OP_LT>;
1517 def SCALAR_CMLT : SInst<"vclt", "sss", "SlSUl">;
1534 def SCALAR_FCMLT : IInst<"vclt", "bss", "SfSd">;
/external/llvm/lib/Target/ARM/
DARMInstrNEON.td4771 defm VCLTz : N2V_QHS_cmp<0b11, 0b11, 0b01, 0b00100, 0, "vclt", "s",
8068 def : NEONInstAlias<"vclt${p}.s8 $Dd, $Dn, $Dm",
8070 def : NEONInstAlias<"vclt${p}.s16 $Dd, $Dn, $Dm",
8072 def : NEONInstAlias<"vclt${p}.s32 $Dd, $Dn, $Dm",
8074 def : NEONInstAlias<"vclt${p}.u8 $Dd, $Dn, $Dm",
8076 def : NEONInstAlias<"vclt${p}.u16 $Dd, $Dn, $Dm",
8078 def : NEONInstAlias<"vclt${p}.u32 $Dd, $Dn, $Dm",
8080 def : NEONInstAlias<"vclt${p}.f32 $Dd, $Dn, $Dm",
8083 def : NEONInstAlias<"vclt${p}.f16 $Dd, $Dn, $Dm",
8086 def : NEONInstAlias<"vclt${p}.s8 $Qd, $Qn, $Qm",
[all …]
/external/swiftshader/third_party/LLVM/test/MC/Disassembler/ARM/
Dneon.txt434 # CHECK: vclt.s8 d16, d16, #0

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