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Searched refs:vqrshrn (Results 1 – 25 of 35) sorted by relevance

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/external/libhevc/common/arm/
Dihevc_itrans_recon_8x8.s273 vqrshrn.s32 d2,q10,#shift_stage1_idct @// r0 = (a0 + b0 + rnd) >> 7(shift_stage1_idct)
274 vqrshrn.s32 d15,q3,#shift_stage1_idct @// r7 = (a0 - b0 + rnd) >> 7(shift_stage1_idct)
275 vqrshrn.s32 d3,q12,#shift_stage1_idct @// r2 = (a2 + b2 + rnd) >> 7(shift_stage1_idct)
276 vqrshrn.s32 d14,q11,#shift_stage1_idct @// r5 = (a2 - b2 + rnd) >> 7(shift_stage1_idct)
277 vqrshrn.s32 d6,q14,#shift_stage1_idct @// r1 = (a1 + b1 + rnd) >> 7(shift_stage1_idct)
278 vqrshrn.s32 d11,q9,#shift_stage1_idct @// r6 = (a1 - b1 + rnd) >> 7(shift_stage1_idct)
279 vqrshrn.s32 d7,q13,#shift_stage1_idct @// r3 = (a3 + b3 + rnd) >> 7(shift_stage1_idct)
280 vqrshrn.s32 d10,q15,#shift_stage1_idct @// r4 = (a3 - b3 + rnd) >> 7(shift_stage1_idct)
341 vqrshrn.s32 d2,q10,#shift_stage1_idct @// r0 = (a0 + b0 + rnd) >> 7(shift_stage1_idct)
342 vqrshrn.s32 d15,q3,#shift_stage1_idct @// r7 = (a0 - b0 + rnd) >> 7(shift_stage1_idct)
[all …]
Dihevc_itrans_recon_16x16.s390 vqrshrn.s32 d30,q10,#shift_stage1_idct @// r0 = (a0 + b0 + rnd) >> 7(shift_stage1_idct)
391 vqrshrn.s32 d19,q11,#shift_stage1_idct @// r7 = (a0 - b0 + rnd) >> 7(shift_stage1_idct)
392 vqrshrn.s32 d31,q7,#shift_stage1_idct @// r2 = (a2 + b2 + rnd) >> 7(shift_stage1_idct)
393 vqrshrn.s32 d18,q13,#shift_stage1_idct @// r5 = (a2 - b2 + rnd) >> 7(shift_stage1_idct)
394 vqrshrn.s32 d12,q6,#shift_stage1_idct @// r1 = (a1 + b1 + rnd) >> 7(shift_stage1_idct)
395 vqrshrn.s32 d15,q12,#shift_stage1_idct @// r6 = (a1 - b1 + rnd) >> 7(shift_stage1_idct)
396 vqrshrn.s32 d13,q8,#shift_stage1_idct @// r3 = (a3 + b3 + rnd) >> 7(shift_stage1_idct)
397 vqrshrn.s32 d14,q14,#shift_stage1_idct @// r4 = (a3 - b3 + rnd) >> 7(shift_stage1_idct)
557 vqrshrn.s32 d18,q2,#shift_stage1_idct @// r0 = (a0 + b0 + rnd) >> 7(shift_stage1_idct)
558 vqrshrn.s32 d31,q11,#shift_stage1_idct @// r7 = (a0 - b0 + rnd) >> 7(shift_stage1_idct)
[all …]
Dihevc_itrans_recon_4x4.s173 vqrshrn.s32 d0,q7,#shift_stage1_idct @pi2_out[0] = clip_s16((e[0] + o[0] + add)>>shift) )
174 vqrshrn.s32 d1,q8,#shift_stage1_idct @pi2_out[1] = clip_s16((e[1] + o[1] + add)>>shift) )
175 vqrshrn.s32 d2,q9,#shift_stage1_idct @pi2_out[2] = clip_s16((e[0] - o[0] + add)>>shift) )
176 vqrshrn.s32 d3,q10,#shift_stage1_idct @pi2_out[3] = clip_s16((e[0] - o[0] + add)>>shift) )
204 vqrshrn.s32 d0,q7,#shift_stage2_idct @pi2_out[0] = clip_s16((e[0] + o[0] + add)>>shift) )
205 vqrshrn.s32 d1,q8,#shift_stage2_idct @pi2_out[1] = clip_s16((e[1] + o[1] + add)>>shift) )
206 vqrshrn.s32 d2,q9,#shift_stage2_idct @pi2_out[2] = clip_s16((e[0] - o[0] + add)>>shift) )
207 vqrshrn.s32 d3,q10,#shift_stage2_idct @pi2_out[3] = clip_s16((e[0] - o[0] + add)>>shift) )
Dihevc_itrans_recon_4x4_ttype1.s169 vqrshrn.s32 d14,q3,#shift_stage1_idct @ (pi2_out[0] + rounding ) >> shift_stage1_idct
170 vqrshrn.s32 d15,q4,#shift_stage1_idct @ (pi2_out[1] + rounding ) >> shift_stage1_idct
171 vqrshrn.s32 d16,q5,#shift_stage1_idct @ (pi2_out[2] + rounding ) >> shift_stage1_idct
172 vqrshrn.s32 d17,q6,#shift_stage1_idct @ (pi2_out[3] + rounding ) >> shift_stage1_idct
209 vqrshrn.s32 d0,q3,#shift_stage2_idct @ (pi2_out[0] + rounding ) >> shift_stage1_idct
210 vqrshrn.s32 d1,q4,#shift_stage2_idct @ (pi2_out[1] + rounding ) >> shift_stage1_idct
211 vqrshrn.s32 d2,q5,#shift_stage2_idct @ (pi2_out[2] + rounding ) >> shift_stage1_idct
212 vqrshrn.s32 d3,q6,#shift_stage2_idct @ (pi2_out[3] + rounding ) >> shift_stage1_idct
Dihevc_itrans_recon_32x32.s504 vqrshrn.s32 d30,q4,#shift_stage1_idct @// r0 = (a0 + b0 + rnd) >> 7(shift_stage1_idct)
505 vqrshrn.s32 d19,q5,#shift_stage1_idct @// r7 = (a0 - b0 + rnd) >> 7(shift_stage1_idct)
506 vqrshrn.s32 d31,q7,#shift_stage1_idct @// r2 = (a2 + b2 + rnd) >> 7(shift_stage1_idct)
507 vqrshrn.s32 d18,q13,#shift_stage1_idct @// r5 = (a2 - b2 + rnd) >> 7(shift_stage1_idct)
508 vqrshrn.s32 d12,q6,#shift_stage1_idct @// r1 = (a1 + b1 + rnd) >> 7(shift_stage1_idct)
509 vqrshrn.s32 d15,q12,#shift_stage1_idct @// r6 = (a1 - b1 + rnd) >> 7(shift_stage1_idct)
510 vqrshrn.s32 d13,q8,#shift_stage1_idct @// r3 = (a3 + b3 + rnd) >> 7(shift_stage1_idct)
511 vqrshrn.s32 d14,q14,#shift_stage1_idct @// r4 = (a3 - b3 + rnd) >> 7(shift_stage1_idct)
843 vqrshrn.s32 d30,q4,#shift_stage1_idct @// r0 = (a0 + b0 + rnd) >> 7(shift_stage1_idct)
844 vqrshrn.s32 d19,q5,#shift_stage1_idct @// r7 = (a0 - b0 + rnd) >> 7(shift_stage1_idct)
[all …]
/external/libmpeg2/common/arm/
Dimpeg2_idct.s528 vqrshrn.s32 d2, q10, #idct_stg1_shift @// r0 = (a0 + b0 + rnd) >> 7(IDCT_STG1_SHIFT)
529 vqrshrn.s32 d15, q3, #idct_stg1_shift @// r7 = (a0 - b0 + rnd) >> 7(IDCT_STG1_SHIFT)
530 vqrshrn.s32 d3, q12, #idct_stg1_shift @// r2 = (a2 + b2 + rnd) >> 7(IDCT_STG1_SHIFT)
531 vqrshrn.s32 d14, q11, #idct_stg1_shift @// r5 = (a2 - b2 + rnd) >> 7(IDCT_STG1_SHIFT)
532 vqrshrn.s32 d6, q14, #idct_stg1_shift @// r1 = (a1 + b1 + rnd) >> 7(IDCT_STG1_SHIFT)
533 vqrshrn.s32 d11, q9, #idct_stg1_shift @// r6 = (a1 - b1 + rnd) >> 7(IDCT_STG1_SHIFT)
534 vqrshrn.s32 d7, q13, #idct_stg1_shift @// r3 = (a3 + b3 + rnd) >> 7(IDCT_STG1_SHIFT)
535 vqrshrn.s32 d10, q15, #idct_stg1_shift @// r4 = (a3 - b3 + rnd) >> 7(IDCT_STG1_SHIFT)
600 vqrshrn.s32 d2, q10, #idct_stg1_shift @// r0 = (a0 + b0 + rnd) >> 7(IDCT_STG1_SHIFT)
601 vqrshrn.s32 d15, q3, #idct_stg1_shift @// r7 = (a0 - b0 + rnd) >> 7(IDCT_STG1_SHIFT)
[all …]
/external/swiftshader/third_party/LLVM/test/MC/ARM/
Dneont2-satshift-encoding.s135 @ CHECK: vqrshrn.s16 d16, q8, #8 @ encoding: [0xc8,0xef,0x70,0x09]
136 vqrshrn.s16 d16, q8, #8
137 @ CHECK: vqrshrn.s32 d16, q8, #16 @ encoding: [0xd0,0xef,0x70,0x09]
138 vqrshrn.s32 d16, q8, #16
139 @ CHECK: vqrshrn.s64 d16, q8, #32 @ encoding: [0xe0,0xef,0x70,0x09]
140 vqrshrn.s64 d16, q8, #32
141 @ CHECK: vqrshrn.u16 d16, q8, #8 @ encoding: [0xc8,0xff,0x70,0x09]
142 vqrshrn.u16 d16, q8, #8
143 @ CHECK: vqrshrn.u32 d16, q8, #16 @ encoding: [0xd0,0xff,0x70,0x09]
144 vqrshrn.u32 d16, q8, #16
[all …]
Dneon-satshift-encoding.s133 @ CHECK: vqrshrn.s16 d16, q8, #8 @ encoding: [0x70,0x09,0xc8,0xf2]
134 vqrshrn.s16 d16, q8, #8
135 @ CHECK: vqrshrn.s32 d16, q8, #16 @ encoding: [0x70,0x09,0xd0,0xf2]
136 vqrshrn.s32 d16, q8, #16
137 @ CHECK: vqrshrn.s64 d16, q8, #32 @ encoding: [0x70,0x09,0xe0,0xf2]
138 vqrshrn.s64 d16, q8, #32
139 @ CHECK: vqrshrn.u16 d16, q8, #8 @ encoding: [0x70,0x09,0xc8,0xf3]
140 vqrshrn.u16 d16, q8, #8
141 @ CHECK: vqrshrn.u32 d16, q8, #16 @ encoding: [0x70,0x09,0xd0,0xf3]
142 vqrshrn.u32 d16, q8, #16
[all …]
Dneon-shift-encoding.s226 @ CHECK: vqrshrn.s16 d16, q8, #4 @ encoding: [0x70,0x09,0xcc,0xf2]
227 vqrshrn.s16 d16, q8, #4
228 @ CHECK: vqrshrn.s32 d16, q8, #13 @ encoding: [0x70,0x09,0xd3,0xf2]
229 vqrshrn.s32 d16, q8, #13
230 @ CHECK: vqrshrn.s64 d16, q8, #13 @ encoding: [0x70,0x09,0xf3,0xf2]
231 vqrshrn.s64 d16, q8, #13
232 @ CHECK: vqrshrn.u16 d16, q8, #4 @ encoding: [0x70,0x09,0xcc,0xf3]
233 vqrshrn.u16 d16, q8, #4
234 @ CHECK: vqrshrn.u32 d16, q8, #13 @ encoding: [0x70,0x09,0xd3,0xf3]
235 vqrshrn.u32 d16, q8, #13
[all …]
/external/llvm/test/MC/ARM/
Dneon-satshift-encoding.s133 @ CHECK: vqrshrn.s16 d16, q8, #8 @ encoding: [0x70,0x09,0xc8,0xf2]
134 vqrshrn.s16 d16, q8, #8
135 @ CHECK: vqrshrn.s32 d16, q8, #16 @ encoding: [0x70,0x09,0xd0,0xf2]
136 vqrshrn.s32 d16, q8, #16
137 @ CHECK: vqrshrn.s64 d16, q8, #32 @ encoding: [0x70,0x09,0xe0,0xf2]
138 vqrshrn.s64 d16, q8, #32
139 @ CHECK: vqrshrn.u16 d16, q8, #8 @ encoding: [0x70,0x09,0xc8,0xf3]
140 vqrshrn.u16 d16, q8, #8
141 @ CHECK: vqrshrn.u32 d16, q8, #16 @ encoding: [0x70,0x09,0xd0,0xf3]
142 vqrshrn.u32 d16, q8, #16
[all …]
Dneont2-satshift-encoding.s135 @ CHECK: vqrshrn.s16 d16, q8, #8 @ encoding: [0xc8,0xef,0x70,0x09]
136 vqrshrn.s16 d16, q8, #8
137 @ CHECK: vqrshrn.s32 d16, q8, #16 @ encoding: [0xd0,0xef,0x70,0x09]
138 vqrshrn.s32 d16, q8, #16
139 @ CHECK: vqrshrn.s64 d16, q8, #32 @ encoding: [0xe0,0xef,0x70,0x09]
140 vqrshrn.s64 d16, q8, #32
141 @ CHECK: vqrshrn.u16 d16, q8, #8 @ encoding: [0xc8,0xff,0x70,0x09]
142 vqrshrn.u16 d16, q8, #8
143 @ CHECK: vqrshrn.u32 d16, q8, #16 @ encoding: [0xd0,0xff,0x70,0x09]
144 vqrshrn.u32 d16, q8, #16
[all …]
Dneon-shift-encoding.s353 vqrshrn.s16 d16, q8, #4
354 vqrshrn.s32 d16, q8, #13
355 vqrshrn.s64 d16, q8, #13
356 vqrshrn.u16 d16, q8, #4
357 vqrshrn.u32 d16, q8, #13
358 vqrshrn.u64 d16, q8, #13
363 @ CHECK: vqrshrn.s16 d16, q8, #4 @ encoding: [0x70,0x09,0xcc,0xf2]
364 @ CHECK: vqrshrn.s32 d16, q8, #13 @ encoding: [0x70,0x09,0xd3,0xf2]
365 @ CHECK: vqrshrn.s64 d16, q8, #13 @ encoding: [0x70,0x09,0xf3,0xf2]
366 @ CHECK: vqrshrn.u16 d16, q8, #4 @ encoding: [0x70,0x09,0xcc,0xf3]
[all …]
/external/libvpx/libvpx/vpx_dsp/arm/
Dloopfilter_16_neon.asm515 vqrshrn.u16 d18, q15, #3 ; r_op2
521 vqrshrn.u16 d19, q15, #3 ; r_op1
526 vqrshrn.u16 d20, q15, #3 ; r_op0
532 vqrshrn.u16 d21, q15, #3 ; r_oq0
538 vqrshrn.u16 d22, q15, #3 ; r_oq1
543 vqrshrn.u16 d27, q15, #3 ; r_oq2
573 vqrshrn.u16 d16, q15, #4 ; w_op6
577 vqrshrn.u16 d24, q15, #4 ; w_op5
583 vqrshrn.u16 d25, q15, #4 ; w_op4
589 vqrshrn.u16 d26, q15, #4 ; w_op3
[all …]
/external/libavc/common/arm/
Dih264_iquant_itrans_recon_a9.s157 vqrshrn.s32 d0, q0, #0x4 @ D0 = c[i] = ((q[i] + 32) >> 4) where i = 0..3
158 vqrshrn.s32 d1, q1, #0x4 @ D1 = c[i] = ((q[i] + 32) >> 4) where i = 4..7
159 vqrshrn.s32 d2, q2, #0x4 @ D2 = c[i] = ((q[i] + 32) >> 4) where i = 8..11
160 vqrshrn.s32 d3, q3, #0x4 @ D3 = c[i] = ((q[i] + 32) >> 4) where i = 12..15
330 vqrshrn.s32 d0, q0, #0x4 @ D0 = c[i] = ((q[i] + 32) >> 4) where i = 0..3
331 vqrshrn.s32 d1, q1, #0x4 @ D1 = c[i] = ((q[i] + 32) >> 4) where i = 4..7
332 vqrshrn.s32 d2, q2, #0x4 @ D2 = c[i] = ((q[i] + 32) >> 4) where i = 8..11
333 vqrshrn.s32 d3, q3, #0x4 @ D3 = c[i] = ((q[i] + 32) >> 4) where i = 12..15
526 vqrshrn.s32 d0, q0, #0x6 @ D0 = c[i] = ((q[i] + 32) >> 6) where i = 0..3
527 vqrshrn.s32 d1, q1, #0x6 @ D1 = c[i] = ((q[i] + 32) >> 6) where i = 4..7
[all …]
Dih264_ihadamard_scaling_a9.s151 vqrshrn.s32 d0, q0, #0x6 @ D0 = c[i] = ((q[i] + 32) >> 4) where i = 0..3
152 vqrshrn.s32 d1, q1, #0x6 @ D1 = c[i] = ((q[i] + 32) >> 4) where i = 4..7
153 vqrshrn.s32 d2, q2, #0x6 @ D2 = c[i] = ((q[i] + 32) >> 4) where i = 8..11
154 vqrshrn.s32 d3, q3, #0x6 @ D3 = c[i] = ((q[i] + 32) >> 4) where i = 12..15
Dih264_deblk_luma_a9.s141 vqrshrn.s16 d24, q12, #3 @
142 vqrshrn.s16 d25, q13, #3 @Q12 = i_macro = (((q0 - p0)<<2) + (p1 - q1) + 4)>>3
/external/swiftshader/third_party/LLVM/test/CodeGen/ARM/
Dvqshrn.ll89 ;CHECK: vqrshrn.s16
97 ;CHECK: vqrshrn.s32
105 ;CHECK: vqrshrn.s64
113 ;CHECK: vqrshrn.u16
121 ;CHECK: vqrshrn.u32
129 ;CHECK: vqrshrn.u64
Dneon_shift.ll6 ; CHECK: vqrshrn.s32 d{{[0-9]+}}, q{{[0-9]*}}, #13
/external/libavc/encoder/arm/
Dih264e_evaluate_intra_chroma_modes_a9q.s132 vqrshrn.u16 d14, q7, #3
133 vqrshrn.u16 d15, q4, #2
134 vqrshrn.u16 d16, q5, #2
142 vqrshrn.u16 d16, q5, #2
150 vqrshrn.u16 d16, q4, #2
/external/llvm/test/CodeGen/ARM/
Dvqshrn.ll89 ;CHECK: vqrshrn.s16
97 ;CHECK: vqrshrn.s32
105 ;CHECK: vqrshrn.s64
113 ;CHECK: vqrshrn.u16
121 ;CHECK: vqrshrn.u32
129 ;CHECK: vqrshrn.u64
Dneon_shift.ll6 ; CHECK: vqrshrn.s32 d{{[0-9]+}}, q{{[0-9]*}}, #13
/external/llvm/test/CodeGen/AArch64/
Darm64-neon-simd-shift.ll501 %vqrshrn = tail call <8 x i8> @llvm.aarch64.neon.sqrshrn.v8i8(<8 x i16> %b, i32 3)
503 %2 = bitcast <8 x i8> %vqrshrn to <1 x i64>
512 %vqrshrn = tail call <4 x i16> @llvm.aarch64.neon.sqrshrn.v4i16(<4 x i32> %b, i32 9)
514 %2 = bitcast <4 x i16> %vqrshrn to <1 x i64>
524 %vqrshrn = tail call <2 x i32> @llvm.aarch64.neon.sqrshrn.v2i32(<2 x i64> %b, i32 19)
525 %2 = bitcast <2 x i32> %vqrshrn to <1 x i64>
534 %vqrshrn = tail call <8 x i8> @llvm.aarch64.neon.uqrshrn.v8i8(<8 x i16> %b, i32 3)
536 %2 = bitcast <8 x i8> %vqrshrn to <1 x i64>
545 %vqrshrn = tail call <4 x i16> @llvm.aarch64.neon.uqrshrn.v4i16(<4 x i32> %b, i32 9)
547 %2 = bitcast <4 x i16> %vqrshrn to <1 x i64>
[all …]
/external/swiftshader/third_party/LLVM/test/MC/Disassembler/ARM/
Dneon.txt1113 # CHECK: vqrshrn.s16 d16, q8, #8
1115 # CHECK: vqrshrn.s32 d16, q8, #16
1117 # CHECK: vqrshrn.s64 d16, q8, #32
1119 # CHECK: vqrshrn.u16 d16, q8, #8
1121 # CHECK: vqrshrn.u32 d16, q8, #16
1123 # CHECK: vqrshrn.u64 d16, q8, #32
1355 # CHECK: vqrshrn.s16 d16, q8, #4
1357 # CHECK: vqrshrn.s32 d16, q8, #13
1359 # CHECK: vqrshrn.s64 d16, q8, #13
1361 # CHECK: vqrshrn.u16 d16, q8, #4
[all …]
/external/llvm/test/MC/Disassembler/ARM/
Dneon.txt1113 # CHECK: vqrshrn.s16 d16, q8, #8
1115 # CHECK: vqrshrn.s32 d16, q8, #16
1117 # CHECK: vqrshrn.s64 d16, q8, #32
1119 # CHECK: vqrshrn.u16 d16, q8, #8
1121 # CHECK: vqrshrn.u32 d16, q8, #16
1123 # CHECK: vqrshrn.u64 d16, q8, #32
1355 # CHECK: vqrshrn.s16 d16, q8, #4
1357 # CHECK: vqrshrn.s32 d16, q8, #13
1359 # CHECK: vqrshrn.s64 d16, q8, #13
1361 # CHECK: vqrshrn.u16 d16, q8, #4
[all …]
/external/libjpeg-turbo/simd/
Djsimd_arm_neon.S506 vqrshrn.s16 d16, q8, #2
507 vqrshrn.s16 d17, q9, #2
508 vqrshrn.s16 d18, q10, #2
509 vqrshrn.s16 d19, q11, #2
511 vqrshrn.s16 d20, q12, #2
514 vqrshrn.s16 d21, q13, #2
515 vqrshrn.s16 d22, q14, #2
517 vqrshrn.s16 d23, q15, #2

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