1 /* 2 * Copyright (C) 2015 The Android Open Source Project 3 * 4 * Licensed under the Apache License, Version 2.0 (the "License"); 5 * you may not use this file except in compliance with the License. 6 * You may obtain a copy of the License at 7 * 8 * http://www.apache.org/licenses/LICENSE-2.0 9 * 10 * Unless required by applicable law or agreed to in writing, software 11 * distributed under the License is distributed on an "AS IS" BASIS, 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 * See the License for the specific language governing permissions and 14 * limitations under the License. 15 */ 16 17 #ifndef ART_COMPILER_DEBUG_DWARF_REGISTER_H_ 18 #define ART_COMPILER_DEBUG_DWARF_REGISTER_H_ 19 20 namespace art { 21 namespace dwarf { 22 23 // Represents DWARF register. 24 class Reg { 25 public: Reg(int reg_num)26 explicit Reg(int reg_num) : num_(reg_num) { } num()27 int num() const { return num_; } 28 29 // TODO: Arm S0–S31 register mapping is obsolescent. 30 // We should use VFP-v3/Neon D0-D31 mapping instead. 31 // However, D0 is aliased to pair of S0 and S1, so using that 32 // mapping we cannot easily say S0 is spilled and S1 is not. 33 // There are ways around this in DWARF but they are complex. 34 // It would be much simpler to always spill whole D registers. 35 // Arm64 mapping is correct since we already do this there. 36 // libunwind might struggle with the new mapping as well. 37 ArmCore(int num)38 static Reg ArmCore(int num) { return Reg(num); } // R0-R15. ArmFp(int num)39 static Reg ArmFp(int num) { return Reg(64 + num); } // S0–S31. ArmDp(int num)40 static Reg ArmDp(int num) { return Reg(256 + num); } // D0–D31. Arm64Core(int num)41 static Reg Arm64Core(int num) { return Reg(num); } // X0-X31. Arm64Fp(int num)42 static Reg Arm64Fp(int num) { return Reg(64 + num); } // V0-V31. MipsCore(int num)43 static Reg MipsCore(int num) { return Reg(num); } Mips64Core(int num)44 static Reg Mips64Core(int num) { return Reg(num); } MipsFp(int num)45 static Reg MipsFp(int num) { return Reg(32 + num); } Mips64Fp(int num)46 static Reg Mips64Fp(int num) { return Reg(32 + num); } X86Core(int num)47 static Reg X86Core(int num) { return Reg(num); } X86Fp(int num)48 static Reg X86Fp(int num) { return Reg(21 + num); } X86_64Core(int num)49 static Reg X86_64Core(int num) { 50 static const int map[8] = {0, 2, 1, 3, 7, 6, 4, 5}; 51 return Reg(num < 8 ? map[num] : num); 52 } X86_64Fp(int num)53 static Reg X86_64Fp(int num) { return Reg(17 + num); } 54 55 private: 56 int num_; 57 }; 58 59 } // namespace dwarf 60 } // namespace art 61 62 #endif // ART_COMPILER_DEBUG_DWARF_REGISTER_H_ 63