1/* 2 * This file was generated automatically by gen-mterp.py for 'mips64'. 3 * 4 * --> DO NOT EDIT <-- 5 */ 6 7/* File: mips64/header.S */ 8/* 9 * Copyright (C) 2016 The Android Open Source Project 10 * 11 * Licensed under the Apache License, Version 2.0 (the "License"); 12 * you may not use this file except in compliance with the License. 13 * You may obtain a copy of the License at 14 * 15 * http://www.apache.org/licenses/LICENSE-2.0 16 * 17 * Unless required by applicable law or agreed to in writing, software 18 * distributed under the License is distributed on an "AS IS" BASIS, 19 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 20 * See the License for the specific language governing permissions and 21 * limitations under the License. 22 */ 23 24#include <machine/regdef.h> 25 26/* TODO: add the missing file and use its FP register definitions. */ 27/* #include <machine/fpregdef.h> */ 28/* FP register definitions */ 29#define f0 $f0 30#define f1 $f1 31#define f2 $f2 32#define f3 $f3 33#define f12 $f12 34#define f13 $f13 35 36/* 37 * It looks like the GNU assembler currently does not support the blec and bgtc 38 * idioms, which should translate into bgec and bltc respectively with swapped 39 * left and right register operands. 40 * TODO: remove these macros when the assembler is fixed. 41 */ 42.macro blec lreg, rreg, target 43 bgec \rreg, \lreg, \target 44.endm 45.macro bgtc lreg, rreg, target 46 bltc \rreg, \lreg, \target 47.endm 48 49/* 50Mterp and MIPS64 notes: 51 52The following registers have fixed assignments: 53 54 reg nick purpose 55 s0 rPC interpreted program counter, used for fetching instructions 56 s1 rFP interpreted frame pointer, used for accessing locals and args 57 s2 rSELF self (Thread) pointer 58 s3 rINST first 16-bit code unit of current instruction 59 s4 rIBASE interpreted instruction base pointer, used for computed goto 60 s5 rREFS base of object references in shadow frame (ideally, we'll get rid of this later). 61 s6 rPROFILE jit profile hotness countdown 62*/ 63 64/* During bringup, we'll use the shadow frame model instead of rFP */ 65/* single-purpose registers, given names for clarity */ 66#define rPC s0 67#define rFP s1 68#define rSELF s2 69#define rINST s3 70#define rIBASE s4 71#define rREFS s5 72#define rPROFILE s6 73 74/* 75 * This is a #include, not a %include, because we want the C pre-processor 76 * to expand the macros into assembler assignment statements. 77 */ 78#include "asm_support.h" 79 80/* 81 * Instead of holding a pointer to the shadow frame, we keep rFP at the base of the vregs. So, 82 * to access other shadow frame fields, we need to use a backwards offset. Define those here. 83 */ 84#define OFF_FP(a) (a - SHADOWFRAME_VREGS_OFFSET) 85#define OFF_FP_NUMBER_OF_VREGS OFF_FP(SHADOWFRAME_NUMBER_OF_VREGS_OFFSET) 86#define OFF_FP_DEX_PC OFF_FP(SHADOWFRAME_DEX_PC_OFFSET) 87#define OFF_FP_LINK OFF_FP(SHADOWFRAME_LINK_OFFSET) 88#define OFF_FP_METHOD OFF_FP(SHADOWFRAME_METHOD_OFFSET) 89#define OFF_FP_RESULT_REGISTER OFF_FP(SHADOWFRAME_RESULT_REGISTER_OFFSET) 90#define OFF_FP_DEX_PC_PTR OFF_FP(SHADOWFRAME_DEX_PC_PTR_OFFSET) 91#define OFF_FP_CODE_ITEM OFF_FP(SHADOWFRAME_CODE_ITEM_OFFSET) 92#define OFF_FP_SHADOWFRAME OFF_FP(0) 93 94#define MTERP_PROFILE_BRANCHES 1 95#define MTERP_LOGGING 0 96 97/* 98 * "export" the PC to dex_pc field in the shadow frame, f/b/o future exception objects. Must 99 * be done *before* something throws. 100 * 101 * It's okay to do this more than once. 102 * 103 * NOTE: the fast interpreter keeps track of dex pc as a direct pointer to the mapped 104 * dex byte codes. However, the rest of the runtime expects dex pc to be an instruction 105 * offset into the code_items_[] array. For effiency, we will "export" the 106 * current dex pc as a direct pointer using the EXPORT_PC macro, and rely on GetDexPC 107 * to convert to a dex pc when needed. 108 */ 109.macro EXPORT_PC 110 sd rPC, OFF_FP_DEX_PC_PTR(rFP) 111.endm 112 113/* 114 * Refresh handler table. 115 */ 116.macro REFRESH_IBASE 117 ld rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) 118.endm 119 120/* 121 * Fetch the next instruction from rPC into rINST. Does not advance rPC. 122 */ 123.macro FETCH_INST 124 lhu rINST, 0(rPC) 125.endm 126 127/* Advance rPC by some number of code units. */ 128.macro ADVANCE count 129 daddu rPC, rPC, (\count) * 2 130.endm 131 132/* 133 * Fetch the next instruction from an offset specified by _reg and advance xPC. 134 * xPC to point to the next instruction. "_reg" must specify the distance 135 * in bytes, *not* 16-bit code units, and may be a signed value. Must not set flags. 136 * 137 */ 138.macro FETCH_ADVANCE_INST_RB reg 139 daddu rPC, rPC, \reg 140 FETCH_INST 141.endm 142 143/* 144 * Fetch the next instruction from the specified offset. Advances rPC 145 * to point to the next instruction. 146 * 147 * This must come AFTER anything that can throw an exception, or the 148 * exception catch may miss. (This also implies that it must come after 149 * EXPORT_PC.) 150 */ 151.macro FETCH_ADVANCE_INST count 152 ADVANCE \count 153 FETCH_INST 154.endm 155 156/* 157 * Similar to FETCH_ADVANCE_INST, but does not update rPC. Used to load 158 * rINST ahead of possible exception point. Be sure to manually advance rPC 159 * later. 160 */ 161.macro PREFETCH_INST count 162 lhu rINST, ((\count) * 2)(rPC) 163.endm 164 165/* 166 * Put the instruction's opcode field into the specified register. 167 */ 168.macro GET_INST_OPCODE reg 169 and \reg, rINST, 255 170.endm 171 172/* 173 * Begin executing the opcode in _reg. 174 */ 175.macro GOTO_OPCODE reg 176 .set noat 177 sll AT, \reg, 7 178 daddu AT, rIBASE, AT 179 jic AT, 0 180 .set at 181.endm 182 183/* 184 * Get/set the 32-bit value from a Dalvik register. 185 * Note, GET_VREG does sign extension to 64 bits while 186 * GET_VREG_U does zero extension to 64 bits. 187 * One is useful for arithmetic while the other is 188 * useful for storing the result value as 64-bit. 189 */ 190.macro GET_VREG reg, vreg 191 .set noat 192 dlsa AT, \vreg, rFP, 2 193 lw \reg, 0(AT) 194 .set at 195.endm 196.macro GET_VREG_U reg, vreg 197 .set noat 198 dlsa AT, \vreg, rFP, 2 199 lwu \reg, 0(AT) 200 .set at 201.endm 202.macro GET_VREG_FLOAT reg, vreg 203 .set noat 204 dlsa AT, \vreg, rFP, 2 205 lwc1 \reg, 0(AT) 206 .set at 207.endm 208.macro SET_VREG reg, vreg 209 .set noat 210 dlsa AT, \vreg, rFP, 2 211 sw \reg, 0(AT) 212 dlsa AT, \vreg, rREFS, 2 213 sw zero, 0(AT) 214 .set at 215.endm 216.macro SET_VREG_OBJECT reg, vreg 217 .set noat 218 dlsa AT, \vreg, rFP, 2 219 sw \reg, 0(AT) 220 dlsa AT, \vreg, rREFS, 2 221 sw \reg, 0(AT) 222 .set at 223.endm 224.macro SET_VREG_FLOAT reg, vreg 225 .set noat 226 dlsa AT, \vreg, rFP, 2 227 swc1 \reg, 0(AT) 228 dlsa AT, \vreg, rREFS, 2 229 sw zero, 0(AT) 230 .set at 231.endm 232 233/* 234 * Get/set the 64-bit value from a Dalvik register. 235 * Avoid unaligned memory accesses. 236 * Note, SET_VREG_WIDE clobbers the register containing the value being stored. 237 * Note, SET_VREG_DOUBLE clobbers the register containing the Dalvik register number. 238 */ 239.macro GET_VREG_WIDE reg, vreg 240 .set noat 241 dlsa AT, \vreg, rFP, 2 242 lw \reg, 0(AT) 243 lw AT, 4(AT) 244 dinsu \reg, AT, 32, 32 245 .set at 246.endm 247.macro GET_VREG_DOUBLE reg, vreg 248 .set noat 249 dlsa AT, \vreg, rFP, 2 250 lwc1 \reg, 0(AT) 251 lw AT, 4(AT) 252 mthc1 AT, \reg 253 .set at 254.endm 255.macro SET_VREG_WIDE reg, vreg 256 .set noat 257 dlsa AT, \vreg, rFP, 2 258 sw \reg, 0(AT) 259 drotr32 \reg, \reg, 0 260 sw \reg, 4(AT) 261 dlsa AT, \vreg, rREFS, 2 262 sw zero, 0(AT) 263 sw zero, 4(AT) 264 .set at 265.endm 266.macro SET_VREG_DOUBLE reg, vreg 267 .set noat 268 dlsa AT, \vreg, rREFS, 2 269 sw zero, 0(AT) 270 sw zero, 4(AT) 271 dlsa AT, \vreg, rFP, 2 272 swc1 \reg, 0(AT) 273 mfhc1 \vreg, \reg 274 sw \vreg, 4(AT) 275 .set at 276.endm 277 278/* 279 * On-stack offsets for spilling/unspilling callee-saved registers 280 * and the frame size. 281 */ 282#define STACK_OFFSET_RA 0 283#define STACK_OFFSET_GP 8 284#define STACK_OFFSET_S0 16 285#define STACK_OFFSET_S1 24 286#define STACK_OFFSET_S2 32 287#define STACK_OFFSET_S3 40 288#define STACK_OFFSET_S4 48 289#define STACK_OFFSET_S5 56 290#define STACK_OFFSET_S6 64 291#define STACK_SIZE 80 /* needs 16 byte alignment */ 292 293/* Constants for float/double_to_int/long conversions */ 294#define INT_MIN 0x80000000 295#define INT_MIN_AS_FLOAT 0xCF000000 296#define INT_MIN_AS_DOUBLE 0xC1E0000000000000 297#define LONG_MIN 0x8000000000000000 298#define LONG_MIN_AS_FLOAT 0xDF000000 299#define LONG_MIN_AS_DOUBLE 0xC3E0000000000000 300 301/* File: mips64/entry.S */ 302/* 303 * Copyright (C) 2016 The Android Open Source Project 304 * 305 * Licensed under the Apache License, Version 2.0 (the "License"); 306 * you may not use this file except in compliance with the License. 307 * You may obtain a copy of the License at 308 * 309 * http://www.apache.org/licenses/LICENSE-2.0 310 * 311 * Unless required by applicable law or agreed to in writing, software 312 * distributed under the License is distributed on an "AS IS" BASIS, 313 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 314 * See the License for the specific language governing permissions and 315 * limitations under the License. 316 */ 317 318/* 319 * Interpreter entry point. 320 */ 321 322 .set reorder 323 324 .text 325 .global ExecuteMterpImpl 326 .type ExecuteMterpImpl, %function 327 .balign 16 328/* 329 * On entry: 330 * a0 Thread* self 331 * a1 code_item 332 * a2 ShadowFrame 333 * a3 JValue* result_register 334 * 335 */ 336ExecuteMterpImpl: 337 .cfi_startproc 338 .cpsetup t9, t8, ExecuteMterpImpl 339 340 .cfi_def_cfa sp, 0 341 daddu sp, sp, -STACK_SIZE 342 .cfi_adjust_cfa_offset STACK_SIZE 343 344 sd t8, STACK_OFFSET_GP(sp) 345 .cfi_rel_offset 28, STACK_OFFSET_GP 346 sd ra, STACK_OFFSET_RA(sp) 347 .cfi_rel_offset 31, STACK_OFFSET_RA 348 349 sd s0, STACK_OFFSET_S0(sp) 350 .cfi_rel_offset 16, STACK_OFFSET_S0 351 sd s1, STACK_OFFSET_S1(sp) 352 .cfi_rel_offset 17, STACK_OFFSET_S1 353 sd s2, STACK_OFFSET_S2(sp) 354 .cfi_rel_offset 18, STACK_OFFSET_S2 355 sd s3, STACK_OFFSET_S3(sp) 356 .cfi_rel_offset 19, STACK_OFFSET_S3 357 sd s4, STACK_OFFSET_S4(sp) 358 .cfi_rel_offset 20, STACK_OFFSET_S4 359 sd s5, STACK_OFFSET_S5(sp) 360 .cfi_rel_offset 21, STACK_OFFSET_S5 361 sd s6, STACK_OFFSET_S6(sp) 362 .cfi_rel_offset 22, STACK_OFFSET_S6 363 364 /* Remember the return register */ 365 sd a3, SHADOWFRAME_RESULT_REGISTER_OFFSET(a2) 366 367 /* Remember the code_item */ 368 sd a1, SHADOWFRAME_CODE_ITEM_OFFSET(a2) 369 370 /* set up "named" registers */ 371 move rSELF, a0 372 daddu rFP, a2, SHADOWFRAME_VREGS_OFFSET 373 lw v0, SHADOWFRAME_NUMBER_OF_VREGS_OFFSET(a2) 374 dlsa rREFS, v0, rFP, 2 375 daddu rPC, a1, CODEITEM_INSNS_OFFSET 376 lw v0, SHADOWFRAME_DEX_PC_OFFSET(a2) 377 dlsa rPC, v0, rPC, 1 378 EXPORT_PC 379 380 /* Starting ibase */ 381 REFRESH_IBASE 382 383 /* Set up for backwards branches & osr profiling */ 384 ld a0, OFF_FP_METHOD(rFP) 385 daddu a1, rFP, OFF_FP_SHADOWFRAME 386 jal MterpSetUpHotnessCountdown 387 move rPROFILE, v0 # Starting hotness countdown to rPROFILE 388 389 /* start executing the instruction at rPC */ 390 FETCH_INST 391 GET_INST_OPCODE v0 392 GOTO_OPCODE v0 393 394 /* NOTE: no fallthrough */ 395 396 397 .global artMterpAsmInstructionStart 398 .type artMterpAsmInstructionStart, %function 399artMterpAsmInstructionStart = .L_op_nop 400 .text 401 402/* ------------------------------ */ 403 .balign 128 404.L_op_nop: /* 0x00 */ 405/* File: mips64/op_nop.S */ 406 FETCH_ADVANCE_INST 1 # advance rPC, load rINST 407 GET_INST_OPCODE v0 # extract opcode from rINST 408 GOTO_OPCODE v0 # jump to next instruction 409 410/* ------------------------------ */ 411 .balign 128 412.L_op_move: /* 0x01 */ 413/* File: mips64/op_move.S */ 414 /* for move, move-object, long-to-int */ 415 /* op vA, vB */ 416 ext a2, rINST, 8, 4 # a2 <- A 417 ext a3, rINST, 12, 4 # a3 <- B 418 FETCH_ADVANCE_INST 1 # advance rPC, load rINST 419 GET_VREG a0, a3 # a0 <- vB 420 GET_INST_OPCODE v0 # extract opcode from rINST 421 .if 0 422 SET_VREG_OBJECT a0, a2 # vA <- vB 423 .else 424 SET_VREG a0, a2 # vA <- vB 425 .endif 426 GOTO_OPCODE v0 # jump to next instruction 427 428/* ------------------------------ */ 429 .balign 128 430.L_op_move_from16: /* 0x02 */ 431/* File: mips64/op_move_from16.S */ 432 /* for: move/from16, move-object/from16 */ 433 /* op vAA, vBBBB */ 434 lhu a3, 2(rPC) # a3 <- BBBB 435 srl a2, rINST, 8 # a2 <- AA 436 FETCH_ADVANCE_INST 2 # advance rPC, load rINST 437 GET_VREG a0, a3 # a0 <- vBBBB 438 GET_INST_OPCODE v0 # extract opcode from rINST 439 .if 0 440 SET_VREG_OBJECT a0, a2 # vAA <- vBBBB 441 .else 442 SET_VREG a0, a2 # vAA <- vBBBB 443 .endif 444 GOTO_OPCODE v0 # jump to next instruction 445 446/* ------------------------------ */ 447 .balign 128 448.L_op_move_16: /* 0x03 */ 449/* File: mips64/op_move_16.S */ 450 /* for: move/16, move-object/16 */ 451 /* op vAAAA, vBBBB */ 452 lhu a3, 4(rPC) # a3 <- BBBB 453 lhu a2, 2(rPC) # a2 <- AAAA 454 FETCH_ADVANCE_INST 3 # advance rPC, load rINST 455 GET_VREG a0, a3 # a0 <- vBBBB 456 GET_INST_OPCODE v0 # extract opcode from rINST 457 .if 0 458 SET_VREG_OBJECT a0, a2 # vAAAA <- vBBBB 459 .else 460 SET_VREG a0, a2 # vAAAA <- vBBBB 461 .endif 462 GOTO_OPCODE v0 # jump to next instruction 463 464/* ------------------------------ */ 465 .balign 128 466.L_op_move_wide: /* 0x04 */ 467/* File: mips64/op_move_wide.S */ 468 /* move-wide vA, vB */ 469 /* NOTE: regs can overlap, e.g. "move v6,v7" or "move v7,v6" */ 470 ext a3, rINST, 12, 4 # a3 <- B 471 ext a2, rINST, 8, 4 # a2 <- A 472 GET_VREG_WIDE a0, a3 # a0 <- vB 473 FETCH_ADVANCE_INST 1 # advance rPC, load rINST 474 GET_INST_OPCODE v0 # extract opcode from rINST 475 SET_VREG_WIDE a0, a2 # vA <- vB 476 GOTO_OPCODE v0 # jump to next instruction 477 478/* ------------------------------ */ 479 .balign 128 480.L_op_move_wide_from16: /* 0x05 */ 481/* File: mips64/op_move_wide_from16.S */ 482 /* move-wide/from16 vAA, vBBBB */ 483 /* NOTE: regs can overlap, e.g. "move v6,v7" or "move v7,v6" */ 484 lhu a3, 2(rPC) # a3 <- BBBB 485 srl a2, rINST, 8 # a2 <- AA 486 GET_VREG_WIDE a0, a3 # a0 <- vBBBB 487 FETCH_ADVANCE_INST 2 # advance rPC, load rINST 488 GET_INST_OPCODE v0 # extract opcode from rINST 489 SET_VREG_WIDE a0, a2 # vAA <- vBBBB 490 GOTO_OPCODE v0 # jump to next instruction 491 492/* ------------------------------ */ 493 .balign 128 494.L_op_move_wide_16: /* 0x06 */ 495/* File: mips64/op_move_wide_16.S */ 496 /* move-wide/16 vAAAA, vBBBB */ 497 /* NOTE: regs can overlap, e.g. "move v6,v7" or "move v7,v6" */ 498 lhu a3, 4(rPC) # a3 <- BBBB 499 lhu a2, 2(rPC) # a2 <- AAAA 500 GET_VREG_WIDE a0, a3 # a0 <- vBBBB 501 FETCH_ADVANCE_INST 3 # advance rPC, load rINST 502 GET_INST_OPCODE v0 # extract opcode from rINST 503 SET_VREG_WIDE a0, a2 # vAAAA <- vBBBB 504 GOTO_OPCODE v0 # jump to next instruction 505 506/* ------------------------------ */ 507 .balign 128 508.L_op_move_object: /* 0x07 */ 509/* File: mips64/op_move_object.S */ 510/* File: mips64/op_move.S */ 511 /* for move, move-object, long-to-int */ 512 /* op vA, vB */ 513 ext a2, rINST, 8, 4 # a2 <- A 514 ext a3, rINST, 12, 4 # a3 <- B 515 FETCH_ADVANCE_INST 1 # advance rPC, load rINST 516 GET_VREG a0, a3 # a0 <- vB 517 GET_INST_OPCODE v0 # extract opcode from rINST 518 .if 1 519 SET_VREG_OBJECT a0, a2 # vA <- vB 520 .else 521 SET_VREG a0, a2 # vA <- vB 522 .endif 523 GOTO_OPCODE v0 # jump to next instruction 524 525 526/* ------------------------------ */ 527 .balign 128 528.L_op_move_object_from16: /* 0x08 */ 529/* File: mips64/op_move_object_from16.S */ 530/* File: mips64/op_move_from16.S */ 531 /* for: move/from16, move-object/from16 */ 532 /* op vAA, vBBBB */ 533 lhu a3, 2(rPC) # a3 <- BBBB 534 srl a2, rINST, 8 # a2 <- AA 535 FETCH_ADVANCE_INST 2 # advance rPC, load rINST 536 GET_VREG a0, a3 # a0 <- vBBBB 537 GET_INST_OPCODE v0 # extract opcode from rINST 538 .if 1 539 SET_VREG_OBJECT a0, a2 # vAA <- vBBBB 540 .else 541 SET_VREG a0, a2 # vAA <- vBBBB 542 .endif 543 GOTO_OPCODE v0 # jump to next instruction 544 545 546/* ------------------------------ */ 547 .balign 128 548.L_op_move_object_16: /* 0x09 */ 549/* File: mips64/op_move_object_16.S */ 550/* File: mips64/op_move_16.S */ 551 /* for: move/16, move-object/16 */ 552 /* op vAAAA, vBBBB */ 553 lhu a3, 4(rPC) # a3 <- BBBB 554 lhu a2, 2(rPC) # a2 <- AAAA 555 FETCH_ADVANCE_INST 3 # advance rPC, load rINST 556 GET_VREG a0, a3 # a0 <- vBBBB 557 GET_INST_OPCODE v0 # extract opcode from rINST 558 .if 1 559 SET_VREG_OBJECT a0, a2 # vAAAA <- vBBBB 560 .else 561 SET_VREG a0, a2 # vAAAA <- vBBBB 562 .endif 563 GOTO_OPCODE v0 # jump to next instruction 564 565 566/* ------------------------------ */ 567 .balign 128 568.L_op_move_result: /* 0x0a */ 569/* File: mips64/op_move_result.S */ 570 /* for: move-result, move-result-object */ 571 /* op vAA */ 572 srl a2, rINST, 8 # a2 <- AA 573 FETCH_ADVANCE_INST 1 # advance rPC, load rINST 574 ld a0, OFF_FP_RESULT_REGISTER(rFP) # get pointer to result JType 575 lw a0, 0(a0) # a0 <- result.i 576 GET_INST_OPCODE v0 # extract opcode from rINST 577 .if 0 578 SET_VREG_OBJECT a0, a2 # vAA <- result 579 .else 580 SET_VREG a0, a2 # vAA <- result 581 .endif 582 GOTO_OPCODE v0 # jump to next instruction 583 584/* ------------------------------ */ 585 .balign 128 586.L_op_move_result_wide: /* 0x0b */ 587/* File: mips64/op_move_result_wide.S */ 588 /* for: move-result-wide */ 589 /* op vAA */ 590 srl a2, rINST, 8 # a2 <- AA 591 FETCH_ADVANCE_INST 1 # advance rPC, load rINST 592 ld a0, OFF_FP_RESULT_REGISTER(rFP) # get pointer to result JType 593 ld a0, 0(a0) # a0 <- result.j 594 GET_INST_OPCODE v0 # extract opcode from rINST 595 SET_VREG_WIDE a0, a2 # vAA <- result 596 GOTO_OPCODE v0 # jump to next instruction 597 598/* ------------------------------ */ 599 .balign 128 600.L_op_move_result_object: /* 0x0c */ 601/* File: mips64/op_move_result_object.S */ 602/* File: mips64/op_move_result.S */ 603 /* for: move-result, move-result-object */ 604 /* op vAA */ 605 srl a2, rINST, 8 # a2 <- AA 606 FETCH_ADVANCE_INST 1 # advance rPC, load rINST 607 ld a0, OFF_FP_RESULT_REGISTER(rFP) # get pointer to result JType 608 lw a0, 0(a0) # a0 <- result.i 609 GET_INST_OPCODE v0 # extract opcode from rINST 610 .if 1 611 SET_VREG_OBJECT a0, a2 # vAA <- result 612 .else 613 SET_VREG a0, a2 # vAA <- result 614 .endif 615 GOTO_OPCODE v0 # jump to next instruction 616 617 618/* ------------------------------ */ 619 .balign 128 620.L_op_move_exception: /* 0x0d */ 621/* File: mips64/op_move_exception.S */ 622 /* move-exception vAA */ 623 srl a2, rINST, 8 # a2 <- AA 624 ld a0, THREAD_EXCEPTION_OFFSET(rSELF) # load exception obj 625 FETCH_ADVANCE_INST 1 # advance rPC, load rINST 626 SET_VREG_OBJECT a0, a2 # vAA <- exception obj 627 GET_INST_OPCODE v0 # extract opcode from rINST 628 sd zero, THREAD_EXCEPTION_OFFSET(rSELF) # clear exception 629 GOTO_OPCODE v0 # jump to next instruction 630 631/* ------------------------------ */ 632 .balign 128 633.L_op_return_void: /* 0x0e */ 634/* File: mips64/op_return_void.S */ 635 .extern MterpThreadFenceForConstructor 636 .extern MterpSuspendCheck 637 jal MterpThreadFenceForConstructor 638 lw ra, THREAD_FLAGS_OFFSET(rSELF) 639 move a0, rSELF 640 and ra, ra, THREAD_SUSPEND_OR_CHECKPOINT_REQUEST 641 beqzc ra, 1f 642 jal MterpSuspendCheck # (self) 6431: 644 li a0, 0 645 b MterpReturn 646 647/* ------------------------------ */ 648 .balign 128 649.L_op_return: /* 0x0f */ 650/* File: mips64/op_return.S */ 651 /* 652 * Return a 32-bit value. 653 * 654 * for: return (sign-extend), return-object (zero-extend) 655 */ 656 /* op vAA */ 657 .extern MterpThreadFenceForConstructor 658 .extern MterpSuspendCheck 659 jal MterpThreadFenceForConstructor 660 lw ra, THREAD_FLAGS_OFFSET(rSELF) 661 move a0, rSELF 662 and ra, ra, THREAD_SUSPEND_OR_CHECKPOINT_REQUEST 663 beqzc ra, 1f 664 jal MterpSuspendCheck # (self) 6651: 666 srl a2, rINST, 8 # a2 <- AA 667 GET_VREG a0, a2 # a0 <- vAA 668 b MterpReturn 669 670/* ------------------------------ */ 671 .balign 128 672.L_op_return_wide: /* 0x10 */ 673/* File: mips64/op_return_wide.S */ 674 /* 675 * Return a 64-bit value. 676 */ 677 /* return-wide vAA */ 678 /* op vAA */ 679 .extern MterpThreadFenceForConstructor 680 .extern MterpSuspendCheck 681 jal MterpThreadFenceForConstructor 682 lw ra, THREAD_FLAGS_OFFSET(rSELF) 683 move a0, rSELF 684 and ra, ra, THREAD_SUSPEND_OR_CHECKPOINT_REQUEST 685 beqzc ra, 1f 686 jal MterpSuspendCheck # (self) 6871: 688 srl a2, rINST, 8 # a2 <- AA 689 GET_VREG_WIDE a0, a2 # a0 <- vAA 690 b MterpReturn 691 692/* ------------------------------ */ 693 .balign 128 694.L_op_return_object: /* 0x11 */ 695/* File: mips64/op_return_object.S */ 696/* File: mips64/op_return.S */ 697 /* 698 * Return a 32-bit value. 699 * 700 * for: return (sign-extend), return-object (zero-extend) 701 */ 702 /* op vAA */ 703 .extern MterpThreadFenceForConstructor 704 .extern MterpSuspendCheck 705 jal MterpThreadFenceForConstructor 706 lw ra, THREAD_FLAGS_OFFSET(rSELF) 707 move a0, rSELF 708 and ra, ra, THREAD_SUSPEND_OR_CHECKPOINT_REQUEST 709 beqzc ra, 1f 710 jal MterpSuspendCheck # (self) 7111: 712 srl a2, rINST, 8 # a2 <- AA 713 GET_VREG_U a0, a2 # a0 <- vAA 714 b MterpReturn 715 716 717/* ------------------------------ */ 718 .balign 128 719.L_op_const_4: /* 0x12 */ 720/* File: mips64/op_const_4.S */ 721 /* const/4 vA, #+B */ 722 ext a2, rINST, 8, 4 # a2 <- A 723 seh a0, rINST # sign extend B in rINST 724 FETCH_ADVANCE_INST 1 # advance rPC, load rINST 725 sra a0, a0, 12 # shift B into its final position 726 GET_INST_OPCODE v0 # extract opcode from rINST 727 SET_VREG a0, a2 # vA <- +B 728 GOTO_OPCODE v0 # jump to next instruction 729 730/* ------------------------------ */ 731 .balign 128 732.L_op_const_16: /* 0x13 */ 733/* File: mips64/op_const_16.S */ 734 /* const/16 vAA, #+BBBB */ 735 srl a2, rINST, 8 # a2 <- AA 736 lh a0, 2(rPC) # a0 <- sign-extended BBBB 737 FETCH_ADVANCE_INST 2 # advance rPC, load rINST 738 GET_INST_OPCODE v0 # extract opcode from rINST 739 SET_VREG a0, a2 # vAA <- +BBBB 740 GOTO_OPCODE v0 # jump to next instruction 741 742/* ------------------------------ */ 743 .balign 128 744.L_op_const: /* 0x14 */ 745/* File: mips64/op_const.S */ 746 /* const vAA, #+BBBBbbbb */ 747 srl a2, rINST, 8 # a2 <- AA 748 lh a0, 2(rPC) # a0 <- bbbb (low) 749 lh a1, 4(rPC) # a1 <- BBBB (high) 750 FETCH_ADVANCE_INST 3 # advance rPC, load rINST 751 ins a0, a1, 16, 16 # a0 = BBBBbbbb 752 GET_INST_OPCODE v0 # extract opcode from rINST 753 SET_VREG a0, a2 # vAA <- +BBBBbbbb 754 GOTO_OPCODE v0 # jump to next instruction 755 756/* ------------------------------ */ 757 .balign 128 758.L_op_const_high16: /* 0x15 */ 759/* File: mips64/op_const_high16.S */ 760 /* const/high16 vAA, #+BBBB0000 */ 761 srl a2, rINST, 8 # a2 <- AA 762 lh a0, 2(rPC) # a0 <- BBBB 763 FETCH_ADVANCE_INST 2 # advance rPC, load rINST 764 sll a0, a0, 16 # a0 <- BBBB0000 765 GET_INST_OPCODE v0 # extract opcode from rINST 766 SET_VREG a0, a2 # vAA <- +BBBB0000 767 GOTO_OPCODE v0 # jump to next instruction 768 769/* ------------------------------ */ 770 .balign 128 771.L_op_const_wide_16: /* 0x16 */ 772/* File: mips64/op_const_wide_16.S */ 773 /* const-wide/16 vAA, #+BBBB */ 774 srl a2, rINST, 8 # a2 <- AA 775 lh a0, 2(rPC) # a0 <- sign-extended BBBB 776 FETCH_ADVANCE_INST 2 # advance rPC, load rINST 777 GET_INST_OPCODE v0 # extract opcode from rINST 778 SET_VREG_WIDE a0, a2 # vAA <- +BBBB 779 GOTO_OPCODE v0 # jump to next instruction 780 781/* ------------------------------ */ 782 .balign 128 783.L_op_const_wide_32: /* 0x17 */ 784/* File: mips64/op_const_wide_32.S */ 785 /* const-wide/32 vAA, #+BBBBbbbb */ 786 srl a2, rINST, 8 # a2 <- AA 787 lh a0, 2(rPC) # a0 <- bbbb (low) 788 lh a1, 4(rPC) # a1 <- BBBB (high) 789 FETCH_ADVANCE_INST 3 # advance rPC, load rINST 790 ins a0, a1, 16, 16 # a0 = BBBBbbbb 791 GET_INST_OPCODE v0 # extract opcode from rINST 792 SET_VREG_WIDE a0, a2 # vAA <- +BBBBbbbb 793 GOTO_OPCODE v0 # jump to next instruction 794 795/* ------------------------------ */ 796 .balign 128 797.L_op_const_wide: /* 0x18 */ 798/* File: mips64/op_const_wide.S */ 799 /* const-wide vAA, #+HHHHhhhhBBBBbbbb */ 800 srl a4, rINST, 8 # a4 <- AA 801 lh a0, 2(rPC) # a0 <- bbbb (low) 802 lh a1, 4(rPC) # a1 <- BBBB (low middle) 803 lh a2, 6(rPC) # a2 <- hhhh (high middle) 804 lh a3, 8(rPC) # a3 <- HHHH (high) 805 FETCH_ADVANCE_INST 5 # advance rPC, load rINST 806 ins a0, a1, 16, 16 # a0 = BBBBbbbb 807 ins a2, a3, 16, 16 # a2 = HHHHhhhh 808 dinsu a0, a2, 32, 32 # a0 = HHHHhhhhBBBBbbbb 809 GET_INST_OPCODE v0 # extract opcode from rINST 810 SET_VREG_WIDE a0, a4 # vAA <- +HHHHhhhhBBBBbbbb 811 GOTO_OPCODE v0 # jump to next instruction 812 813/* ------------------------------ */ 814 .balign 128 815.L_op_const_wide_high16: /* 0x19 */ 816/* File: mips64/op_const_wide_high16.S */ 817 /* const-wide/high16 vAA, #+BBBB000000000000 */ 818 srl a2, rINST, 8 # a2 <- AA 819 lh a0, 2(rPC) # a0 <- BBBB 820 FETCH_ADVANCE_INST 2 # advance rPC, load rINST 821 dsll32 a0, a0, 16 # a0 <- BBBB000000000000 822 GET_INST_OPCODE v0 # extract opcode from rINST 823 SET_VREG_WIDE a0, a2 # vAA <- +BBBB000000000000 824 GOTO_OPCODE v0 # jump to next instruction 825 826/* ------------------------------ */ 827 .balign 128 828.L_op_const_string: /* 0x1a */ 829/* File: mips64/op_const_string.S */ 830 /* const/string vAA, String//BBBB */ 831 .extern MterpConstString 832 EXPORT_PC 833 lhu a0, 2(rPC) # a0 <- BBBB 834 srl a1, rINST, 8 # a1 <- AA 835 daddu a2, rFP, OFF_FP_SHADOWFRAME 836 move a3, rSELF 837 jal MterpConstString # (index, tgt_reg, shadow_frame, self) 838 PREFETCH_INST 2 # load rINST 839 bnez v0, MterpPossibleException # let reference interpreter deal with it. 840 ADVANCE 2 # advance rPC 841 GET_INST_OPCODE v0 # extract opcode from rINST 842 GOTO_OPCODE v0 # jump to next instruction 843 844/* ------------------------------ */ 845 .balign 128 846.L_op_const_string_jumbo: /* 0x1b */ 847/* File: mips64/op_const_string_jumbo.S */ 848 /* const/string vAA, String//BBBBBBBB */ 849 .extern MterpConstString 850 EXPORT_PC 851 lh a0, 2(rPC) # a0 <- bbbb (low) 852 lh a4, 4(rPC) # a4 <- BBBB (high) 853 srl a1, rINST, 8 # a1 <- AA 854 ins a0, a4, 16, 16 # a0 <- BBBBbbbb 855 daddu a2, rFP, OFF_FP_SHADOWFRAME 856 move a3, rSELF 857 jal MterpConstString # (index, tgt_reg, shadow_frame, self) 858 PREFETCH_INST 3 # load rINST 859 bnez v0, MterpPossibleException # let reference interpreter deal with it. 860 ADVANCE 3 # advance rPC 861 GET_INST_OPCODE v0 # extract opcode from rINST 862 GOTO_OPCODE v0 # jump to next instruction 863 864/* ------------------------------ */ 865 .balign 128 866.L_op_const_class: /* 0x1c */ 867/* File: mips64/op_const_class.S */ 868 /* const/class vAA, Class//BBBB */ 869 .extern MterpConstClass 870 EXPORT_PC 871 lhu a0, 2(rPC) # a0 <- BBBB 872 srl a1, rINST, 8 # a1 <- AA 873 daddu a2, rFP, OFF_FP_SHADOWFRAME 874 move a3, rSELF 875 jal MterpConstClass # (index, tgt_reg, shadow_frame, self) 876 PREFETCH_INST 2 # load rINST 877 bnez v0, MterpPossibleException # let reference interpreter deal with it. 878 ADVANCE 2 # advance rPC 879 GET_INST_OPCODE v0 # extract opcode from rINST 880 GOTO_OPCODE v0 # jump to next instruction 881 882/* ------------------------------ */ 883 .balign 128 884.L_op_monitor_enter: /* 0x1d */ 885/* File: mips64/op_monitor_enter.S */ 886 /* 887 * Synchronize on an object. 888 */ 889 /* monitor-enter vAA */ 890 .extern artLockObjectFromCode 891 EXPORT_PC 892 srl a2, rINST, 8 # a2 <- AA 893 GET_VREG_U a0, a2 # a0 <- vAA (object) 894 move a1, rSELF # a1 <- self 895 jal artLockObjectFromCode 896 bnezc v0, MterpException 897 FETCH_ADVANCE_INST 1 898 GET_INST_OPCODE v0 # extract opcode from rINST 899 GOTO_OPCODE v0 # jump to next instruction 900 901/* ------------------------------ */ 902 .balign 128 903.L_op_monitor_exit: /* 0x1e */ 904/* File: mips64/op_monitor_exit.S */ 905 /* 906 * Unlock an object. 907 * 908 * Exceptions that occur when unlocking a monitor need to appear as 909 * if they happened at the following instruction. See the Dalvik 910 * instruction spec. 911 */ 912 /* monitor-exit vAA */ 913 .extern artUnlockObjectFromCode 914 EXPORT_PC 915 srl a2, rINST, 8 # a2 <- AA 916 GET_VREG_U a0, a2 # a0 <- vAA (object) 917 move a1, rSELF # a1 <- self 918 jal artUnlockObjectFromCode # v0 <- success for unlock(self, obj) 919 bnezc v0, MterpException 920 FETCH_ADVANCE_INST 1 # before throw: advance rPC, load rINST 921 GET_INST_OPCODE v0 # extract opcode from rINST 922 GOTO_OPCODE v0 # jump to next instruction 923 924/* ------------------------------ */ 925 .balign 128 926.L_op_check_cast: /* 0x1f */ 927/* File: mips64/op_check_cast.S */ 928 /* 929 * Check to see if a cast from one class to another is allowed. 930 */ 931 /* check-cast vAA, class//BBBB */ 932 .extern MterpCheckCast 933 EXPORT_PC 934 lhu a0, 2(rPC) # a0 <- BBBB 935 srl a1, rINST, 8 # a1 <- AA 936 dlsa a1, a1, rFP, 2 # a1 <- &object 937 ld a2, OFF_FP_METHOD(rFP) # a2 <- method 938 move a3, rSELF # a3 <- self 939 jal MterpCheckCast # (index, &obj, method, self) 940 PREFETCH_INST 2 941 bnez v0, MterpPossibleException 942 ADVANCE 2 943 GET_INST_OPCODE v0 # extract opcode from rINST 944 GOTO_OPCODE v0 # jump to next instruction 945 946/* ------------------------------ */ 947 .balign 128 948.L_op_instance_of: /* 0x20 */ 949/* File: mips64/op_instance_of.S */ 950 /* 951 * Check to see if an object reference is an instance of a class. 952 * 953 * Most common situation is a non-null object, being compared against 954 * an already-resolved class. 955 */ 956 /* instance-of vA, vB, class//CCCC */ 957 .extern MterpInstanceOf 958 EXPORT_PC 959 lhu a0, 2(rPC) # a0 <- CCCC 960 srl a1, rINST, 12 # a1 <- B 961 dlsa a1, a1, rFP, 2 # a1 <- &object 962 ld a2, OFF_FP_METHOD(rFP) # a2 <- method 963 move a3, rSELF # a3 <- self 964 jal MterpInstanceOf # (index, &obj, method, self) 965 ld a1, THREAD_EXCEPTION_OFFSET(rSELF) 966 ext a2, rINST, 8, 4 # a2 <- A 967 PREFETCH_INST 2 968 bnez a1, MterpException 969 ADVANCE 2 # advance rPC 970 SET_VREG v0, a2 # vA <- v0 971 GET_INST_OPCODE v0 # extract opcode from rINST 972 GOTO_OPCODE v0 # jump to next instruction 973 974/* ------------------------------ */ 975 .balign 128 976.L_op_array_length: /* 0x21 */ 977/* File: mips64/op_array_length.S */ 978 /* 979 * Return the length of an array. 980 */ 981 srl a1, rINST, 12 # a1 <- B 982 GET_VREG_U a0, a1 # a0 <- vB (object ref) 983 ext a2, rINST, 8, 4 # a2 <- A 984 beqz a0, common_errNullObject # yup, fail 985 FETCH_ADVANCE_INST 1 # advance rPC, load rINST 986 lw a3, MIRROR_ARRAY_LENGTH_OFFSET(a0) # a3 <- array length 987 GET_INST_OPCODE v0 # extract opcode from rINST 988 SET_VREG a3, a2 # vB <- length 989 GOTO_OPCODE v0 # jump to next instruction 990 991/* ------------------------------ */ 992 .balign 128 993.L_op_new_instance: /* 0x22 */ 994/* File: mips64/op_new_instance.S */ 995 /* 996 * Create a new instance of a class. 997 */ 998 /* new-instance vAA, class//BBBB */ 999 .extern MterpNewInstance 1000 EXPORT_PC 1001 daddu a0, rFP, OFF_FP_SHADOWFRAME 1002 move a1, rSELF 1003 move a2, rINST 1004 jal MterpNewInstance # (shadow_frame, self, inst_data) 1005 beqzc v0, MterpPossibleException 1006 FETCH_ADVANCE_INST 2 # advance rPC, load rINST 1007 GET_INST_OPCODE v0 # extract opcode from rINST 1008 GOTO_OPCODE v0 # jump to next instruction 1009 1010/* ------------------------------ */ 1011 .balign 128 1012.L_op_new_array: /* 0x23 */ 1013/* File: mips64/op_new_array.S */ 1014 /* 1015 * Allocate an array of objects, specified with the array class 1016 * and a count. 1017 * 1018 * The verifier guarantees that this is an array class, so we don't 1019 * check for it here. 1020 */ 1021 /* new-array vA, vB, class//CCCC */ 1022 .extern MterpNewArray 1023 EXPORT_PC 1024 daddu a0, rFP, OFF_FP_SHADOWFRAME 1025 move a1, rPC 1026 move a2, rINST 1027 move a3, rSELF 1028 jal MterpNewArray 1029 beqzc v0, MterpPossibleException 1030 FETCH_ADVANCE_INST 2 # advance rPC, load rINST 1031 GET_INST_OPCODE v0 # extract opcode from rINST 1032 GOTO_OPCODE v0 # jump to next instruction 1033 1034/* ------------------------------ */ 1035 .balign 128 1036.L_op_filled_new_array: /* 0x24 */ 1037/* File: mips64/op_filled_new_array.S */ 1038 /* 1039 * Create a new array with elements filled from registers. 1040 * 1041 * for: filled-new-array, filled-new-array/range 1042 */ 1043 /* op vB, {vD, vE, vF, vG, vA}, class//CCCC */ 1044 /* op {vCCCC..v(CCCC+AA-1)}, type//BBBB */ 1045 .extern MterpFilledNewArray 1046 EXPORT_PC 1047 daddu a0, rFP, OFF_FP_SHADOWFRAME 1048 move a1, rPC 1049 move a2, rSELF 1050 jal MterpFilledNewArray 1051 beqzc v0, MterpPossibleException 1052 FETCH_ADVANCE_INST 3 # advance rPC, load rINST 1053 GET_INST_OPCODE v0 # extract opcode from rINST 1054 GOTO_OPCODE v0 # jump to next instruction 1055 1056/* ------------------------------ */ 1057 .balign 128 1058.L_op_filled_new_array_range: /* 0x25 */ 1059/* File: mips64/op_filled_new_array_range.S */ 1060/* File: mips64/op_filled_new_array.S */ 1061 /* 1062 * Create a new array with elements filled from registers. 1063 * 1064 * for: filled-new-array, filled-new-array/range 1065 */ 1066 /* op vB, {vD, vE, vF, vG, vA}, class//CCCC */ 1067 /* op {vCCCC..v(CCCC+AA-1)}, type//BBBB */ 1068 .extern MterpFilledNewArrayRange 1069 EXPORT_PC 1070 daddu a0, rFP, OFF_FP_SHADOWFRAME 1071 move a1, rPC 1072 move a2, rSELF 1073 jal MterpFilledNewArrayRange 1074 beqzc v0, MterpPossibleException 1075 FETCH_ADVANCE_INST 3 # advance rPC, load rINST 1076 GET_INST_OPCODE v0 # extract opcode from rINST 1077 GOTO_OPCODE v0 # jump to next instruction 1078 1079 1080/* ------------------------------ */ 1081 .balign 128 1082.L_op_fill_array_data: /* 0x26 */ 1083/* File: mips64/op_fill_array_data.S */ 1084 /* fill-array-data vAA, +BBBBBBBB */ 1085 .extern MterpFillArrayData 1086 EXPORT_PC 1087 lh a1, 2(rPC) # a1 <- bbbb (lo) 1088 lh a0, 4(rPC) # a0 <- BBBB (hi) 1089 srl a3, rINST, 8 # a3 <- AA 1090 ins a1, a0, 16, 16 # a1 <- BBBBbbbb 1091 GET_VREG_U a0, a3 # a0 <- vAA (array object) 1092 dlsa a1, a1, rPC, 1 # a1 <- PC + BBBBbbbb*2 (array data off.) 1093 jal MterpFillArrayData # (obj, payload) 1094 beqzc v0, MterpPossibleException # exception? 1095 FETCH_ADVANCE_INST 3 # advance rPC, load rINST 1096 GET_INST_OPCODE v0 # extract opcode from rINST 1097 GOTO_OPCODE v0 # jump to next instruction 1098 1099/* ------------------------------ */ 1100 .balign 128 1101.L_op_throw: /* 0x27 */ 1102/* File: mips64/op_throw.S */ 1103 /* 1104 * Throw an exception object in the current thread. 1105 */ 1106 /* throw vAA */ 1107 EXPORT_PC 1108 srl a2, rINST, 8 # a2 <- AA 1109 GET_VREG_U a0, a2 # a0 <- vAA (exception object) 1110 beqzc a0, common_errNullObject 1111 sd a0, THREAD_EXCEPTION_OFFSET(rSELF) # thread->exception <- obj 1112 b MterpException 1113 1114/* ------------------------------ */ 1115 .balign 128 1116.L_op_goto: /* 0x28 */ 1117/* File: mips64/op_goto.S */ 1118 /* 1119 * Unconditional branch, 8-bit offset. 1120 * 1121 * The branch distance is a signed code-unit offset, which we need to 1122 * double to get a byte offset. 1123 */ 1124 /* goto +AA */ 1125 srl rINST, rINST, 8 1126 seb rINST, rINST # rINST <- offset (sign-extended AA) 1127 b MterpCommonTakenBranchNoFlags 1128 1129/* ------------------------------ */ 1130 .balign 128 1131.L_op_goto_16: /* 0x29 */ 1132/* File: mips64/op_goto_16.S */ 1133 /* 1134 * Unconditional branch, 16-bit offset. 1135 * 1136 * The branch distance is a signed code-unit offset, which we need to 1137 * double to get a byte offset. 1138 */ 1139 /* goto/16 +AAAA */ 1140 lh rINST, 2(rPC) # rINST <- offset (sign-extended AAAA) 1141 b MterpCommonTakenBranchNoFlags 1142 1143/* ------------------------------ */ 1144 .balign 128 1145.L_op_goto_32: /* 0x2a */ 1146/* File: mips64/op_goto_32.S */ 1147 /* 1148 * Unconditional branch, 32-bit offset. 1149 * 1150 * The branch distance is a signed code-unit offset, which we need to 1151 * double to get a byte offset. 1152 * 1153 * Unlike most opcodes, this one is allowed to branch to itself, so 1154 * our "backward branch" test must be "<=0" instead of "<0". 1155 */ 1156 /* goto/32 +AAAAAAAA */ 1157 lh rINST, 2(rPC) # rINST <- aaaa (low) 1158 lh a1, 4(rPC) # a1 <- AAAA (high) 1159 ins rINST, a1, 16, 16 # rINST <- offset (sign-extended AAAAaaaa) 1160 b MterpCommonTakenBranchNoFlags 1161 1162/* ------------------------------ */ 1163 .balign 128 1164.L_op_packed_switch: /* 0x2b */ 1165/* File: mips64/op_packed_switch.S */ 1166 /* 1167 * Handle a packed-switch or sparse-switch instruction. In both cases 1168 * we decode it and hand it off to a helper function. 1169 * 1170 * We don't really expect backward branches in a switch statement, but 1171 * they're perfectly legal, so we check for them here. 1172 * 1173 * for: packed-switch, sparse-switch 1174 */ 1175 /* op vAA, +BBBBBBBB */ 1176 .extern MterpDoPackedSwitch 1177 lh a0, 2(rPC) # a0 <- bbbb (lo) 1178 lh a1, 4(rPC) # a1 <- BBBB (hi) 1179 srl a3, rINST, 8 # a3 <- AA 1180 ins a0, a1, 16, 16 # a0 <- BBBBbbbb 1181 GET_VREG a1, a3 # a1 <- vAA 1182 dlsa a0, a0, rPC, 1 # a0 <- PC + BBBBbbbb*2 1183 jal MterpDoPackedSwitch # v0 <- code-unit branch offset 1184 move rINST, v0 1185 b MterpCommonTakenBranchNoFlags 1186 1187/* ------------------------------ */ 1188 .balign 128 1189.L_op_sparse_switch: /* 0x2c */ 1190/* File: mips64/op_sparse_switch.S */ 1191/* File: mips64/op_packed_switch.S */ 1192 /* 1193 * Handle a packed-switch or sparse-switch instruction. In both cases 1194 * we decode it and hand it off to a helper function. 1195 * 1196 * We don't really expect backward branches in a switch statement, but 1197 * they're perfectly legal, so we check for them here. 1198 * 1199 * for: packed-switch, sparse-switch 1200 */ 1201 /* op vAA, +BBBBBBBB */ 1202 .extern MterpDoSparseSwitch 1203 lh a0, 2(rPC) # a0 <- bbbb (lo) 1204 lh a1, 4(rPC) # a1 <- BBBB (hi) 1205 srl a3, rINST, 8 # a3 <- AA 1206 ins a0, a1, 16, 16 # a0 <- BBBBbbbb 1207 GET_VREG a1, a3 # a1 <- vAA 1208 dlsa a0, a0, rPC, 1 # a0 <- PC + BBBBbbbb*2 1209 jal MterpDoSparseSwitch # v0 <- code-unit branch offset 1210 move rINST, v0 1211 b MterpCommonTakenBranchNoFlags 1212 1213 1214/* ------------------------------ */ 1215 .balign 128 1216.L_op_cmpl_float: /* 0x2d */ 1217/* File: mips64/op_cmpl_float.S */ 1218/* File: mips64/fcmp.S */ 1219 /* 1220 * Compare two floating-point values. Puts 0, 1, or -1 into the 1221 * destination register based on the results of the comparison. 1222 * 1223 * For: cmpl-float, cmpg-float 1224 */ 1225 /* op vAA, vBB, vCC */ 1226 srl a4, rINST, 8 # a4 <- AA 1227 lbu a2, 2(rPC) # a2 <- BB 1228 lbu a3, 3(rPC) # a3 <- CC 1229 GET_VREG_FLOAT f0, a2 # f0 <- vBB 1230 GET_VREG_FLOAT f1, a3 # f1 <- vCC 1231 cmp.eq.s f2, f0, f1 1232 li a0, 0 1233 bc1nez f2, 1f # done if vBB == vCC (ordered) 1234 .if 0 1235 cmp.lt.s f2, f0, f1 1236 li a0, -1 1237 bc1nez f2, 1f # done if vBB < vCC (ordered) 1238 li a0, 1 # vBB > vCC or unordered 1239 .else 1240 cmp.lt.s f2, f1, f0 1241 li a0, 1 1242 bc1nez f2, 1f # done if vBB > vCC (ordered) 1243 li a0, -1 # vBB < vCC or unordered 1244 .endif 12451: 1246 FETCH_ADVANCE_INST 2 # advance rPC, load rINST 1247 GET_INST_OPCODE v0 # extract opcode from rINST 1248 SET_VREG a0, a4 # vAA <- a0 1249 GOTO_OPCODE v0 # jump to next instruction 1250 1251 1252/* ------------------------------ */ 1253 .balign 128 1254.L_op_cmpg_float: /* 0x2e */ 1255/* File: mips64/op_cmpg_float.S */ 1256/* File: mips64/fcmp.S */ 1257 /* 1258 * Compare two floating-point values. Puts 0, 1, or -1 into the 1259 * destination register based on the results of the comparison. 1260 * 1261 * For: cmpl-float, cmpg-float 1262 */ 1263 /* op vAA, vBB, vCC */ 1264 srl a4, rINST, 8 # a4 <- AA 1265 lbu a2, 2(rPC) # a2 <- BB 1266 lbu a3, 3(rPC) # a3 <- CC 1267 GET_VREG_FLOAT f0, a2 # f0 <- vBB 1268 GET_VREG_FLOAT f1, a3 # f1 <- vCC 1269 cmp.eq.s f2, f0, f1 1270 li a0, 0 1271 bc1nez f2, 1f # done if vBB == vCC (ordered) 1272 .if 1 1273 cmp.lt.s f2, f0, f1 1274 li a0, -1 1275 bc1nez f2, 1f # done if vBB < vCC (ordered) 1276 li a0, 1 # vBB > vCC or unordered 1277 .else 1278 cmp.lt.s f2, f1, f0 1279 li a0, 1 1280 bc1nez f2, 1f # done if vBB > vCC (ordered) 1281 li a0, -1 # vBB < vCC or unordered 1282 .endif 12831: 1284 FETCH_ADVANCE_INST 2 # advance rPC, load rINST 1285 GET_INST_OPCODE v0 # extract opcode from rINST 1286 SET_VREG a0, a4 # vAA <- a0 1287 GOTO_OPCODE v0 # jump to next instruction 1288 1289 1290/* ------------------------------ */ 1291 .balign 128 1292.L_op_cmpl_double: /* 0x2f */ 1293/* File: mips64/op_cmpl_double.S */ 1294/* File: mips64/fcmpWide.S */ 1295 /* 1296 * Compare two floating-point values. Puts 0, 1, or -1 into the 1297 * destination register based on the results of the comparison. 1298 * 1299 * For: cmpl-double, cmpg-double 1300 */ 1301 /* op vAA, vBB, vCC */ 1302 srl a4, rINST, 8 # a4 <- AA 1303 lbu a2, 2(rPC) # a2 <- BB 1304 lbu a3, 3(rPC) # a3 <- CC 1305 GET_VREG_DOUBLE f0, a2 # f0 <- vBB 1306 GET_VREG_DOUBLE f1, a3 # f1 <- vCC 1307 cmp.eq.d f2, f0, f1 1308 li a0, 0 1309 bc1nez f2, 1f # done if vBB == vCC (ordered) 1310 .if 0 1311 cmp.lt.d f2, f0, f1 1312 li a0, -1 1313 bc1nez f2, 1f # done if vBB < vCC (ordered) 1314 li a0, 1 # vBB > vCC or unordered 1315 .else 1316 cmp.lt.d f2, f1, f0 1317 li a0, 1 1318 bc1nez f2, 1f # done if vBB > vCC (ordered) 1319 li a0, -1 # vBB < vCC or unordered 1320 .endif 13211: 1322 FETCH_ADVANCE_INST 2 # advance rPC, load rINST 1323 GET_INST_OPCODE v0 # extract opcode from rINST 1324 SET_VREG a0, a4 # vAA <- a0 1325 GOTO_OPCODE v0 # jump to next instruction 1326 1327 1328/* ------------------------------ */ 1329 .balign 128 1330.L_op_cmpg_double: /* 0x30 */ 1331/* File: mips64/op_cmpg_double.S */ 1332/* File: mips64/fcmpWide.S */ 1333 /* 1334 * Compare two floating-point values. Puts 0, 1, or -1 into the 1335 * destination register based on the results of the comparison. 1336 * 1337 * For: cmpl-double, cmpg-double 1338 */ 1339 /* op vAA, vBB, vCC */ 1340 srl a4, rINST, 8 # a4 <- AA 1341 lbu a2, 2(rPC) # a2 <- BB 1342 lbu a3, 3(rPC) # a3 <- CC 1343 GET_VREG_DOUBLE f0, a2 # f0 <- vBB 1344 GET_VREG_DOUBLE f1, a3 # f1 <- vCC 1345 cmp.eq.d f2, f0, f1 1346 li a0, 0 1347 bc1nez f2, 1f # done if vBB == vCC (ordered) 1348 .if 1 1349 cmp.lt.d f2, f0, f1 1350 li a0, -1 1351 bc1nez f2, 1f # done if vBB < vCC (ordered) 1352 li a0, 1 # vBB > vCC or unordered 1353 .else 1354 cmp.lt.d f2, f1, f0 1355 li a0, 1 1356 bc1nez f2, 1f # done if vBB > vCC (ordered) 1357 li a0, -1 # vBB < vCC or unordered 1358 .endif 13591: 1360 FETCH_ADVANCE_INST 2 # advance rPC, load rINST 1361 GET_INST_OPCODE v0 # extract opcode from rINST 1362 SET_VREG a0, a4 # vAA <- a0 1363 GOTO_OPCODE v0 # jump to next instruction 1364 1365 1366/* ------------------------------ */ 1367 .balign 128 1368.L_op_cmp_long: /* 0x31 */ 1369/* File: mips64/op_cmp_long.S */ 1370 /* cmp-long vAA, vBB, vCC */ 1371 lbu a2, 2(rPC) # a2 <- BB 1372 lbu a3, 3(rPC) # a3 <- CC 1373 srl a4, rINST, 8 # a4 <- AA 1374 GET_VREG_WIDE a0, a2 # a0 <- vBB 1375 GET_VREG_WIDE a1, a3 # a1 <- vCC 1376 FETCH_ADVANCE_INST 2 # advance rPC, load rINST 1377 slt a2, a0, a1 1378 slt a0, a1, a0 1379 subu a0, a0, a2 1380 GET_INST_OPCODE v0 # extract opcode from rINST 1381 SET_VREG a0, a4 # vAA <- result 1382 GOTO_OPCODE v0 # jump to next instruction 1383 1384/* ------------------------------ */ 1385 .balign 128 1386.L_op_if_eq: /* 0x32 */ 1387/* File: mips64/op_if_eq.S */ 1388/* File: mips64/bincmp.S */ 1389 /* 1390 * Generic two-operand compare-and-branch operation. Provide a "condition" 1391 * fragment that specifies the comparison to perform, e.g. for 1392 * "if-le" you would use "le". 1393 * 1394 * For: if-eq, if-ne, if-lt, if-ge, if-gt, if-le 1395 */ 1396 /* if-cmp vA, vB, +CCCC */ 1397 ext a2, rINST, 8, 4 # a2 <- A 1398 ext a3, rINST, 12, 4 # a3 <- B 1399 lh rINST, 2(rPC) # rINST <- offset (sign-extended CCCC) 1400 GET_VREG a0, a2 # a0 <- vA 1401 GET_VREG a1, a3 # a1 <- vB 1402 beqc a0, a1, MterpCommonTakenBranchNoFlags 1403 li v0, JIT_CHECK_OSR # possible OSR re-entry? 1404 beqc rPROFILE, v0, .L_check_not_taken_osr 1405 FETCH_ADVANCE_INST 2 # advance rPC, load rINST 1406 GET_INST_OPCODE v0 # extract opcode from rINST 1407 GOTO_OPCODE v0 # jump to next instruction 1408 1409 1410/* ------------------------------ */ 1411 .balign 128 1412.L_op_if_ne: /* 0x33 */ 1413/* File: mips64/op_if_ne.S */ 1414/* File: mips64/bincmp.S */ 1415 /* 1416 * Generic two-operand compare-and-branch operation. Provide a "condition" 1417 * fragment that specifies the comparison to perform, e.g. for 1418 * "if-le" you would use "le". 1419 * 1420 * For: if-eq, if-ne, if-lt, if-ge, if-gt, if-le 1421 */ 1422 /* if-cmp vA, vB, +CCCC */ 1423 ext a2, rINST, 8, 4 # a2 <- A 1424 ext a3, rINST, 12, 4 # a3 <- B 1425 lh rINST, 2(rPC) # rINST <- offset (sign-extended CCCC) 1426 GET_VREG a0, a2 # a0 <- vA 1427 GET_VREG a1, a3 # a1 <- vB 1428 bnec a0, a1, MterpCommonTakenBranchNoFlags 1429 li v0, JIT_CHECK_OSR # possible OSR re-entry? 1430 beqc rPROFILE, v0, .L_check_not_taken_osr 1431 FETCH_ADVANCE_INST 2 # advance rPC, load rINST 1432 GET_INST_OPCODE v0 # extract opcode from rINST 1433 GOTO_OPCODE v0 # jump to next instruction 1434 1435 1436/* ------------------------------ */ 1437 .balign 128 1438.L_op_if_lt: /* 0x34 */ 1439/* File: mips64/op_if_lt.S */ 1440/* File: mips64/bincmp.S */ 1441 /* 1442 * Generic two-operand compare-and-branch operation. Provide a "condition" 1443 * fragment that specifies the comparison to perform, e.g. for 1444 * "if-le" you would use "le". 1445 * 1446 * For: if-eq, if-ne, if-lt, if-ge, if-gt, if-le 1447 */ 1448 /* if-cmp vA, vB, +CCCC */ 1449 ext a2, rINST, 8, 4 # a2 <- A 1450 ext a3, rINST, 12, 4 # a3 <- B 1451 lh rINST, 2(rPC) # rINST <- offset (sign-extended CCCC) 1452 GET_VREG a0, a2 # a0 <- vA 1453 GET_VREG a1, a3 # a1 <- vB 1454 bltc a0, a1, MterpCommonTakenBranchNoFlags 1455 li v0, JIT_CHECK_OSR # possible OSR re-entry? 1456 beqc rPROFILE, v0, .L_check_not_taken_osr 1457 FETCH_ADVANCE_INST 2 # advance rPC, load rINST 1458 GET_INST_OPCODE v0 # extract opcode from rINST 1459 GOTO_OPCODE v0 # jump to next instruction 1460 1461 1462/* ------------------------------ */ 1463 .balign 128 1464.L_op_if_ge: /* 0x35 */ 1465/* File: mips64/op_if_ge.S */ 1466/* File: mips64/bincmp.S */ 1467 /* 1468 * Generic two-operand compare-and-branch operation. Provide a "condition" 1469 * fragment that specifies the comparison to perform, e.g. for 1470 * "if-le" you would use "le". 1471 * 1472 * For: if-eq, if-ne, if-lt, if-ge, if-gt, if-le 1473 */ 1474 /* if-cmp vA, vB, +CCCC */ 1475 ext a2, rINST, 8, 4 # a2 <- A 1476 ext a3, rINST, 12, 4 # a3 <- B 1477 lh rINST, 2(rPC) # rINST <- offset (sign-extended CCCC) 1478 GET_VREG a0, a2 # a0 <- vA 1479 GET_VREG a1, a3 # a1 <- vB 1480 bgec a0, a1, MterpCommonTakenBranchNoFlags 1481 li v0, JIT_CHECK_OSR # possible OSR re-entry? 1482 beqc rPROFILE, v0, .L_check_not_taken_osr 1483 FETCH_ADVANCE_INST 2 # advance rPC, load rINST 1484 GET_INST_OPCODE v0 # extract opcode from rINST 1485 GOTO_OPCODE v0 # jump to next instruction 1486 1487 1488/* ------------------------------ */ 1489 .balign 128 1490.L_op_if_gt: /* 0x36 */ 1491/* File: mips64/op_if_gt.S */ 1492/* File: mips64/bincmp.S */ 1493 /* 1494 * Generic two-operand compare-and-branch operation. Provide a "condition" 1495 * fragment that specifies the comparison to perform, e.g. for 1496 * "if-le" you would use "le". 1497 * 1498 * For: if-eq, if-ne, if-lt, if-ge, if-gt, if-le 1499 */ 1500 /* if-cmp vA, vB, +CCCC */ 1501 ext a2, rINST, 8, 4 # a2 <- A 1502 ext a3, rINST, 12, 4 # a3 <- B 1503 lh rINST, 2(rPC) # rINST <- offset (sign-extended CCCC) 1504 GET_VREG a0, a2 # a0 <- vA 1505 GET_VREG a1, a3 # a1 <- vB 1506 bgtc a0, a1, MterpCommonTakenBranchNoFlags 1507 li v0, JIT_CHECK_OSR # possible OSR re-entry? 1508 beqc rPROFILE, v0, .L_check_not_taken_osr 1509 FETCH_ADVANCE_INST 2 # advance rPC, load rINST 1510 GET_INST_OPCODE v0 # extract opcode from rINST 1511 GOTO_OPCODE v0 # jump to next instruction 1512 1513 1514/* ------------------------------ */ 1515 .balign 128 1516.L_op_if_le: /* 0x37 */ 1517/* File: mips64/op_if_le.S */ 1518/* File: mips64/bincmp.S */ 1519 /* 1520 * Generic two-operand compare-and-branch operation. Provide a "condition" 1521 * fragment that specifies the comparison to perform, e.g. for 1522 * "if-le" you would use "le". 1523 * 1524 * For: if-eq, if-ne, if-lt, if-ge, if-gt, if-le 1525 */ 1526 /* if-cmp vA, vB, +CCCC */ 1527 ext a2, rINST, 8, 4 # a2 <- A 1528 ext a3, rINST, 12, 4 # a3 <- B 1529 lh rINST, 2(rPC) # rINST <- offset (sign-extended CCCC) 1530 GET_VREG a0, a2 # a0 <- vA 1531 GET_VREG a1, a3 # a1 <- vB 1532 blec a0, a1, MterpCommonTakenBranchNoFlags 1533 li v0, JIT_CHECK_OSR # possible OSR re-entry? 1534 beqc rPROFILE, v0, .L_check_not_taken_osr 1535 FETCH_ADVANCE_INST 2 # advance rPC, load rINST 1536 GET_INST_OPCODE v0 # extract opcode from rINST 1537 GOTO_OPCODE v0 # jump to next instruction 1538 1539 1540/* ------------------------------ */ 1541 .balign 128 1542.L_op_if_eqz: /* 0x38 */ 1543/* File: mips64/op_if_eqz.S */ 1544/* File: mips64/zcmp.S */ 1545 /* 1546 * Generic one-operand compare-and-branch operation. Provide a "condition" 1547 * fragment that specifies the comparison to perform, e.g. for 1548 * "if-lez" you would use "le". 1549 * 1550 * For: if-eqz, if-nez, if-ltz, if-gez, if-gtz, if-lez 1551 */ 1552 /* if-cmp vAA, +BBBB */ 1553 srl a2, rINST, 8 # a2 <- AA 1554 lh rINST, 2(rPC) # rINST <- offset (sign-extended BBBB) 1555 GET_VREG a0, a2 # a0 <- vAA 1556 beqzc a0, MterpCommonTakenBranchNoFlags 1557 li v0, JIT_CHECK_OSR # possible OSR re-entry? 1558 beqc rPROFILE, v0, .L_check_not_taken_osr 1559 FETCH_ADVANCE_INST 2 # advance rPC, load rINST 1560 GET_INST_OPCODE v0 # extract opcode from rINST 1561 GOTO_OPCODE v0 # jump to next instruction 1562 1563 1564/* ------------------------------ */ 1565 .balign 128 1566.L_op_if_nez: /* 0x39 */ 1567/* File: mips64/op_if_nez.S */ 1568/* File: mips64/zcmp.S */ 1569 /* 1570 * Generic one-operand compare-and-branch operation. Provide a "condition" 1571 * fragment that specifies the comparison to perform, e.g. for 1572 * "if-lez" you would use "le". 1573 * 1574 * For: if-eqz, if-nez, if-ltz, if-gez, if-gtz, if-lez 1575 */ 1576 /* if-cmp vAA, +BBBB */ 1577 srl a2, rINST, 8 # a2 <- AA 1578 lh rINST, 2(rPC) # rINST <- offset (sign-extended BBBB) 1579 GET_VREG a0, a2 # a0 <- vAA 1580 bnezc a0, MterpCommonTakenBranchNoFlags 1581 li v0, JIT_CHECK_OSR # possible OSR re-entry? 1582 beqc rPROFILE, v0, .L_check_not_taken_osr 1583 FETCH_ADVANCE_INST 2 # advance rPC, load rINST 1584 GET_INST_OPCODE v0 # extract opcode from rINST 1585 GOTO_OPCODE v0 # jump to next instruction 1586 1587 1588/* ------------------------------ */ 1589 .balign 128 1590.L_op_if_ltz: /* 0x3a */ 1591/* File: mips64/op_if_ltz.S */ 1592/* File: mips64/zcmp.S */ 1593 /* 1594 * Generic one-operand compare-and-branch operation. Provide a "condition" 1595 * fragment that specifies the comparison to perform, e.g. for 1596 * "if-lez" you would use "le". 1597 * 1598 * For: if-eqz, if-nez, if-ltz, if-gez, if-gtz, if-lez 1599 */ 1600 /* if-cmp vAA, +BBBB */ 1601 srl a2, rINST, 8 # a2 <- AA 1602 lh rINST, 2(rPC) # rINST <- offset (sign-extended BBBB) 1603 GET_VREG a0, a2 # a0 <- vAA 1604 bltzc a0, MterpCommonTakenBranchNoFlags 1605 li v0, JIT_CHECK_OSR # possible OSR re-entry? 1606 beqc rPROFILE, v0, .L_check_not_taken_osr 1607 FETCH_ADVANCE_INST 2 # advance rPC, load rINST 1608 GET_INST_OPCODE v0 # extract opcode from rINST 1609 GOTO_OPCODE v0 # jump to next instruction 1610 1611 1612/* ------------------------------ */ 1613 .balign 128 1614.L_op_if_gez: /* 0x3b */ 1615/* File: mips64/op_if_gez.S */ 1616/* File: mips64/zcmp.S */ 1617 /* 1618 * Generic one-operand compare-and-branch operation. Provide a "condition" 1619 * fragment that specifies the comparison to perform, e.g. for 1620 * "if-lez" you would use "le". 1621 * 1622 * For: if-eqz, if-nez, if-ltz, if-gez, if-gtz, if-lez 1623 */ 1624 /* if-cmp vAA, +BBBB */ 1625 srl a2, rINST, 8 # a2 <- AA 1626 lh rINST, 2(rPC) # rINST <- offset (sign-extended BBBB) 1627 GET_VREG a0, a2 # a0 <- vAA 1628 bgezc a0, MterpCommonTakenBranchNoFlags 1629 li v0, JIT_CHECK_OSR # possible OSR re-entry? 1630 beqc rPROFILE, v0, .L_check_not_taken_osr 1631 FETCH_ADVANCE_INST 2 # advance rPC, load rINST 1632 GET_INST_OPCODE v0 # extract opcode from rINST 1633 GOTO_OPCODE v0 # jump to next instruction 1634 1635 1636/* ------------------------------ */ 1637 .balign 128 1638.L_op_if_gtz: /* 0x3c */ 1639/* File: mips64/op_if_gtz.S */ 1640/* File: mips64/zcmp.S */ 1641 /* 1642 * Generic one-operand compare-and-branch operation. Provide a "condition" 1643 * fragment that specifies the comparison to perform, e.g. for 1644 * "if-lez" you would use "le". 1645 * 1646 * For: if-eqz, if-nez, if-ltz, if-gez, if-gtz, if-lez 1647 */ 1648 /* if-cmp vAA, +BBBB */ 1649 srl a2, rINST, 8 # a2 <- AA 1650 lh rINST, 2(rPC) # rINST <- offset (sign-extended BBBB) 1651 GET_VREG a0, a2 # a0 <- vAA 1652 bgtzc a0, MterpCommonTakenBranchNoFlags 1653 li v0, JIT_CHECK_OSR # possible OSR re-entry? 1654 beqc rPROFILE, v0, .L_check_not_taken_osr 1655 FETCH_ADVANCE_INST 2 # advance rPC, load rINST 1656 GET_INST_OPCODE v0 # extract opcode from rINST 1657 GOTO_OPCODE v0 # jump to next instruction 1658 1659 1660/* ------------------------------ */ 1661 .balign 128 1662.L_op_if_lez: /* 0x3d */ 1663/* File: mips64/op_if_lez.S */ 1664/* File: mips64/zcmp.S */ 1665 /* 1666 * Generic one-operand compare-and-branch operation. Provide a "condition" 1667 * fragment that specifies the comparison to perform, e.g. for 1668 * "if-lez" you would use "le". 1669 * 1670 * For: if-eqz, if-nez, if-ltz, if-gez, if-gtz, if-lez 1671 */ 1672 /* if-cmp vAA, +BBBB */ 1673 srl a2, rINST, 8 # a2 <- AA 1674 lh rINST, 2(rPC) # rINST <- offset (sign-extended BBBB) 1675 GET_VREG a0, a2 # a0 <- vAA 1676 blezc a0, MterpCommonTakenBranchNoFlags 1677 li v0, JIT_CHECK_OSR # possible OSR re-entry? 1678 beqc rPROFILE, v0, .L_check_not_taken_osr 1679 FETCH_ADVANCE_INST 2 # advance rPC, load rINST 1680 GET_INST_OPCODE v0 # extract opcode from rINST 1681 GOTO_OPCODE v0 # jump to next instruction 1682 1683 1684/* ------------------------------ */ 1685 .balign 128 1686.L_op_unused_3e: /* 0x3e */ 1687/* File: mips64/op_unused_3e.S */ 1688/* File: mips64/unused.S */ 1689/* 1690 * Bail to reference interpreter to throw. 1691 */ 1692 b MterpFallback 1693 1694 1695/* ------------------------------ */ 1696 .balign 128 1697.L_op_unused_3f: /* 0x3f */ 1698/* File: mips64/op_unused_3f.S */ 1699/* File: mips64/unused.S */ 1700/* 1701 * Bail to reference interpreter to throw. 1702 */ 1703 b MterpFallback 1704 1705 1706/* ------------------------------ */ 1707 .balign 128 1708.L_op_unused_40: /* 0x40 */ 1709/* File: mips64/op_unused_40.S */ 1710/* File: mips64/unused.S */ 1711/* 1712 * Bail to reference interpreter to throw. 1713 */ 1714 b MterpFallback 1715 1716 1717/* ------------------------------ */ 1718 .balign 128 1719.L_op_unused_41: /* 0x41 */ 1720/* File: mips64/op_unused_41.S */ 1721/* File: mips64/unused.S */ 1722/* 1723 * Bail to reference interpreter to throw. 1724 */ 1725 b MterpFallback 1726 1727 1728/* ------------------------------ */ 1729 .balign 128 1730.L_op_unused_42: /* 0x42 */ 1731/* File: mips64/op_unused_42.S */ 1732/* File: mips64/unused.S */ 1733/* 1734 * Bail to reference interpreter to throw. 1735 */ 1736 b MterpFallback 1737 1738 1739/* ------------------------------ */ 1740 .balign 128 1741.L_op_unused_43: /* 0x43 */ 1742/* File: mips64/op_unused_43.S */ 1743/* File: mips64/unused.S */ 1744/* 1745 * Bail to reference interpreter to throw. 1746 */ 1747 b MterpFallback 1748 1749 1750/* ------------------------------ */ 1751 .balign 128 1752.L_op_aget: /* 0x44 */ 1753/* File: mips64/op_aget.S */ 1754 /* 1755 * Array get, 32 bits or less. vAA <- vBB[vCC]. 1756 * 1757 * for: aget, aget-boolean, aget-byte, aget-char, aget-short 1758 * 1759 * NOTE: assumes data offset for arrays is the same for all non-wide types. 1760 * If this changes, specialize. 1761 */ 1762 /* op vAA, vBB, vCC */ 1763 lbu a2, 2(rPC) # a2 <- BB 1764 lbu a3, 3(rPC) # a3 <- CC 1765 srl a4, rINST, 8 # a4 <- AA 1766 GET_VREG_U a0, a2 # a0 <- vBB (array object) 1767 GET_VREG a1, a3 # a1 <- vCC (requested index) 1768 beqz a0, common_errNullObject # bail if null array object 1769 lw a3, MIRROR_ARRAY_LENGTH_OFFSET(a0) # a3 <- arrayObj->length 1770 .if 2 1771 # [d]lsa does not support shift count of 0. 1772 dlsa a0, a1, a0, 2 # a0 <- arrayObj + index*width 1773 .else 1774 daddu a0, a1, a0 # a0 <- arrayObj + index*width 1775 .endif 1776 bgeu a1, a3, common_errArrayIndex # unsigned compare: index >= length, bail 1777 FETCH_ADVANCE_INST 2 # advance rPC, load rINST 1778 lw a2, MIRROR_INT_ARRAY_DATA_OFFSET(a0) # a2 <- vBB[vCC] 1779 GET_INST_OPCODE v0 # extract opcode from rINST 1780 SET_VREG a2, a4 # vAA <- a2 1781 GOTO_OPCODE v0 # jump to next instruction 1782 1783/* ------------------------------ */ 1784 .balign 128 1785.L_op_aget_wide: /* 0x45 */ 1786/* File: mips64/op_aget_wide.S */ 1787 /* 1788 * Array get, 64 bits. vAA <- vBB[vCC]. 1789 * 1790 */ 1791 /* aget-wide vAA, vBB, vCC */ 1792 lbu a2, 2(rPC) # a2 <- BB 1793 lbu a3, 3(rPC) # a3 <- CC 1794 srl a4, rINST, 8 # a4 <- AA 1795 GET_VREG_U a0, a2 # a0 <- vBB (array object) 1796 GET_VREG a1, a3 # a1 <- vCC (requested index) 1797 beqz a0, common_errNullObject # bail if null array object 1798 lw a3, MIRROR_ARRAY_LENGTH_OFFSET(a0) # a3 <- arrayObj->length 1799 dlsa a0, a1, a0, 3 # a0 <- arrayObj + index*width 1800 bgeu a1, a3, common_errArrayIndex # unsigned compare: index >= length, bail 1801 FETCH_ADVANCE_INST 2 # advance rPC, load rINST 1802 lw a2, MIRROR_WIDE_ARRAY_DATA_OFFSET(a0) 1803 lw a3, (MIRROR_WIDE_ARRAY_DATA_OFFSET+4)(a0) 1804 dinsu a2, a3, 32, 32 # a2 <- vBB[vCC] 1805 GET_INST_OPCODE v0 # extract opcode from rINST 1806 SET_VREG_WIDE a2, a4 # vAA <- a2 1807 GOTO_OPCODE v0 # jump to next instruction 1808 1809/* ------------------------------ */ 1810 .balign 128 1811.L_op_aget_object: /* 0x46 */ 1812/* File: mips64/op_aget_object.S */ 1813 /* 1814 * Array object get. vAA <- vBB[vCC]. 1815 * 1816 * for: aget-object 1817 */ 1818 /* op vAA, vBB, vCC */ 1819 .extern artAGetObjectFromMterp 1820 lbu a2, 2(rPC) # a2 <- BB 1821 lbu a3, 3(rPC) # a3 <- CC 1822 EXPORT_PC 1823 GET_VREG_U a0, a2 # a0 <- vBB (array object) 1824 GET_VREG a1, a3 # a1 <- vCC (requested index) 1825 jal artAGetObjectFromMterp # (array, index) 1826 ld a1, THREAD_EXCEPTION_OFFSET(rSELF) 1827 srl a4, rINST, 8 # a4 <- AA 1828 PREFETCH_INST 2 1829 bnez a1, MterpException 1830 SET_VREG_OBJECT v0, a4 # vAA <- v0 1831 ADVANCE 2 1832 GET_INST_OPCODE v0 # extract opcode from rINST 1833 GOTO_OPCODE v0 # jump to next instruction 1834 1835/* ------------------------------ */ 1836 .balign 128 1837.L_op_aget_boolean: /* 0x47 */ 1838/* File: mips64/op_aget_boolean.S */ 1839/* File: mips64/op_aget.S */ 1840 /* 1841 * Array get, 32 bits or less. vAA <- vBB[vCC]. 1842 * 1843 * for: aget, aget-boolean, aget-byte, aget-char, aget-short 1844 * 1845 * NOTE: assumes data offset for arrays is the same for all non-wide types. 1846 * If this changes, specialize. 1847 */ 1848 /* op vAA, vBB, vCC */ 1849 lbu a2, 2(rPC) # a2 <- BB 1850 lbu a3, 3(rPC) # a3 <- CC 1851 srl a4, rINST, 8 # a4 <- AA 1852 GET_VREG_U a0, a2 # a0 <- vBB (array object) 1853 GET_VREG a1, a3 # a1 <- vCC (requested index) 1854 beqz a0, common_errNullObject # bail if null array object 1855 lw a3, MIRROR_ARRAY_LENGTH_OFFSET(a0) # a3 <- arrayObj->length 1856 .if 0 1857 # [d]lsa does not support shift count of 0. 1858 dlsa a0, a1, a0, 0 # a0 <- arrayObj + index*width 1859 .else 1860 daddu a0, a1, a0 # a0 <- arrayObj + index*width 1861 .endif 1862 bgeu a1, a3, common_errArrayIndex # unsigned compare: index >= length, bail 1863 FETCH_ADVANCE_INST 2 # advance rPC, load rINST 1864 lbu a2, MIRROR_BOOLEAN_ARRAY_DATA_OFFSET(a0) # a2 <- vBB[vCC] 1865 GET_INST_OPCODE v0 # extract opcode from rINST 1866 SET_VREG a2, a4 # vAA <- a2 1867 GOTO_OPCODE v0 # jump to next instruction 1868 1869 1870/* ------------------------------ */ 1871 .balign 128 1872.L_op_aget_byte: /* 0x48 */ 1873/* File: mips64/op_aget_byte.S */ 1874/* File: mips64/op_aget.S */ 1875 /* 1876 * Array get, 32 bits or less. vAA <- vBB[vCC]. 1877 * 1878 * for: aget, aget-boolean, aget-byte, aget-char, aget-short 1879 * 1880 * NOTE: assumes data offset for arrays is the same for all non-wide types. 1881 * If this changes, specialize. 1882 */ 1883 /* op vAA, vBB, vCC */ 1884 lbu a2, 2(rPC) # a2 <- BB 1885 lbu a3, 3(rPC) # a3 <- CC 1886 srl a4, rINST, 8 # a4 <- AA 1887 GET_VREG_U a0, a2 # a0 <- vBB (array object) 1888 GET_VREG a1, a3 # a1 <- vCC (requested index) 1889 beqz a0, common_errNullObject # bail if null array object 1890 lw a3, MIRROR_ARRAY_LENGTH_OFFSET(a0) # a3 <- arrayObj->length 1891 .if 0 1892 # [d]lsa does not support shift count of 0. 1893 dlsa a0, a1, a0, 0 # a0 <- arrayObj + index*width 1894 .else 1895 daddu a0, a1, a0 # a0 <- arrayObj + index*width 1896 .endif 1897 bgeu a1, a3, common_errArrayIndex # unsigned compare: index >= length, bail 1898 FETCH_ADVANCE_INST 2 # advance rPC, load rINST 1899 lb a2, MIRROR_BYTE_ARRAY_DATA_OFFSET(a0) # a2 <- vBB[vCC] 1900 GET_INST_OPCODE v0 # extract opcode from rINST 1901 SET_VREG a2, a4 # vAA <- a2 1902 GOTO_OPCODE v0 # jump to next instruction 1903 1904 1905/* ------------------------------ */ 1906 .balign 128 1907.L_op_aget_char: /* 0x49 */ 1908/* File: mips64/op_aget_char.S */ 1909/* File: mips64/op_aget.S */ 1910 /* 1911 * Array get, 32 bits or less. vAA <- vBB[vCC]. 1912 * 1913 * for: aget, aget-boolean, aget-byte, aget-char, aget-short 1914 * 1915 * NOTE: assumes data offset for arrays is the same for all non-wide types. 1916 * If this changes, specialize. 1917 */ 1918 /* op vAA, vBB, vCC */ 1919 lbu a2, 2(rPC) # a2 <- BB 1920 lbu a3, 3(rPC) # a3 <- CC 1921 srl a4, rINST, 8 # a4 <- AA 1922 GET_VREG_U a0, a2 # a0 <- vBB (array object) 1923 GET_VREG a1, a3 # a1 <- vCC (requested index) 1924 beqz a0, common_errNullObject # bail if null array object 1925 lw a3, MIRROR_ARRAY_LENGTH_OFFSET(a0) # a3 <- arrayObj->length 1926 .if 1 1927 # [d]lsa does not support shift count of 0. 1928 dlsa a0, a1, a0, 1 # a0 <- arrayObj + index*width 1929 .else 1930 daddu a0, a1, a0 # a0 <- arrayObj + index*width 1931 .endif 1932 bgeu a1, a3, common_errArrayIndex # unsigned compare: index >= length, bail 1933 FETCH_ADVANCE_INST 2 # advance rPC, load rINST 1934 lhu a2, MIRROR_CHAR_ARRAY_DATA_OFFSET(a0) # a2 <- vBB[vCC] 1935 GET_INST_OPCODE v0 # extract opcode from rINST 1936 SET_VREG a2, a4 # vAA <- a2 1937 GOTO_OPCODE v0 # jump to next instruction 1938 1939 1940/* ------------------------------ */ 1941 .balign 128 1942.L_op_aget_short: /* 0x4a */ 1943/* File: mips64/op_aget_short.S */ 1944/* File: mips64/op_aget.S */ 1945 /* 1946 * Array get, 32 bits or less. vAA <- vBB[vCC]. 1947 * 1948 * for: aget, aget-boolean, aget-byte, aget-char, aget-short 1949 * 1950 * NOTE: assumes data offset for arrays is the same for all non-wide types. 1951 * If this changes, specialize. 1952 */ 1953 /* op vAA, vBB, vCC */ 1954 lbu a2, 2(rPC) # a2 <- BB 1955 lbu a3, 3(rPC) # a3 <- CC 1956 srl a4, rINST, 8 # a4 <- AA 1957 GET_VREG_U a0, a2 # a0 <- vBB (array object) 1958 GET_VREG a1, a3 # a1 <- vCC (requested index) 1959 beqz a0, common_errNullObject # bail if null array object 1960 lw a3, MIRROR_ARRAY_LENGTH_OFFSET(a0) # a3 <- arrayObj->length 1961 .if 1 1962 # [d]lsa does not support shift count of 0. 1963 dlsa a0, a1, a0, 1 # a0 <- arrayObj + index*width 1964 .else 1965 daddu a0, a1, a0 # a0 <- arrayObj + index*width 1966 .endif 1967 bgeu a1, a3, common_errArrayIndex # unsigned compare: index >= length, bail 1968 FETCH_ADVANCE_INST 2 # advance rPC, load rINST 1969 lh a2, MIRROR_SHORT_ARRAY_DATA_OFFSET(a0) # a2 <- vBB[vCC] 1970 GET_INST_OPCODE v0 # extract opcode from rINST 1971 SET_VREG a2, a4 # vAA <- a2 1972 GOTO_OPCODE v0 # jump to next instruction 1973 1974 1975/* ------------------------------ */ 1976 .balign 128 1977.L_op_aput: /* 0x4b */ 1978/* File: mips64/op_aput.S */ 1979 /* 1980 * Array put, 32 bits or less. vBB[vCC] <- vAA. 1981 * 1982 * for: aput, aput-boolean, aput-byte, aput-char, aput-short 1983 * 1984 * NOTE: this assumes data offset for arrays is the same for all non-wide types. 1985 * If this changes, specialize. 1986 */ 1987 /* op vAA, vBB, vCC */ 1988 lbu a2, 2(rPC) # a2 <- BB 1989 lbu a3, 3(rPC) # a3 <- CC 1990 srl a4, rINST, 8 # a4 <- AA 1991 GET_VREG_U a0, a2 # a0 <- vBB (array object) 1992 GET_VREG a1, a3 # a1 <- vCC (requested index) 1993 beqz a0, common_errNullObject # bail if null array object 1994 lw a3, MIRROR_ARRAY_LENGTH_OFFSET(a0) # a3 <- arrayObj->length 1995 .if 2 1996 # [d]lsa does not support shift count of 0. 1997 dlsa a0, a1, a0, 2 # a0 <- arrayObj + index*width 1998 .else 1999 daddu a0, a1, a0 # a0 <- arrayObj + index*width 2000 .endif 2001 bgeu a1, a3, common_errArrayIndex # unsigned compare: index >= length, bail 2002 FETCH_ADVANCE_INST 2 # advance rPC, load rINST 2003 GET_VREG a2, a4 # a2 <- vAA 2004 GET_INST_OPCODE v0 # extract opcode from rINST 2005 sw a2, MIRROR_INT_ARRAY_DATA_OFFSET(a0) # vBB[vCC] <- a2 2006 GOTO_OPCODE v0 # jump to next instruction 2007 2008/* ------------------------------ */ 2009 .balign 128 2010.L_op_aput_wide: /* 0x4c */ 2011/* File: mips64/op_aput_wide.S */ 2012 /* 2013 * Array put, 64 bits. vBB[vCC] <- vAA. 2014 * 2015 */ 2016 /* aput-wide vAA, vBB, vCC */ 2017 lbu a2, 2(rPC) # a2 <- BB 2018 lbu a3, 3(rPC) # a3 <- CC 2019 srl a4, rINST, 8 # a4 <- AA 2020 GET_VREG_U a0, a2 # a0 <- vBB (array object) 2021 GET_VREG a1, a3 # a1 <- vCC (requested index) 2022 beqz a0, common_errNullObject # bail if null array object 2023 lw a3, MIRROR_ARRAY_LENGTH_OFFSET(a0) # a3 <- arrayObj->length 2024 dlsa a0, a1, a0, 3 # a0 <- arrayObj + index*width 2025 bgeu a1, a3, common_errArrayIndex # unsigned compare: index >= length, bail 2026 GET_VREG_WIDE a2, a4 # a2 <- vAA 2027 FETCH_ADVANCE_INST 2 # advance rPC, load rINST 2028 GET_INST_OPCODE v0 # extract opcode from rINST 2029 sw a2, MIRROR_WIDE_ARRAY_DATA_OFFSET(a0) 2030 dsrl32 a2, a2, 0 2031 sw a2, (MIRROR_WIDE_ARRAY_DATA_OFFSET+4)(a0) # vBB[vCC] <- a2 2032 GOTO_OPCODE v0 # jump to next instruction 2033 2034/* ------------------------------ */ 2035 .balign 128 2036.L_op_aput_object: /* 0x4d */ 2037/* File: mips64/op_aput_object.S */ 2038 /* 2039 * Store an object into an array. vBB[vCC] <- vAA. 2040 */ 2041 /* op vAA, vBB, vCC */ 2042 .extern MterpAputObject 2043 EXPORT_PC 2044 daddu a0, rFP, OFF_FP_SHADOWFRAME 2045 move a1, rPC 2046 move a2, rINST 2047 jal MterpAputObject 2048 beqzc v0, MterpPossibleException 2049 FETCH_ADVANCE_INST 2 # advance rPC, load rINST 2050 GET_INST_OPCODE v0 # extract opcode from rINST 2051 GOTO_OPCODE v0 # jump to next instruction 2052 2053/* ------------------------------ */ 2054 .balign 128 2055.L_op_aput_boolean: /* 0x4e */ 2056/* File: mips64/op_aput_boolean.S */ 2057/* File: mips64/op_aput.S */ 2058 /* 2059 * Array put, 32 bits or less. vBB[vCC] <- vAA. 2060 * 2061 * for: aput, aput-boolean, aput-byte, aput-char, aput-short 2062 * 2063 * NOTE: this assumes data offset for arrays is the same for all non-wide types. 2064 * If this changes, specialize. 2065 */ 2066 /* op vAA, vBB, vCC */ 2067 lbu a2, 2(rPC) # a2 <- BB 2068 lbu a3, 3(rPC) # a3 <- CC 2069 srl a4, rINST, 8 # a4 <- AA 2070 GET_VREG_U a0, a2 # a0 <- vBB (array object) 2071 GET_VREG a1, a3 # a1 <- vCC (requested index) 2072 beqz a0, common_errNullObject # bail if null array object 2073 lw a3, MIRROR_ARRAY_LENGTH_OFFSET(a0) # a3 <- arrayObj->length 2074 .if 0 2075 # [d]lsa does not support shift count of 0. 2076 dlsa a0, a1, a0, 0 # a0 <- arrayObj + index*width 2077 .else 2078 daddu a0, a1, a0 # a0 <- arrayObj + index*width 2079 .endif 2080 bgeu a1, a3, common_errArrayIndex # unsigned compare: index >= length, bail 2081 FETCH_ADVANCE_INST 2 # advance rPC, load rINST 2082 GET_VREG a2, a4 # a2 <- vAA 2083 GET_INST_OPCODE v0 # extract opcode from rINST 2084 sb a2, MIRROR_BOOLEAN_ARRAY_DATA_OFFSET(a0) # vBB[vCC] <- a2 2085 GOTO_OPCODE v0 # jump to next instruction 2086 2087 2088/* ------------------------------ */ 2089 .balign 128 2090.L_op_aput_byte: /* 0x4f */ 2091/* File: mips64/op_aput_byte.S */ 2092/* File: mips64/op_aput.S */ 2093 /* 2094 * Array put, 32 bits or less. vBB[vCC] <- vAA. 2095 * 2096 * for: aput, aput-boolean, aput-byte, aput-char, aput-short 2097 * 2098 * NOTE: this assumes data offset for arrays is the same for all non-wide types. 2099 * If this changes, specialize. 2100 */ 2101 /* op vAA, vBB, vCC */ 2102 lbu a2, 2(rPC) # a2 <- BB 2103 lbu a3, 3(rPC) # a3 <- CC 2104 srl a4, rINST, 8 # a4 <- AA 2105 GET_VREG_U a0, a2 # a0 <- vBB (array object) 2106 GET_VREG a1, a3 # a1 <- vCC (requested index) 2107 beqz a0, common_errNullObject # bail if null array object 2108 lw a3, MIRROR_ARRAY_LENGTH_OFFSET(a0) # a3 <- arrayObj->length 2109 .if 0 2110 # [d]lsa does not support shift count of 0. 2111 dlsa a0, a1, a0, 0 # a0 <- arrayObj + index*width 2112 .else 2113 daddu a0, a1, a0 # a0 <- arrayObj + index*width 2114 .endif 2115 bgeu a1, a3, common_errArrayIndex # unsigned compare: index >= length, bail 2116 FETCH_ADVANCE_INST 2 # advance rPC, load rINST 2117 GET_VREG a2, a4 # a2 <- vAA 2118 GET_INST_OPCODE v0 # extract opcode from rINST 2119 sb a2, MIRROR_BYTE_ARRAY_DATA_OFFSET(a0) # vBB[vCC] <- a2 2120 GOTO_OPCODE v0 # jump to next instruction 2121 2122 2123/* ------------------------------ */ 2124 .balign 128 2125.L_op_aput_char: /* 0x50 */ 2126/* File: mips64/op_aput_char.S */ 2127/* File: mips64/op_aput.S */ 2128 /* 2129 * Array put, 32 bits or less. vBB[vCC] <- vAA. 2130 * 2131 * for: aput, aput-boolean, aput-byte, aput-char, aput-short 2132 * 2133 * NOTE: this assumes data offset for arrays is the same for all non-wide types. 2134 * If this changes, specialize. 2135 */ 2136 /* op vAA, vBB, vCC */ 2137 lbu a2, 2(rPC) # a2 <- BB 2138 lbu a3, 3(rPC) # a3 <- CC 2139 srl a4, rINST, 8 # a4 <- AA 2140 GET_VREG_U a0, a2 # a0 <- vBB (array object) 2141 GET_VREG a1, a3 # a1 <- vCC (requested index) 2142 beqz a0, common_errNullObject # bail if null array object 2143 lw a3, MIRROR_ARRAY_LENGTH_OFFSET(a0) # a3 <- arrayObj->length 2144 .if 1 2145 # [d]lsa does not support shift count of 0. 2146 dlsa a0, a1, a0, 1 # a0 <- arrayObj + index*width 2147 .else 2148 daddu a0, a1, a0 # a0 <- arrayObj + index*width 2149 .endif 2150 bgeu a1, a3, common_errArrayIndex # unsigned compare: index >= length, bail 2151 FETCH_ADVANCE_INST 2 # advance rPC, load rINST 2152 GET_VREG a2, a4 # a2 <- vAA 2153 GET_INST_OPCODE v0 # extract opcode from rINST 2154 sh a2, MIRROR_CHAR_ARRAY_DATA_OFFSET(a0) # vBB[vCC] <- a2 2155 GOTO_OPCODE v0 # jump to next instruction 2156 2157 2158/* ------------------------------ */ 2159 .balign 128 2160.L_op_aput_short: /* 0x51 */ 2161/* File: mips64/op_aput_short.S */ 2162/* File: mips64/op_aput.S */ 2163 /* 2164 * Array put, 32 bits or less. vBB[vCC] <- vAA. 2165 * 2166 * for: aput, aput-boolean, aput-byte, aput-char, aput-short 2167 * 2168 * NOTE: this assumes data offset for arrays is the same for all non-wide types. 2169 * If this changes, specialize. 2170 */ 2171 /* op vAA, vBB, vCC */ 2172 lbu a2, 2(rPC) # a2 <- BB 2173 lbu a3, 3(rPC) # a3 <- CC 2174 srl a4, rINST, 8 # a4 <- AA 2175 GET_VREG_U a0, a2 # a0 <- vBB (array object) 2176 GET_VREG a1, a3 # a1 <- vCC (requested index) 2177 beqz a0, common_errNullObject # bail if null array object 2178 lw a3, MIRROR_ARRAY_LENGTH_OFFSET(a0) # a3 <- arrayObj->length 2179 .if 1 2180 # [d]lsa does not support shift count of 0. 2181 dlsa a0, a1, a0, 1 # a0 <- arrayObj + index*width 2182 .else 2183 daddu a0, a1, a0 # a0 <- arrayObj + index*width 2184 .endif 2185 bgeu a1, a3, common_errArrayIndex # unsigned compare: index >= length, bail 2186 FETCH_ADVANCE_INST 2 # advance rPC, load rINST 2187 GET_VREG a2, a4 # a2 <- vAA 2188 GET_INST_OPCODE v0 # extract opcode from rINST 2189 sh a2, MIRROR_SHORT_ARRAY_DATA_OFFSET(a0) # vBB[vCC] <- a2 2190 GOTO_OPCODE v0 # jump to next instruction 2191 2192 2193/* ------------------------------ */ 2194 .balign 128 2195.L_op_iget: /* 0x52 */ 2196/* File: mips64/op_iget.S */ 2197 /* 2198 * General instance field get. 2199 * 2200 * for: iget, iget-object, iget-boolean, iget-byte, iget-char, iget-short 2201 */ 2202 .extern artGet32InstanceFromCode 2203 EXPORT_PC 2204 lhu a0, 2(rPC) # a0 <- field ref CCCC 2205 srl a1, rINST, 12 # a1 <- B 2206 GET_VREG_U a1, a1 # a1 <- fp[B], the object pointer 2207 ld a2, OFF_FP_METHOD(rFP) # a2 <- referrer 2208 move a3, rSELF # a3 <- self 2209 jal artGet32InstanceFromCode 2210 ld a3, THREAD_EXCEPTION_OFFSET(rSELF) 2211 ext a2, rINST, 8, 4 # a2 <- A 2212 PREFETCH_INST 2 2213 bnez a3, MterpPossibleException # bail out 2214 .if 0 2215 SET_VREG_OBJECT v0, a2 # fp[A] <- v0 2216 .else 2217 SET_VREG v0, a2 # fp[A] <- v0 2218 .endif 2219 ADVANCE 2 2220 GET_INST_OPCODE v0 # extract opcode from rINST 2221 GOTO_OPCODE v0 # jump to next instruction 2222 2223/* ------------------------------ */ 2224 .balign 128 2225.L_op_iget_wide: /* 0x53 */ 2226/* File: mips64/op_iget_wide.S */ 2227 /* 2228 * 64-bit instance field get. 2229 * 2230 * for: iget-wide 2231 */ 2232 .extern artGet64InstanceFromCode 2233 EXPORT_PC 2234 lhu a0, 2(rPC) # a0 <- field ref CCCC 2235 srl a1, rINST, 12 # a1 <- B 2236 GET_VREG_U a1, a1 # a1 <- fp[B], the object pointer 2237 ld a2, OFF_FP_METHOD(rFP) # a2 <- referrer 2238 move a3, rSELF # a3 <- self 2239 jal artGet64InstanceFromCode 2240 ld a3, THREAD_EXCEPTION_OFFSET(rSELF) 2241 ext a2, rINST, 8, 4 # a2 <- A 2242 PREFETCH_INST 2 2243 bnez a3, MterpPossibleException # bail out 2244 SET_VREG_WIDE v0, a2 # fp[A] <- v0 2245 ADVANCE 2 2246 GET_INST_OPCODE v0 # extract opcode from rINST 2247 GOTO_OPCODE v0 # jump to next instruction 2248 2249/* ------------------------------ */ 2250 .balign 128 2251.L_op_iget_object: /* 0x54 */ 2252/* File: mips64/op_iget_object.S */ 2253/* File: mips64/op_iget.S */ 2254 /* 2255 * General instance field get. 2256 * 2257 * for: iget, iget-object, iget-boolean, iget-byte, iget-char, iget-short 2258 */ 2259 .extern artGetObjInstanceFromCode 2260 EXPORT_PC 2261 lhu a0, 2(rPC) # a0 <- field ref CCCC 2262 srl a1, rINST, 12 # a1 <- B 2263 GET_VREG_U a1, a1 # a1 <- fp[B], the object pointer 2264 ld a2, OFF_FP_METHOD(rFP) # a2 <- referrer 2265 move a3, rSELF # a3 <- self 2266 jal artGetObjInstanceFromCode 2267 ld a3, THREAD_EXCEPTION_OFFSET(rSELF) 2268 ext a2, rINST, 8, 4 # a2 <- A 2269 PREFETCH_INST 2 2270 bnez a3, MterpPossibleException # bail out 2271 .if 1 2272 SET_VREG_OBJECT v0, a2 # fp[A] <- v0 2273 .else 2274 SET_VREG v0, a2 # fp[A] <- v0 2275 .endif 2276 ADVANCE 2 2277 GET_INST_OPCODE v0 # extract opcode from rINST 2278 GOTO_OPCODE v0 # jump to next instruction 2279 2280 2281/* ------------------------------ */ 2282 .balign 128 2283.L_op_iget_boolean: /* 0x55 */ 2284/* File: mips64/op_iget_boolean.S */ 2285/* File: mips64/op_iget.S */ 2286 /* 2287 * General instance field get. 2288 * 2289 * for: iget, iget-object, iget-boolean, iget-byte, iget-char, iget-short 2290 */ 2291 .extern artGetBooleanInstanceFromCode 2292 EXPORT_PC 2293 lhu a0, 2(rPC) # a0 <- field ref CCCC 2294 srl a1, rINST, 12 # a1 <- B 2295 GET_VREG_U a1, a1 # a1 <- fp[B], the object pointer 2296 ld a2, OFF_FP_METHOD(rFP) # a2 <- referrer 2297 move a3, rSELF # a3 <- self 2298 jal artGetBooleanInstanceFromCode 2299 ld a3, THREAD_EXCEPTION_OFFSET(rSELF) 2300 ext a2, rINST, 8, 4 # a2 <- A 2301 PREFETCH_INST 2 2302 bnez a3, MterpPossibleException # bail out 2303 .if 0 2304 SET_VREG_OBJECT v0, a2 # fp[A] <- v0 2305 .else 2306 SET_VREG v0, a2 # fp[A] <- v0 2307 .endif 2308 ADVANCE 2 2309 GET_INST_OPCODE v0 # extract opcode from rINST 2310 GOTO_OPCODE v0 # jump to next instruction 2311 2312 2313/* ------------------------------ */ 2314 .balign 128 2315.L_op_iget_byte: /* 0x56 */ 2316/* File: mips64/op_iget_byte.S */ 2317/* File: mips64/op_iget.S */ 2318 /* 2319 * General instance field get. 2320 * 2321 * for: iget, iget-object, iget-boolean, iget-byte, iget-char, iget-short 2322 */ 2323 .extern artGetByteInstanceFromCode 2324 EXPORT_PC 2325 lhu a0, 2(rPC) # a0 <- field ref CCCC 2326 srl a1, rINST, 12 # a1 <- B 2327 GET_VREG_U a1, a1 # a1 <- fp[B], the object pointer 2328 ld a2, OFF_FP_METHOD(rFP) # a2 <- referrer 2329 move a3, rSELF # a3 <- self 2330 jal artGetByteInstanceFromCode 2331 ld a3, THREAD_EXCEPTION_OFFSET(rSELF) 2332 ext a2, rINST, 8, 4 # a2 <- A 2333 PREFETCH_INST 2 2334 bnez a3, MterpPossibleException # bail out 2335 .if 0 2336 SET_VREG_OBJECT v0, a2 # fp[A] <- v0 2337 .else 2338 SET_VREG v0, a2 # fp[A] <- v0 2339 .endif 2340 ADVANCE 2 2341 GET_INST_OPCODE v0 # extract opcode from rINST 2342 GOTO_OPCODE v0 # jump to next instruction 2343 2344 2345/* ------------------------------ */ 2346 .balign 128 2347.L_op_iget_char: /* 0x57 */ 2348/* File: mips64/op_iget_char.S */ 2349/* File: mips64/op_iget.S */ 2350 /* 2351 * General instance field get. 2352 * 2353 * for: iget, iget-object, iget-boolean, iget-byte, iget-char, iget-short 2354 */ 2355 .extern artGetCharInstanceFromCode 2356 EXPORT_PC 2357 lhu a0, 2(rPC) # a0 <- field ref CCCC 2358 srl a1, rINST, 12 # a1 <- B 2359 GET_VREG_U a1, a1 # a1 <- fp[B], the object pointer 2360 ld a2, OFF_FP_METHOD(rFP) # a2 <- referrer 2361 move a3, rSELF # a3 <- self 2362 jal artGetCharInstanceFromCode 2363 ld a3, THREAD_EXCEPTION_OFFSET(rSELF) 2364 ext a2, rINST, 8, 4 # a2 <- A 2365 PREFETCH_INST 2 2366 bnez a3, MterpPossibleException # bail out 2367 .if 0 2368 SET_VREG_OBJECT v0, a2 # fp[A] <- v0 2369 .else 2370 SET_VREG v0, a2 # fp[A] <- v0 2371 .endif 2372 ADVANCE 2 2373 GET_INST_OPCODE v0 # extract opcode from rINST 2374 GOTO_OPCODE v0 # jump to next instruction 2375 2376 2377/* ------------------------------ */ 2378 .balign 128 2379.L_op_iget_short: /* 0x58 */ 2380/* File: mips64/op_iget_short.S */ 2381/* File: mips64/op_iget.S */ 2382 /* 2383 * General instance field get. 2384 * 2385 * for: iget, iget-object, iget-boolean, iget-byte, iget-char, iget-short 2386 */ 2387 .extern artGetShortInstanceFromCode 2388 EXPORT_PC 2389 lhu a0, 2(rPC) # a0 <- field ref CCCC 2390 srl a1, rINST, 12 # a1 <- B 2391 GET_VREG_U a1, a1 # a1 <- fp[B], the object pointer 2392 ld a2, OFF_FP_METHOD(rFP) # a2 <- referrer 2393 move a3, rSELF # a3 <- self 2394 jal artGetShortInstanceFromCode 2395 ld a3, THREAD_EXCEPTION_OFFSET(rSELF) 2396 ext a2, rINST, 8, 4 # a2 <- A 2397 PREFETCH_INST 2 2398 bnez a3, MterpPossibleException # bail out 2399 .if 0 2400 SET_VREG_OBJECT v0, a2 # fp[A] <- v0 2401 .else 2402 SET_VREG v0, a2 # fp[A] <- v0 2403 .endif 2404 ADVANCE 2 2405 GET_INST_OPCODE v0 # extract opcode from rINST 2406 GOTO_OPCODE v0 # jump to next instruction 2407 2408 2409/* ------------------------------ */ 2410 .balign 128 2411.L_op_iput: /* 0x59 */ 2412/* File: mips64/op_iput.S */ 2413 /* 2414 * General 32-bit instance field put. 2415 * 2416 * for: iput, iput-boolean, iput-byte, iput-char, iput-short 2417 */ 2418 /* op vA, vB, field//CCCC */ 2419 .extern artSet32InstanceFromMterp 2420 EXPORT_PC 2421 lhu a0, 2(rPC) # a0 <- field ref CCCC 2422 srl a1, rINST, 12 # a1 <- B 2423 GET_VREG_U a1, a1 # a1 <- fp[B], the object pointer 2424 ext a2, rINST, 8, 4 # a2 <- A 2425 GET_VREG a2, a2 # a2 <- fp[A] 2426 ld a3, OFF_FP_METHOD(rFP) # a3 <- referrer 2427 PREFETCH_INST 2 2428 jal artSet32InstanceFromMterp 2429 bnez v0, MterpPossibleException # bail out 2430 ADVANCE 2 2431 GET_INST_OPCODE v0 # extract opcode from rINST 2432 GOTO_OPCODE v0 # jump to next instruction 2433 2434/* ------------------------------ */ 2435 .balign 128 2436.L_op_iput_wide: /* 0x5a */ 2437/* File: mips64/op_iput_wide.S */ 2438 /* iput-wide vA, vB, field//CCCC */ 2439 .extern artSet64InstanceFromMterp 2440 EXPORT_PC 2441 lhu a0, 2(rPC) # a0 <- field ref CCCC 2442 srl a1, rINST, 12 # a1 <- B 2443 GET_VREG_U a1, a1 # a1 <- fp[B], the object pointer 2444 ext a2, rINST, 8, 4 # a2 <- A 2445 dlsa a2, a2, rFP, 2 # a2 <- &fp[A] 2446 ld a3, OFF_FP_METHOD(rFP) # a3 <- referrer 2447 PREFETCH_INST 2 2448 jal artSet64InstanceFromMterp 2449 bnez v0, MterpPossibleException # bail out 2450 ADVANCE 2 2451 GET_INST_OPCODE v0 # extract opcode from rINST 2452 GOTO_OPCODE v0 # jump to next instruction 2453 2454/* ------------------------------ */ 2455 .balign 128 2456.L_op_iput_object: /* 0x5b */ 2457/* File: mips64/op_iput_object.S */ 2458 .extern MterpIputObject 2459 EXPORT_PC 2460 daddu a0, rFP, OFF_FP_SHADOWFRAME 2461 move a1, rPC 2462 move a2, rINST 2463 move a3, rSELF 2464 jal MterpIputObject 2465 beqzc v0, MterpException 2466 FETCH_ADVANCE_INST 2 # advance rPC, load rINST 2467 GET_INST_OPCODE v0 # extract opcode from rINST 2468 GOTO_OPCODE v0 # jump to next instruction 2469 2470/* ------------------------------ */ 2471 .balign 128 2472.L_op_iput_boolean: /* 0x5c */ 2473/* File: mips64/op_iput_boolean.S */ 2474/* File: mips64/op_iput.S */ 2475 /* 2476 * General 32-bit instance field put. 2477 * 2478 * for: iput, iput-boolean, iput-byte, iput-char, iput-short 2479 */ 2480 /* op vA, vB, field//CCCC */ 2481 .extern artSet8InstanceFromMterp 2482 EXPORT_PC 2483 lhu a0, 2(rPC) # a0 <- field ref CCCC 2484 srl a1, rINST, 12 # a1 <- B 2485 GET_VREG_U a1, a1 # a1 <- fp[B], the object pointer 2486 ext a2, rINST, 8, 4 # a2 <- A 2487 GET_VREG a2, a2 # a2 <- fp[A] 2488 ld a3, OFF_FP_METHOD(rFP) # a3 <- referrer 2489 PREFETCH_INST 2 2490 jal artSet8InstanceFromMterp 2491 bnez v0, MterpPossibleException # bail out 2492 ADVANCE 2 2493 GET_INST_OPCODE v0 # extract opcode from rINST 2494 GOTO_OPCODE v0 # jump to next instruction 2495 2496 2497/* ------------------------------ */ 2498 .balign 128 2499.L_op_iput_byte: /* 0x5d */ 2500/* File: mips64/op_iput_byte.S */ 2501/* File: mips64/op_iput.S */ 2502 /* 2503 * General 32-bit instance field put. 2504 * 2505 * for: iput, iput-boolean, iput-byte, iput-char, iput-short 2506 */ 2507 /* op vA, vB, field//CCCC */ 2508 .extern artSet8InstanceFromMterp 2509 EXPORT_PC 2510 lhu a0, 2(rPC) # a0 <- field ref CCCC 2511 srl a1, rINST, 12 # a1 <- B 2512 GET_VREG_U a1, a1 # a1 <- fp[B], the object pointer 2513 ext a2, rINST, 8, 4 # a2 <- A 2514 GET_VREG a2, a2 # a2 <- fp[A] 2515 ld a3, OFF_FP_METHOD(rFP) # a3 <- referrer 2516 PREFETCH_INST 2 2517 jal artSet8InstanceFromMterp 2518 bnez v0, MterpPossibleException # bail out 2519 ADVANCE 2 2520 GET_INST_OPCODE v0 # extract opcode from rINST 2521 GOTO_OPCODE v0 # jump to next instruction 2522 2523 2524/* ------------------------------ */ 2525 .balign 128 2526.L_op_iput_char: /* 0x5e */ 2527/* File: mips64/op_iput_char.S */ 2528/* File: mips64/op_iput.S */ 2529 /* 2530 * General 32-bit instance field put. 2531 * 2532 * for: iput, iput-boolean, iput-byte, iput-char, iput-short 2533 */ 2534 /* op vA, vB, field//CCCC */ 2535 .extern artSet16InstanceFromMterp 2536 EXPORT_PC 2537 lhu a0, 2(rPC) # a0 <- field ref CCCC 2538 srl a1, rINST, 12 # a1 <- B 2539 GET_VREG_U a1, a1 # a1 <- fp[B], the object pointer 2540 ext a2, rINST, 8, 4 # a2 <- A 2541 GET_VREG a2, a2 # a2 <- fp[A] 2542 ld a3, OFF_FP_METHOD(rFP) # a3 <- referrer 2543 PREFETCH_INST 2 2544 jal artSet16InstanceFromMterp 2545 bnez v0, MterpPossibleException # bail out 2546 ADVANCE 2 2547 GET_INST_OPCODE v0 # extract opcode from rINST 2548 GOTO_OPCODE v0 # jump to next instruction 2549 2550 2551/* ------------------------------ */ 2552 .balign 128 2553.L_op_iput_short: /* 0x5f */ 2554/* File: mips64/op_iput_short.S */ 2555/* File: mips64/op_iput.S */ 2556 /* 2557 * General 32-bit instance field put. 2558 * 2559 * for: iput, iput-boolean, iput-byte, iput-char, iput-short 2560 */ 2561 /* op vA, vB, field//CCCC */ 2562 .extern artSet16InstanceFromMterp 2563 EXPORT_PC 2564 lhu a0, 2(rPC) # a0 <- field ref CCCC 2565 srl a1, rINST, 12 # a1 <- B 2566 GET_VREG_U a1, a1 # a1 <- fp[B], the object pointer 2567 ext a2, rINST, 8, 4 # a2 <- A 2568 GET_VREG a2, a2 # a2 <- fp[A] 2569 ld a3, OFF_FP_METHOD(rFP) # a3 <- referrer 2570 PREFETCH_INST 2 2571 jal artSet16InstanceFromMterp 2572 bnez v0, MterpPossibleException # bail out 2573 ADVANCE 2 2574 GET_INST_OPCODE v0 # extract opcode from rINST 2575 GOTO_OPCODE v0 # jump to next instruction 2576 2577 2578/* ------------------------------ */ 2579 .balign 128 2580.L_op_sget: /* 0x60 */ 2581/* File: mips64/op_sget.S */ 2582 /* 2583 * General SGET handler wrapper. 2584 * 2585 * for: sget, sget-object, sget-boolean, sget-byte, sget-char, sget-short 2586 */ 2587 /* op vAA, field//BBBB */ 2588 .extern MterpGet32Static 2589 EXPORT_PC 2590 lhu a0, 2(rPC) # a0 <- field ref BBBB 2591 ld a1, OFF_FP_METHOD(rFP) 2592 move a2, rSELF 2593 jal MterpGet32Static 2594 ld a3, THREAD_EXCEPTION_OFFSET(rSELF) 2595 srl a2, rINST, 8 # a2 <- AA 2596 2597 PREFETCH_INST 2 2598 bnez a3, MterpException # bail out 2599 .if 0 2600 SET_VREG_OBJECT v0, a2 # fp[AA] <- v0 2601 .else 2602 SET_VREG v0, a2 # fp[AA] <- v0 2603 .endif 2604 ADVANCE 2 2605 GET_INST_OPCODE v0 # extract opcode from rINST 2606 GOTO_OPCODE v0 2607 2608/* ------------------------------ */ 2609 .balign 128 2610.L_op_sget_wide: /* 0x61 */ 2611/* File: mips64/op_sget_wide.S */ 2612 /* 2613 * SGET_WIDE handler wrapper. 2614 * 2615 */ 2616 /* sget-wide vAA, field//BBBB */ 2617 .extern MterpGet64Static 2618 EXPORT_PC 2619 lhu a0, 2(rPC) # a0 <- field ref BBBB 2620 ld a1, OFF_FP_METHOD(rFP) 2621 move a2, rSELF 2622 jal MterpGet64Static 2623 ld a3, THREAD_EXCEPTION_OFFSET(rSELF) 2624 srl a4, rINST, 8 # a4 <- AA 2625 bnez a3, MterpException # bail out 2626 FETCH_ADVANCE_INST 2 # advance rPC, load rINST 2627 SET_VREG_WIDE v0, a4 2628 GET_INST_OPCODE v0 # extract opcode from rINST 2629 GOTO_OPCODE v0 # jump to next instruction 2630 2631/* ------------------------------ */ 2632 .balign 128 2633.L_op_sget_object: /* 0x62 */ 2634/* File: mips64/op_sget_object.S */ 2635/* File: mips64/op_sget.S */ 2636 /* 2637 * General SGET handler wrapper. 2638 * 2639 * for: sget, sget-object, sget-boolean, sget-byte, sget-char, sget-short 2640 */ 2641 /* op vAA, field//BBBB */ 2642 .extern MterpGetObjStatic 2643 EXPORT_PC 2644 lhu a0, 2(rPC) # a0 <- field ref BBBB 2645 ld a1, OFF_FP_METHOD(rFP) 2646 move a2, rSELF 2647 jal MterpGetObjStatic 2648 ld a3, THREAD_EXCEPTION_OFFSET(rSELF) 2649 srl a2, rINST, 8 # a2 <- AA 2650 2651 PREFETCH_INST 2 2652 bnez a3, MterpException # bail out 2653 .if 1 2654 SET_VREG_OBJECT v0, a2 # fp[AA] <- v0 2655 .else 2656 SET_VREG v0, a2 # fp[AA] <- v0 2657 .endif 2658 ADVANCE 2 2659 GET_INST_OPCODE v0 # extract opcode from rINST 2660 GOTO_OPCODE v0 2661 2662 2663/* ------------------------------ */ 2664 .balign 128 2665.L_op_sget_boolean: /* 0x63 */ 2666/* File: mips64/op_sget_boolean.S */ 2667/* File: mips64/op_sget.S */ 2668 /* 2669 * General SGET handler wrapper. 2670 * 2671 * for: sget, sget-object, sget-boolean, sget-byte, sget-char, sget-short 2672 */ 2673 /* op vAA, field//BBBB */ 2674 .extern MterpGetBooleanStatic 2675 EXPORT_PC 2676 lhu a0, 2(rPC) # a0 <- field ref BBBB 2677 ld a1, OFF_FP_METHOD(rFP) 2678 move a2, rSELF 2679 jal MterpGetBooleanStatic 2680 ld a3, THREAD_EXCEPTION_OFFSET(rSELF) 2681 srl a2, rINST, 8 # a2 <- AA 2682 and v0, v0, 0xff 2683 PREFETCH_INST 2 2684 bnez a3, MterpException # bail out 2685 .if 0 2686 SET_VREG_OBJECT v0, a2 # fp[AA] <- v0 2687 .else 2688 SET_VREG v0, a2 # fp[AA] <- v0 2689 .endif 2690 ADVANCE 2 2691 GET_INST_OPCODE v0 # extract opcode from rINST 2692 GOTO_OPCODE v0 2693 2694 2695/* ------------------------------ */ 2696 .balign 128 2697.L_op_sget_byte: /* 0x64 */ 2698/* File: mips64/op_sget_byte.S */ 2699/* File: mips64/op_sget.S */ 2700 /* 2701 * General SGET handler wrapper. 2702 * 2703 * for: sget, sget-object, sget-boolean, sget-byte, sget-char, sget-short 2704 */ 2705 /* op vAA, field//BBBB */ 2706 .extern MterpGetByteStatic 2707 EXPORT_PC 2708 lhu a0, 2(rPC) # a0 <- field ref BBBB 2709 ld a1, OFF_FP_METHOD(rFP) 2710 move a2, rSELF 2711 jal MterpGetByteStatic 2712 ld a3, THREAD_EXCEPTION_OFFSET(rSELF) 2713 srl a2, rINST, 8 # a2 <- AA 2714 seb v0, v0 2715 PREFETCH_INST 2 2716 bnez a3, MterpException # bail out 2717 .if 0 2718 SET_VREG_OBJECT v0, a2 # fp[AA] <- v0 2719 .else 2720 SET_VREG v0, a2 # fp[AA] <- v0 2721 .endif 2722 ADVANCE 2 2723 GET_INST_OPCODE v0 # extract opcode from rINST 2724 GOTO_OPCODE v0 2725 2726 2727/* ------------------------------ */ 2728 .balign 128 2729.L_op_sget_char: /* 0x65 */ 2730/* File: mips64/op_sget_char.S */ 2731/* File: mips64/op_sget.S */ 2732 /* 2733 * General SGET handler wrapper. 2734 * 2735 * for: sget, sget-object, sget-boolean, sget-byte, sget-char, sget-short 2736 */ 2737 /* op vAA, field//BBBB */ 2738 .extern MterpGetCharStatic 2739 EXPORT_PC 2740 lhu a0, 2(rPC) # a0 <- field ref BBBB 2741 ld a1, OFF_FP_METHOD(rFP) 2742 move a2, rSELF 2743 jal MterpGetCharStatic 2744 ld a3, THREAD_EXCEPTION_OFFSET(rSELF) 2745 srl a2, rINST, 8 # a2 <- AA 2746 and v0, v0, 0xffff 2747 PREFETCH_INST 2 2748 bnez a3, MterpException # bail out 2749 .if 0 2750 SET_VREG_OBJECT v0, a2 # fp[AA] <- v0 2751 .else 2752 SET_VREG v0, a2 # fp[AA] <- v0 2753 .endif 2754 ADVANCE 2 2755 GET_INST_OPCODE v0 # extract opcode from rINST 2756 GOTO_OPCODE v0 2757 2758 2759/* ------------------------------ */ 2760 .balign 128 2761.L_op_sget_short: /* 0x66 */ 2762/* File: mips64/op_sget_short.S */ 2763/* File: mips64/op_sget.S */ 2764 /* 2765 * General SGET handler wrapper. 2766 * 2767 * for: sget, sget-object, sget-boolean, sget-byte, sget-char, sget-short 2768 */ 2769 /* op vAA, field//BBBB */ 2770 .extern MterpGetShortStatic 2771 EXPORT_PC 2772 lhu a0, 2(rPC) # a0 <- field ref BBBB 2773 ld a1, OFF_FP_METHOD(rFP) 2774 move a2, rSELF 2775 jal MterpGetShortStatic 2776 ld a3, THREAD_EXCEPTION_OFFSET(rSELF) 2777 srl a2, rINST, 8 # a2 <- AA 2778 seh v0, v0 2779 PREFETCH_INST 2 2780 bnez a3, MterpException # bail out 2781 .if 0 2782 SET_VREG_OBJECT v0, a2 # fp[AA] <- v0 2783 .else 2784 SET_VREG v0, a2 # fp[AA] <- v0 2785 .endif 2786 ADVANCE 2 2787 GET_INST_OPCODE v0 # extract opcode from rINST 2788 GOTO_OPCODE v0 2789 2790 2791/* ------------------------------ */ 2792 .balign 128 2793.L_op_sput: /* 0x67 */ 2794/* File: mips64/op_sput.S */ 2795 /* 2796 * General SPUT handler wrapper. 2797 * 2798 * for: sput, sput-boolean, sput-byte, sput-char, sput-short 2799 */ 2800 /* op vAA, field//BBBB */ 2801 .extern MterpSet32Static 2802 EXPORT_PC 2803 lhu a0, 2(rPC) # a0 <- field ref BBBB 2804 srl a3, rINST, 8 # a3 <- AA 2805 GET_VREG a1, a3 # a1 <- fp[AA] 2806 ld a2, OFF_FP_METHOD(rFP) 2807 move a3, rSELF 2808 PREFETCH_INST 2 # Get next inst, but don't advance rPC 2809 jal MterpSet32Static 2810 bnezc v0, MterpException # 0 on success 2811 ADVANCE 2 # Past exception point - now advance rPC 2812 GET_INST_OPCODE v0 # extract opcode from rINST 2813 GOTO_OPCODE v0 # jump to next instruction 2814 2815/* ------------------------------ */ 2816 .balign 128 2817.L_op_sput_wide: /* 0x68 */ 2818/* File: mips64/op_sput_wide.S */ 2819 /* 2820 * SPUT_WIDE handler wrapper. 2821 * 2822 */ 2823 /* sput-wide vAA, field//BBBB */ 2824 .extern MterpSet64Static 2825 EXPORT_PC 2826 lhu a0, 2(rPC) # a0 <- field ref BBBB 2827 srl a1, rINST, 8 # a2 <- AA 2828 dlsa a1, a1, rFP, 2 2829 ld a2, OFF_FP_METHOD(rFP) 2830 move a3, rSELF 2831 PREFETCH_INST 2 # Get next inst, but don't advance rPC 2832 jal MterpSet64Static 2833 bnezc v0, MterpException # 0 on success, -1 on failure 2834 ADVANCE 2 # Past exception point - now advance rPC 2835 GET_INST_OPCODE v0 # extract opcode from rINST 2836 GOTO_OPCODE v0 # jump to next instruction 2837 2838/* ------------------------------ */ 2839 .balign 128 2840.L_op_sput_object: /* 0x69 */ 2841/* File: mips64/op_sput_object.S */ 2842 .extern MterpSputObject 2843 EXPORT_PC 2844 daddu a0, rFP, OFF_FP_SHADOWFRAME 2845 move a1, rPC 2846 move a2, rINST 2847 move a3, rSELF 2848 jal MterpSputObject 2849 beqzc v0, MterpException 2850 FETCH_ADVANCE_INST 2 # advance rPC, load rINST 2851 GET_INST_OPCODE v0 # extract opcode from rINST 2852 GOTO_OPCODE v0 # jump to next instruction 2853 2854/* ------------------------------ */ 2855 .balign 128 2856.L_op_sput_boolean: /* 0x6a */ 2857/* File: mips64/op_sput_boolean.S */ 2858/* File: mips64/op_sput.S */ 2859 /* 2860 * General SPUT handler wrapper. 2861 * 2862 * for: sput, sput-boolean, sput-byte, sput-char, sput-short 2863 */ 2864 /* op vAA, field//BBBB */ 2865 .extern MterpSetBooleanStatic 2866 EXPORT_PC 2867 lhu a0, 2(rPC) # a0 <- field ref BBBB 2868 srl a3, rINST, 8 # a3 <- AA 2869 GET_VREG a1, a3 # a1 <- fp[AA] 2870 ld a2, OFF_FP_METHOD(rFP) 2871 move a3, rSELF 2872 PREFETCH_INST 2 # Get next inst, but don't advance rPC 2873 jal MterpSetBooleanStatic 2874 bnezc v0, MterpException # 0 on success 2875 ADVANCE 2 # Past exception point - now advance rPC 2876 GET_INST_OPCODE v0 # extract opcode from rINST 2877 GOTO_OPCODE v0 # jump to next instruction 2878 2879 2880/* ------------------------------ */ 2881 .balign 128 2882.L_op_sput_byte: /* 0x6b */ 2883/* File: mips64/op_sput_byte.S */ 2884/* File: mips64/op_sput.S */ 2885 /* 2886 * General SPUT handler wrapper. 2887 * 2888 * for: sput, sput-boolean, sput-byte, sput-char, sput-short 2889 */ 2890 /* op vAA, field//BBBB */ 2891 .extern MterpSetByteStatic 2892 EXPORT_PC 2893 lhu a0, 2(rPC) # a0 <- field ref BBBB 2894 srl a3, rINST, 8 # a3 <- AA 2895 GET_VREG a1, a3 # a1 <- fp[AA] 2896 ld a2, OFF_FP_METHOD(rFP) 2897 move a3, rSELF 2898 PREFETCH_INST 2 # Get next inst, but don't advance rPC 2899 jal MterpSetByteStatic 2900 bnezc v0, MterpException # 0 on success 2901 ADVANCE 2 # Past exception point - now advance rPC 2902 GET_INST_OPCODE v0 # extract opcode from rINST 2903 GOTO_OPCODE v0 # jump to next instruction 2904 2905 2906/* ------------------------------ */ 2907 .balign 128 2908.L_op_sput_char: /* 0x6c */ 2909/* File: mips64/op_sput_char.S */ 2910/* File: mips64/op_sput.S */ 2911 /* 2912 * General SPUT handler wrapper. 2913 * 2914 * for: sput, sput-boolean, sput-byte, sput-char, sput-short 2915 */ 2916 /* op vAA, field//BBBB */ 2917 .extern MterpSetCharStatic 2918 EXPORT_PC 2919 lhu a0, 2(rPC) # a0 <- field ref BBBB 2920 srl a3, rINST, 8 # a3 <- AA 2921 GET_VREG a1, a3 # a1 <- fp[AA] 2922 ld a2, OFF_FP_METHOD(rFP) 2923 move a3, rSELF 2924 PREFETCH_INST 2 # Get next inst, but don't advance rPC 2925 jal MterpSetCharStatic 2926 bnezc v0, MterpException # 0 on success 2927 ADVANCE 2 # Past exception point - now advance rPC 2928 GET_INST_OPCODE v0 # extract opcode from rINST 2929 GOTO_OPCODE v0 # jump to next instruction 2930 2931 2932/* ------------------------------ */ 2933 .balign 128 2934.L_op_sput_short: /* 0x6d */ 2935/* File: mips64/op_sput_short.S */ 2936/* File: mips64/op_sput.S */ 2937 /* 2938 * General SPUT handler wrapper. 2939 * 2940 * for: sput, sput-boolean, sput-byte, sput-char, sput-short 2941 */ 2942 /* op vAA, field//BBBB */ 2943 .extern MterpSetShortStatic 2944 EXPORT_PC 2945 lhu a0, 2(rPC) # a0 <- field ref BBBB 2946 srl a3, rINST, 8 # a3 <- AA 2947 GET_VREG a1, a3 # a1 <- fp[AA] 2948 ld a2, OFF_FP_METHOD(rFP) 2949 move a3, rSELF 2950 PREFETCH_INST 2 # Get next inst, but don't advance rPC 2951 jal MterpSetShortStatic 2952 bnezc v0, MterpException # 0 on success 2953 ADVANCE 2 # Past exception point - now advance rPC 2954 GET_INST_OPCODE v0 # extract opcode from rINST 2955 GOTO_OPCODE v0 # jump to next instruction 2956 2957 2958/* ------------------------------ */ 2959 .balign 128 2960.L_op_invoke_virtual: /* 0x6e */ 2961/* File: mips64/op_invoke_virtual.S */ 2962/* File: mips64/invoke.S */ 2963 /* 2964 * Generic invoke handler wrapper. 2965 */ 2966 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 2967 /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 2968 .extern MterpInvokeVirtual 2969 .extern MterpShouldSwitchInterpreters 2970 EXPORT_PC 2971 move a0, rSELF 2972 daddu a1, rFP, OFF_FP_SHADOWFRAME 2973 move a2, rPC 2974 move a3, rINST 2975 jal MterpInvokeVirtual 2976 beqzc v0, MterpException 2977 FETCH_ADVANCE_INST 3 2978 jal MterpShouldSwitchInterpreters 2979 bnezc v0, MterpFallback 2980 GET_INST_OPCODE v0 2981 GOTO_OPCODE v0 2982 2983 /* 2984 * Handle a virtual method call. 2985 * 2986 * for: invoke-virtual, invoke-virtual/range 2987 */ 2988 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 2989 /* op vAA, {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 2990 2991/* ------------------------------ */ 2992 .balign 128 2993.L_op_invoke_super: /* 0x6f */ 2994/* File: mips64/op_invoke_super.S */ 2995/* File: mips64/invoke.S */ 2996 /* 2997 * Generic invoke handler wrapper. 2998 */ 2999 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 3000 /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 3001 .extern MterpInvokeSuper 3002 .extern MterpShouldSwitchInterpreters 3003 EXPORT_PC 3004 move a0, rSELF 3005 daddu a1, rFP, OFF_FP_SHADOWFRAME 3006 move a2, rPC 3007 move a3, rINST 3008 jal MterpInvokeSuper 3009 beqzc v0, MterpException 3010 FETCH_ADVANCE_INST 3 3011 jal MterpShouldSwitchInterpreters 3012 bnezc v0, MterpFallback 3013 GET_INST_OPCODE v0 3014 GOTO_OPCODE v0 3015 3016 /* 3017 * Handle a "super" method call. 3018 * 3019 * for: invoke-super, invoke-super/range 3020 */ 3021 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 3022 /* op vAA, {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 3023 3024/* ------------------------------ */ 3025 .balign 128 3026.L_op_invoke_direct: /* 0x70 */ 3027/* File: mips64/op_invoke_direct.S */ 3028/* File: mips64/invoke.S */ 3029 /* 3030 * Generic invoke handler wrapper. 3031 */ 3032 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 3033 /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 3034 .extern MterpInvokeDirect 3035 .extern MterpShouldSwitchInterpreters 3036 EXPORT_PC 3037 move a0, rSELF 3038 daddu a1, rFP, OFF_FP_SHADOWFRAME 3039 move a2, rPC 3040 move a3, rINST 3041 jal MterpInvokeDirect 3042 beqzc v0, MterpException 3043 FETCH_ADVANCE_INST 3 3044 jal MterpShouldSwitchInterpreters 3045 bnezc v0, MterpFallback 3046 GET_INST_OPCODE v0 3047 GOTO_OPCODE v0 3048 3049 3050/* ------------------------------ */ 3051 .balign 128 3052.L_op_invoke_static: /* 0x71 */ 3053/* File: mips64/op_invoke_static.S */ 3054/* File: mips64/invoke.S */ 3055 /* 3056 * Generic invoke handler wrapper. 3057 */ 3058 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 3059 /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 3060 .extern MterpInvokeStatic 3061 .extern MterpShouldSwitchInterpreters 3062 EXPORT_PC 3063 move a0, rSELF 3064 daddu a1, rFP, OFF_FP_SHADOWFRAME 3065 move a2, rPC 3066 move a3, rINST 3067 jal MterpInvokeStatic 3068 beqzc v0, MterpException 3069 FETCH_ADVANCE_INST 3 3070 jal MterpShouldSwitchInterpreters 3071 bnezc v0, MterpFallback 3072 GET_INST_OPCODE v0 3073 GOTO_OPCODE v0 3074 3075 3076/* ------------------------------ */ 3077 .balign 128 3078.L_op_invoke_interface: /* 0x72 */ 3079/* File: mips64/op_invoke_interface.S */ 3080/* File: mips64/invoke.S */ 3081 /* 3082 * Generic invoke handler wrapper. 3083 */ 3084 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 3085 /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 3086 .extern MterpInvokeInterface 3087 .extern MterpShouldSwitchInterpreters 3088 EXPORT_PC 3089 move a0, rSELF 3090 daddu a1, rFP, OFF_FP_SHADOWFRAME 3091 move a2, rPC 3092 move a3, rINST 3093 jal MterpInvokeInterface 3094 beqzc v0, MterpException 3095 FETCH_ADVANCE_INST 3 3096 jal MterpShouldSwitchInterpreters 3097 bnezc v0, MterpFallback 3098 GET_INST_OPCODE v0 3099 GOTO_OPCODE v0 3100 3101 /* 3102 * Handle an interface method call. 3103 * 3104 * for: invoke-interface, invoke-interface/range 3105 */ 3106 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 3107 /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 3108 3109/* ------------------------------ */ 3110 .balign 128 3111.L_op_return_void_no_barrier: /* 0x73 */ 3112/* File: mips64/op_return_void_no_barrier.S */ 3113 .extern MterpSuspendCheck 3114 lw ra, THREAD_FLAGS_OFFSET(rSELF) 3115 move a0, rSELF 3116 and ra, ra, THREAD_SUSPEND_OR_CHECKPOINT_REQUEST 3117 beqzc ra, 1f 3118 jal MterpSuspendCheck # (self) 31191: 3120 li a0, 0 3121 b MterpReturn 3122 3123/* ------------------------------ */ 3124 .balign 128 3125.L_op_invoke_virtual_range: /* 0x74 */ 3126/* File: mips64/op_invoke_virtual_range.S */ 3127/* File: mips64/invoke.S */ 3128 /* 3129 * Generic invoke handler wrapper. 3130 */ 3131 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 3132 /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 3133 .extern MterpInvokeVirtualRange 3134 .extern MterpShouldSwitchInterpreters 3135 EXPORT_PC 3136 move a0, rSELF 3137 daddu a1, rFP, OFF_FP_SHADOWFRAME 3138 move a2, rPC 3139 move a3, rINST 3140 jal MterpInvokeVirtualRange 3141 beqzc v0, MterpException 3142 FETCH_ADVANCE_INST 3 3143 jal MterpShouldSwitchInterpreters 3144 bnezc v0, MterpFallback 3145 GET_INST_OPCODE v0 3146 GOTO_OPCODE v0 3147 3148 3149/* ------------------------------ */ 3150 .balign 128 3151.L_op_invoke_super_range: /* 0x75 */ 3152/* File: mips64/op_invoke_super_range.S */ 3153/* File: mips64/invoke.S */ 3154 /* 3155 * Generic invoke handler wrapper. 3156 */ 3157 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 3158 /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 3159 .extern MterpInvokeSuperRange 3160 .extern MterpShouldSwitchInterpreters 3161 EXPORT_PC 3162 move a0, rSELF 3163 daddu a1, rFP, OFF_FP_SHADOWFRAME 3164 move a2, rPC 3165 move a3, rINST 3166 jal MterpInvokeSuperRange 3167 beqzc v0, MterpException 3168 FETCH_ADVANCE_INST 3 3169 jal MterpShouldSwitchInterpreters 3170 bnezc v0, MterpFallback 3171 GET_INST_OPCODE v0 3172 GOTO_OPCODE v0 3173 3174 3175/* ------------------------------ */ 3176 .balign 128 3177.L_op_invoke_direct_range: /* 0x76 */ 3178/* File: mips64/op_invoke_direct_range.S */ 3179/* File: mips64/invoke.S */ 3180 /* 3181 * Generic invoke handler wrapper. 3182 */ 3183 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 3184 /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 3185 .extern MterpInvokeDirectRange 3186 .extern MterpShouldSwitchInterpreters 3187 EXPORT_PC 3188 move a0, rSELF 3189 daddu a1, rFP, OFF_FP_SHADOWFRAME 3190 move a2, rPC 3191 move a3, rINST 3192 jal MterpInvokeDirectRange 3193 beqzc v0, MterpException 3194 FETCH_ADVANCE_INST 3 3195 jal MterpShouldSwitchInterpreters 3196 bnezc v0, MterpFallback 3197 GET_INST_OPCODE v0 3198 GOTO_OPCODE v0 3199 3200 3201/* ------------------------------ */ 3202 .balign 128 3203.L_op_invoke_static_range: /* 0x77 */ 3204/* File: mips64/op_invoke_static_range.S */ 3205/* File: mips64/invoke.S */ 3206 /* 3207 * Generic invoke handler wrapper. 3208 */ 3209 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 3210 /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 3211 .extern MterpInvokeStaticRange 3212 .extern MterpShouldSwitchInterpreters 3213 EXPORT_PC 3214 move a0, rSELF 3215 daddu a1, rFP, OFF_FP_SHADOWFRAME 3216 move a2, rPC 3217 move a3, rINST 3218 jal MterpInvokeStaticRange 3219 beqzc v0, MterpException 3220 FETCH_ADVANCE_INST 3 3221 jal MterpShouldSwitchInterpreters 3222 bnezc v0, MterpFallback 3223 GET_INST_OPCODE v0 3224 GOTO_OPCODE v0 3225 3226 3227/* ------------------------------ */ 3228 .balign 128 3229.L_op_invoke_interface_range: /* 0x78 */ 3230/* File: mips64/op_invoke_interface_range.S */ 3231/* File: mips64/invoke.S */ 3232 /* 3233 * Generic invoke handler wrapper. 3234 */ 3235 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 3236 /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 3237 .extern MterpInvokeInterfaceRange 3238 .extern MterpShouldSwitchInterpreters 3239 EXPORT_PC 3240 move a0, rSELF 3241 daddu a1, rFP, OFF_FP_SHADOWFRAME 3242 move a2, rPC 3243 move a3, rINST 3244 jal MterpInvokeInterfaceRange 3245 beqzc v0, MterpException 3246 FETCH_ADVANCE_INST 3 3247 jal MterpShouldSwitchInterpreters 3248 bnezc v0, MterpFallback 3249 GET_INST_OPCODE v0 3250 GOTO_OPCODE v0 3251 3252 3253/* ------------------------------ */ 3254 .balign 128 3255.L_op_unused_79: /* 0x79 */ 3256/* File: mips64/op_unused_79.S */ 3257/* File: mips64/unused.S */ 3258/* 3259 * Bail to reference interpreter to throw. 3260 */ 3261 b MterpFallback 3262 3263 3264/* ------------------------------ */ 3265 .balign 128 3266.L_op_unused_7a: /* 0x7a */ 3267/* File: mips64/op_unused_7a.S */ 3268/* File: mips64/unused.S */ 3269/* 3270 * Bail to reference interpreter to throw. 3271 */ 3272 b MterpFallback 3273 3274 3275/* ------------------------------ */ 3276 .balign 128 3277.L_op_neg_int: /* 0x7b */ 3278/* File: mips64/op_neg_int.S */ 3279/* File: mips64/unop.S */ 3280 /* 3281 * Generic 32-bit unary operation. Provide an "instr" line that 3282 * specifies an instruction that performs "a0 = op a0". 3283 * 3284 * for: int-to-byte, int-to-char, int-to-short, 3285 * not-int, neg-int 3286 */ 3287 /* unop vA, vB */ 3288 ext a3, rINST, 12, 4 # a3 <- B 3289 GET_VREG a0, a3 # a0 <- vB 3290 ext a2, rINST, 8, 4 # a2 <- A 3291 # optional op 3292 FETCH_ADVANCE_INST 1 # advance rPC, load rINST 3293 subu a0, zero, a0 # a0 <- op, a0-a3 changed 3294 GET_INST_OPCODE v0 # extract opcode from rINST 3295 SET_VREG a0, a2 # vA <- a0 3296 GOTO_OPCODE v0 # jump to next instruction 3297 3298 3299/* ------------------------------ */ 3300 .balign 128 3301.L_op_not_int: /* 0x7c */ 3302/* File: mips64/op_not_int.S */ 3303/* File: mips64/unop.S */ 3304 /* 3305 * Generic 32-bit unary operation. Provide an "instr" line that 3306 * specifies an instruction that performs "a0 = op a0". 3307 * 3308 * for: int-to-byte, int-to-char, int-to-short, 3309 * not-int, neg-int 3310 */ 3311 /* unop vA, vB */ 3312 ext a3, rINST, 12, 4 # a3 <- B 3313 GET_VREG a0, a3 # a0 <- vB 3314 ext a2, rINST, 8, 4 # a2 <- A 3315 # optional op 3316 FETCH_ADVANCE_INST 1 # advance rPC, load rINST 3317 nor a0, zero, a0 # a0 <- op, a0-a3 changed 3318 GET_INST_OPCODE v0 # extract opcode from rINST 3319 SET_VREG a0, a2 # vA <- a0 3320 GOTO_OPCODE v0 # jump to next instruction 3321 3322 3323/* ------------------------------ */ 3324 .balign 128 3325.L_op_neg_long: /* 0x7d */ 3326/* File: mips64/op_neg_long.S */ 3327/* File: mips64/unopWide.S */ 3328 /* 3329 * Generic 64-bit unary operation. Provide an "instr" line that 3330 * specifies an instruction that performs "a0 = op a0". 3331 * 3332 * For: not-long, neg-long 3333 */ 3334 /* unop vA, vB */ 3335 ext a3, rINST, 12, 4 # a3 <- B 3336 GET_VREG_WIDE a0, a3 # a0 <- vB 3337 ext a2, rINST, 8, 4 # a2 <- A 3338 # optional op 3339 FETCH_ADVANCE_INST 1 # advance rPC, load rINST 3340 dsubu a0, zero, a0 # a0 <- op, a0-a3 changed 3341 GET_INST_OPCODE v0 # extract opcode from rINST 3342 SET_VREG_WIDE a0, a2 # vA <- a0 3343 GOTO_OPCODE v0 # jump to next instruction 3344 3345 3346/* ------------------------------ */ 3347 .balign 128 3348.L_op_not_long: /* 0x7e */ 3349/* File: mips64/op_not_long.S */ 3350/* File: mips64/unopWide.S */ 3351 /* 3352 * Generic 64-bit unary operation. Provide an "instr" line that 3353 * specifies an instruction that performs "a0 = op a0". 3354 * 3355 * For: not-long, neg-long 3356 */ 3357 /* unop vA, vB */ 3358 ext a3, rINST, 12, 4 # a3 <- B 3359 GET_VREG_WIDE a0, a3 # a0 <- vB 3360 ext a2, rINST, 8, 4 # a2 <- A 3361 # optional op 3362 FETCH_ADVANCE_INST 1 # advance rPC, load rINST 3363 nor a0, zero, a0 # a0 <- op, a0-a3 changed 3364 GET_INST_OPCODE v0 # extract opcode from rINST 3365 SET_VREG_WIDE a0, a2 # vA <- a0 3366 GOTO_OPCODE v0 # jump to next instruction 3367 3368 3369/* ------------------------------ */ 3370 .balign 128 3371.L_op_neg_float: /* 0x7f */ 3372/* File: mips64/op_neg_float.S */ 3373/* File: mips64/fcvtHeader.S */ 3374 /* 3375 * Loads a specified register from vB. Used primarily for conversions 3376 * from or to a floating-point type. 3377 * 3378 * Sets up a1 = A and a2 = B. a2 is later used by fcvtFooter.S to 3379 * store the result in vA and jump to the next instruction. 3380 * 3381 * For: int-to-float, int-to-double, long-to-float, long-to-double, 3382 * float-to-int, float-to-long, float-to-double, double-to-int, 3383 * double-to-long, double-to-float, neg-float, neg-double. 3384 */ 3385 ext a1, rINST, 8, 4 # a1 <- A 3386 srl a2, rINST, 12 # a2 <- B 3387 GET_VREG_FLOAT f0, a2 3388 FETCH_ADVANCE_INST 1 # advance rPC, load rINST 3389 3390 neg.s f0, f0 3391/* File: mips64/fcvtFooter.S */ 3392 /* 3393 * Stores a specified register containing the result of conversion 3394 * from or to a floating-point type and jumps to the next instruction. 3395 * 3396 * Expects a1 to contain the destination Dalvik register number. 3397 * a1 is set up by fcvtHeader.S. 3398 * 3399 * For: int-to-float, int-to-double, long-to-float, long-to-double, 3400 * float-to-int, float-to-long, float-to-double, double-to-int, 3401 * double-to-long, double-to-float, neg-float, neg-double. 3402 * 3403 * Note that this file can't be included after a break in other files 3404 * and in those files its contents appear as a copy. 3405 * See: float-to-int, float-to-long, double-to-int, double-to-long. 3406 */ 3407 GET_INST_OPCODE v0 # extract opcode from rINST 3408 SET_VREG_FLOAT f0, a1 3409 GOTO_OPCODE v0 # jump to next instruction 3410 3411 3412/* ------------------------------ */ 3413 .balign 128 3414.L_op_neg_double: /* 0x80 */ 3415/* File: mips64/op_neg_double.S */ 3416/* File: mips64/fcvtHeader.S */ 3417 /* 3418 * Loads a specified register from vB. Used primarily for conversions 3419 * from or to a floating-point type. 3420 * 3421 * Sets up a1 = A and a2 = B. a2 is later used by fcvtFooter.S to 3422 * store the result in vA and jump to the next instruction. 3423 * 3424 * For: int-to-float, int-to-double, long-to-float, long-to-double, 3425 * float-to-int, float-to-long, float-to-double, double-to-int, 3426 * double-to-long, double-to-float, neg-float, neg-double. 3427 */ 3428 ext a1, rINST, 8, 4 # a1 <- A 3429 srl a2, rINST, 12 # a2 <- B 3430 GET_VREG_DOUBLE f0, a2 3431 FETCH_ADVANCE_INST 1 # advance rPC, load rINST 3432 3433 neg.d f0, f0 3434/* File: mips64/fcvtFooter.S */ 3435 /* 3436 * Stores a specified register containing the result of conversion 3437 * from or to a floating-point type and jumps to the next instruction. 3438 * 3439 * Expects a1 to contain the destination Dalvik register number. 3440 * a1 is set up by fcvtHeader.S. 3441 * 3442 * For: int-to-float, int-to-double, long-to-float, long-to-double, 3443 * float-to-int, float-to-long, float-to-double, double-to-int, 3444 * double-to-long, double-to-float, neg-float, neg-double. 3445 * 3446 * Note that this file can't be included after a break in other files 3447 * and in those files its contents appear as a copy. 3448 * See: float-to-int, float-to-long, double-to-int, double-to-long. 3449 */ 3450 GET_INST_OPCODE v0 # extract opcode from rINST 3451 SET_VREG_DOUBLE f0, a1 3452 GOTO_OPCODE v0 # jump to next instruction 3453 3454 3455/* ------------------------------ */ 3456 .balign 128 3457.L_op_int_to_long: /* 0x81 */ 3458/* File: mips64/op_int_to_long.S */ 3459 /* int-to-long vA, vB */ 3460 ext a3, rINST, 12, 4 # a3 <- B 3461 GET_VREG a0, a3 # a0 <- vB (sign-extended to 64 bits) 3462 ext a2, rINST, 8, 4 # a2 <- A 3463 FETCH_ADVANCE_INST 1 # advance rPC, load rINST 3464 GET_INST_OPCODE v0 # extract opcode from rINST 3465 SET_VREG_WIDE a0, a2 # vA <- vB 3466 GOTO_OPCODE v0 # jump to next instruction 3467 3468/* ------------------------------ */ 3469 .balign 128 3470.L_op_int_to_float: /* 0x82 */ 3471/* File: mips64/op_int_to_float.S */ 3472 /* 3473 * Conversion from or to floating-point happens in a floating-point register. 3474 * Therefore we load the input and store the output into or from a 3475 * floating-point register irrespective of the type. 3476 */ 3477/* File: mips64/fcvtHeader.S */ 3478 /* 3479 * Loads a specified register from vB. Used primarily for conversions 3480 * from or to a floating-point type. 3481 * 3482 * Sets up a1 = A and a2 = B. a2 is later used by fcvtFooter.S to 3483 * store the result in vA and jump to the next instruction. 3484 * 3485 * For: int-to-float, int-to-double, long-to-float, long-to-double, 3486 * float-to-int, float-to-long, float-to-double, double-to-int, 3487 * double-to-long, double-to-float, neg-float, neg-double. 3488 */ 3489 ext a1, rINST, 8, 4 # a1 <- A 3490 srl a2, rINST, 12 # a2 <- B 3491 GET_VREG_FLOAT f0, a2 3492 FETCH_ADVANCE_INST 1 # advance rPC, load rINST 3493 3494 cvt.s.w f0, f0 3495/* File: mips64/fcvtFooter.S */ 3496 /* 3497 * Stores a specified register containing the result of conversion 3498 * from or to a floating-point type and jumps to the next instruction. 3499 * 3500 * Expects a1 to contain the destination Dalvik register number. 3501 * a1 is set up by fcvtHeader.S. 3502 * 3503 * For: int-to-float, int-to-double, long-to-float, long-to-double, 3504 * float-to-int, float-to-long, float-to-double, double-to-int, 3505 * double-to-long, double-to-float, neg-float, neg-double. 3506 * 3507 * Note that this file can't be included after a break in other files 3508 * and in those files its contents appear as a copy. 3509 * See: float-to-int, float-to-long, double-to-int, double-to-long. 3510 */ 3511 GET_INST_OPCODE v0 # extract opcode from rINST 3512 SET_VREG_FLOAT f0, a1 3513 GOTO_OPCODE v0 # jump to next instruction 3514 3515 3516/* ------------------------------ */ 3517 .balign 128 3518.L_op_int_to_double: /* 0x83 */ 3519/* File: mips64/op_int_to_double.S */ 3520 /* 3521 * Conversion from or to floating-point happens in a floating-point register. 3522 * Therefore we load the input and store the output into or from a 3523 * floating-point register irrespective of the type. 3524 */ 3525/* File: mips64/fcvtHeader.S */ 3526 /* 3527 * Loads a specified register from vB. Used primarily for conversions 3528 * from or to a floating-point type. 3529 * 3530 * Sets up a1 = A and a2 = B. a2 is later used by fcvtFooter.S to 3531 * store the result in vA and jump to the next instruction. 3532 * 3533 * For: int-to-float, int-to-double, long-to-float, long-to-double, 3534 * float-to-int, float-to-long, float-to-double, double-to-int, 3535 * double-to-long, double-to-float, neg-float, neg-double. 3536 */ 3537 ext a1, rINST, 8, 4 # a1 <- A 3538 srl a2, rINST, 12 # a2 <- B 3539 GET_VREG_FLOAT f0, a2 3540 FETCH_ADVANCE_INST 1 # advance rPC, load rINST 3541 3542 cvt.d.w f0, f0 3543/* File: mips64/fcvtFooter.S */ 3544 /* 3545 * Stores a specified register containing the result of conversion 3546 * from or to a floating-point type and jumps to the next instruction. 3547 * 3548 * Expects a1 to contain the destination Dalvik register number. 3549 * a1 is set up by fcvtHeader.S. 3550 * 3551 * For: int-to-float, int-to-double, long-to-float, long-to-double, 3552 * float-to-int, float-to-long, float-to-double, double-to-int, 3553 * double-to-long, double-to-float, neg-float, neg-double. 3554 * 3555 * Note that this file can't be included after a break in other files 3556 * and in those files its contents appear as a copy. 3557 * See: float-to-int, float-to-long, double-to-int, double-to-long. 3558 */ 3559 GET_INST_OPCODE v0 # extract opcode from rINST 3560 SET_VREG_DOUBLE f0, a1 3561 GOTO_OPCODE v0 # jump to next instruction 3562 3563 3564/* ------------------------------ */ 3565 .balign 128 3566.L_op_long_to_int: /* 0x84 */ 3567/* File: mips64/op_long_to_int.S */ 3568/* we ignore the high word, making this equivalent to a 32-bit reg move */ 3569/* File: mips64/op_move.S */ 3570 /* for move, move-object, long-to-int */ 3571 /* op vA, vB */ 3572 ext a2, rINST, 8, 4 # a2 <- A 3573 ext a3, rINST, 12, 4 # a3 <- B 3574 FETCH_ADVANCE_INST 1 # advance rPC, load rINST 3575 GET_VREG a0, a3 # a0 <- vB 3576 GET_INST_OPCODE v0 # extract opcode from rINST 3577 .if 0 3578 SET_VREG_OBJECT a0, a2 # vA <- vB 3579 .else 3580 SET_VREG a0, a2 # vA <- vB 3581 .endif 3582 GOTO_OPCODE v0 # jump to next instruction 3583 3584 3585/* ------------------------------ */ 3586 .balign 128 3587.L_op_long_to_float: /* 0x85 */ 3588/* File: mips64/op_long_to_float.S */ 3589 /* 3590 * Conversion from or to floating-point happens in a floating-point register. 3591 * Therefore we load the input and store the output into or from a 3592 * floating-point register irrespective of the type. 3593 */ 3594/* File: mips64/fcvtHeader.S */ 3595 /* 3596 * Loads a specified register from vB. Used primarily for conversions 3597 * from or to a floating-point type. 3598 * 3599 * Sets up a1 = A and a2 = B. a2 is later used by fcvtFooter.S to 3600 * store the result in vA and jump to the next instruction. 3601 * 3602 * For: int-to-float, int-to-double, long-to-float, long-to-double, 3603 * float-to-int, float-to-long, float-to-double, double-to-int, 3604 * double-to-long, double-to-float, neg-float, neg-double. 3605 */ 3606 ext a1, rINST, 8, 4 # a1 <- A 3607 srl a2, rINST, 12 # a2 <- B 3608 GET_VREG_DOUBLE f0, a2 3609 FETCH_ADVANCE_INST 1 # advance rPC, load rINST 3610 3611 cvt.s.l f0, f0 3612/* File: mips64/fcvtFooter.S */ 3613 /* 3614 * Stores a specified register containing the result of conversion 3615 * from or to a floating-point type and jumps to the next instruction. 3616 * 3617 * Expects a1 to contain the destination Dalvik register number. 3618 * a1 is set up by fcvtHeader.S. 3619 * 3620 * For: int-to-float, int-to-double, long-to-float, long-to-double, 3621 * float-to-int, float-to-long, float-to-double, double-to-int, 3622 * double-to-long, double-to-float, neg-float, neg-double. 3623 * 3624 * Note that this file can't be included after a break in other files 3625 * and in those files its contents appear as a copy. 3626 * See: float-to-int, float-to-long, double-to-int, double-to-long. 3627 */ 3628 GET_INST_OPCODE v0 # extract opcode from rINST 3629 SET_VREG_FLOAT f0, a1 3630 GOTO_OPCODE v0 # jump to next instruction 3631 3632 3633/* ------------------------------ */ 3634 .balign 128 3635.L_op_long_to_double: /* 0x86 */ 3636/* File: mips64/op_long_to_double.S */ 3637 /* 3638 * Conversion from or to floating-point happens in a floating-point register. 3639 * Therefore we load the input and store the output into or from a 3640 * floating-point register irrespective of the type. 3641 */ 3642/* File: mips64/fcvtHeader.S */ 3643 /* 3644 * Loads a specified register from vB. Used primarily for conversions 3645 * from or to a floating-point type. 3646 * 3647 * Sets up a1 = A and a2 = B. a2 is later used by fcvtFooter.S to 3648 * store the result in vA and jump to the next instruction. 3649 * 3650 * For: int-to-float, int-to-double, long-to-float, long-to-double, 3651 * float-to-int, float-to-long, float-to-double, double-to-int, 3652 * double-to-long, double-to-float, neg-float, neg-double. 3653 */ 3654 ext a1, rINST, 8, 4 # a1 <- A 3655 srl a2, rINST, 12 # a2 <- B 3656 GET_VREG_DOUBLE f0, a2 3657 FETCH_ADVANCE_INST 1 # advance rPC, load rINST 3658 3659 cvt.d.l f0, f0 3660/* File: mips64/fcvtFooter.S */ 3661 /* 3662 * Stores a specified register containing the result of conversion 3663 * from or to a floating-point type and jumps to the next instruction. 3664 * 3665 * Expects a1 to contain the destination Dalvik register number. 3666 * a1 is set up by fcvtHeader.S. 3667 * 3668 * For: int-to-float, int-to-double, long-to-float, long-to-double, 3669 * float-to-int, float-to-long, float-to-double, double-to-int, 3670 * double-to-long, double-to-float, neg-float, neg-double. 3671 * 3672 * Note that this file can't be included after a break in other files 3673 * and in those files its contents appear as a copy. 3674 * See: float-to-int, float-to-long, double-to-int, double-to-long. 3675 */ 3676 GET_INST_OPCODE v0 # extract opcode from rINST 3677 SET_VREG_DOUBLE f0, a1 3678 GOTO_OPCODE v0 # jump to next instruction 3679 3680 3681/* ------------------------------ */ 3682 .balign 128 3683.L_op_float_to_int: /* 0x87 */ 3684/* File: mips64/op_float_to_int.S */ 3685/* File: mips64/fcvtHeader.S */ 3686 /* 3687 * Loads a specified register from vB. Used primarily for conversions 3688 * from or to a floating-point type. 3689 * 3690 * Sets up a1 = A and a2 = B. a2 is later used by fcvtFooter.S to 3691 * store the result in vA and jump to the next instruction. 3692 * 3693 * For: int-to-float, int-to-double, long-to-float, long-to-double, 3694 * float-to-int, float-to-long, float-to-double, double-to-int, 3695 * double-to-long, double-to-float, neg-float, neg-double. 3696 */ 3697 ext a1, rINST, 8, 4 # a1 <- A 3698 srl a2, rINST, 12 # a2 <- B 3699 GET_VREG_FLOAT f0, a2 3700 FETCH_ADVANCE_INST 1 # advance rPC, load rINST 3701 3702 trunc.w.s f0, f0 3703/* File: mips64/fcvtFooter.S */ 3704 /* 3705 * Stores a specified register containing the result of conversion 3706 * from or to a floating-point type and jumps to the next instruction. 3707 * 3708 * Expects a1 to contain the destination Dalvik register number. 3709 * a1 is set up by fcvtHeader.S. 3710 * 3711 * For: int-to-float, int-to-double, long-to-float, long-to-double, 3712 * float-to-int, float-to-long, float-to-double, double-to-int, 3713 * double-to-long, double-to-float, neg-float, neg-double. 3714 * 3715 * Note that this file can't be included after a break in other files 3716 * and in those files its contents appear as a copy. 3717 * See: float-to-int, float-to-long, double-to-int, double-to-long. 3718 */ 3719 GET_INST_OPCODE v0 # extract opcode from rINST 3720 SET_VREG_FLOAT f0, a1 3721 GOTO_OPCODE v0 # jump to next instruction 3722 3723 3724/* ------------------------------ */ 3725 .balign 128 3726.L_op_float_to_long: /* 0x88 */ 3727/* File: mips64/op_float_to_long.S */ 3728/* File: mips64/fcvtHeader.S */ 3729 /* 3730 * Loads a specified register from vB. Used primarily for conversions 3731 * from or to a floating-point type. 3732 * 3733 * Sets up a1 = A and a2 = B. a2 is later used by fcvtFooter.S to 3734 * store the result in vA and jump to the next instruction. 3735 * 3736 * For: int-to-float, int-to-double, long-to-float, long-to-double, 3737 * float-to-int, float-to-long, float-to-double, double-to-int, 3738 * double-to-long, double-to-float, neg-float, neg-double. 3739 */ 3740 ext a1, rINST, 8, 4 # a1 <- A 3741 srl a2, rINST, 12 # a2 <- B 3742 GET_VREG_FLOAT f0, a2 3743 FETCH_ADVANCE_INST 1 # advance rPC, load rINST 3744 3745 trunc.l.s f0, f0 3746/* File: mips64/fcvtFooter.S */ 3747 /* 3748 * Stores a specified register containing the result of conversion 3749 * from or to a floating-point type and jumps to the next instruction. 3750 * 3751 * Expects a1 to contain the destination Dalvik register number. 3752 * a1 is set up by fcvtHeader.S. 3753 * 3754 * For: int-to-float, int-to-double, long-to-float, long-to-double, 3755 * float-to-int, float-to-long, float-to-double, double-to-int, 3756 * double-to-long, double-to-float, neg-float, neg-double. 3757 * 3758 * Note that this file can't be included after a break in other files 3759 * and in those files its contents appear as a copy. 3760 * See: float-to-int, float-to-long, double-to-int, double-to-long. 3761 */ 3762 GET_INST_OPCODE v0 # extract opcode from rINST 3763 SET_VREG_DOUBLE f0, a1 3764 GOTO_OPCODE v0 # jump to next instruction 3765 3766 3767 3768/* ------------------------------ */ 3769 .balign 128 3770.L_op_float_to_double: /* 0x89 */ 3771/* File: mips64/op_float_to_double.S */ 3772 /* 3773 * Conversion from or to floating-point happens in a floating-point register. 3774 * Therefore we load the input and store the output into or from a 3775 * floating-point register irrespective of the type. 3776 */ 3777/* File: mips64/fcvtHeader.S */ 3778 /* 3779 * Loads a specified register from vB. Used primarily for conversions 3780 * from or to a floating-point type. 3781 * 3782 * Sets up a1 = A and a2 = B. a2 is later used by fcvtFooter.S to 3783 * store the result in vA and jump to the next instruction. 3784 * 3785 * For: int-to-float, int-to-double, long-to-float, long-to-double, 3786 * float-to-int, float-to-long, float-to-double, double-to-int, 3787 * double-to-long, double-to-float, neg-float, neg-double. 3788 */ 3789 ext a1, rINST, 8, 4 # a1 <- A 3790 srl a2, rINST, 12 # a2 <- B 3791 GET_VREG_FLOAT f0, a2 3792 FETCH_ADVANCE_INST 1 # advance rPC, load rINST 3793 3794 cvt.d.s f0, f0 3795/* File: mips64/fcvtFooter.S */ 3796 /* 3797 * Stores a specified register containing the result of conversion 3798 * from or to a floating-point type and jumps to the next instruction. 3799 * 3800 * Expects a1 to contain the destination Dalvik register number. 3801 * a1 is set up by fcvtHeader.S. 3802 * 3803 * For: int-to-float, int-to-double, long-to-float, long-to-double, 3804 * float-to-int, float-to-long, float-to-double, double-to-int, 3805 * double-to-long, double-to-float, neg-float, neg-double. 3806 * 3807 * Note that this file can't be included after a break in other files 3808 * and in those files its contents appear as a copy. 3809 * See: float-to-int, float-to-long, double-to-int, double-to-long. 3810 */ 3811 GET_INST_OPCODE v0 # extract opcode from rINST 3812 SET_VREG_DOUBLE f0, a1 3813 GOTO_OPCODE v0 # jump to next instruction 3814 3815 3816/* ------------------------------ */ 3817 .balign 128 3818.L_op_double_to_int: /* 0x8a */ 3819/* File: mips64/op_double_to_int.S */ 3820/* File: mips64/fcvtHeader.S */ 3821 /* 3822 * Loads a specified register from vB. Used primarily for conversions 3823 * from or to a floating-point type. 3824 * 3825 * Sets up a1 = A and a2 = B. a2 is later used by fcvtFooter.S to 3826 * store the result in vA and jump to the next instruction. 3827 * 3828 * For: int-to-float, int-to-double, long-to-float, long-to-double, 3829 * float-to-int, float-to-long, float-to-double, double-to-int, 3830 * double-to-long, double-to-float, neg-float, neg-double. 3831 */ 3832 ext a1, rINST, 8, 4 # a1 <- A 3833 srl a2, rINST, 12 # a2 <- B 3834 GET_VREG_DOUBLE f0, a2 3835 FETCH_ADVANCE_INST 1 # advance rPC, load rINST 3836 3837 trunc.w.d f0, f0 3838/* File: mips64/fcvtFooter.S */ 3839 /* 3840 * Stores a specified register containing the result of conversion 3841 * from or to a floating-point type and jumps to the next instruction. 3842 * 3843 * Expects a1 to contain the destination Dalvik register number. 3844 * a1 is set up by fcvtHeader.S. 3845 * 3846 * For: int-to-float, int-to-double, long-to-float, long-to-double, 3847 * float-to-int, float-to-long, float-to-double, double-to-int, 3848 * double-to-long, double-to-float, neg-float, neg-double. 3849 * 3850 * Note that this file can't be included after a break in other files 3851 * and in those files its contents appear as a copy. 3852 * See: float-to-int, float-to-long, double-to-int, double-to-long. 3853 */ 3854 GET_INST_OPCODE v0 # extract opcode from rINST 3855 SET_VREG_FLOAT f0, a1 3856 GOTO_OPCODE v0 # jump to next instruction 3857 3858 3859/* ------------------------------ */ 3860 .balign 128 3861.L_op_double_to_long: /* 0x8b */ 3862/* File: mips64/op_double_to_long.S */ 3863/* File: mips64/fcvtHeader.S */ 3864 /* 3865 * Loads a specified register from vB. Used primarily for conversions 3866 * from or to a floating-point type. 3867 * 3868 * Sets up a1 = A and a2 = B. a2 is later used by fcvtFooter.S to 3869 * store the result in vA and jump to the next instruction. 3870 * 3871 * For: int-to-float, int-to-double, long-to-float, long-to-double, 3872 * float-to-int, float-to-long, float-to-double, double-to-int, 3873 * double-to-long, double-to-float, neg-float, neg-double. 3874 */ 3875 ext a1, rINST, 8, 4 # a1 <- A 3876 srl a2, rINST, 12 # a2 <- B 3877 GET_VREG_DOUBLE f0, a2 3878 FETCH_ADVANCE_INST 1 # advance rPC, load rINST 3879 3880 trunc.l.d f0, f0 3881/* File: mips64/fcvtFooter.S */ 3882 /* 3883 * Stores a specified register containing the result of conversion 3884 * from or to a floating-point type and jumps to the next instruction. 3885 * 3886 * Expects a1 to contain the destination Dalvik register number. 3887 * a1 is set up by fcvtHeader.S. 3888 * 3889 * For: int-to-float, int-to-double, long-to-float, long-to-double, 3890 * float-to-int, float-to-long, float-to-double, double-to-int, 3891 * double-to-long, double-to-float, neg-float, neg-double. 3892 * 3893 * Note that this file can't be included after a break in other files 3894 * and in those files its contents appear as a copy. 3895 * See: float-to-int, float-to-long, double-to-int, double-to-long. 3896 */ 3897 GET_INST_OPCODE v0 # extract opcode from rINST 3898 SET_VREG_DOUBLE f0, a1 3899 GOTO_OPCODE v0 # jump to next instruction 3900 3901 3902/* ------------------------------ */ 3903 .balign 128 3904.L_op_double_to_float: /* 0x8c */ 3905/* File: mips64/op_double_to_float.S */ 3906 /* 3907 * Conversion from or to floating-point happens in a floating-point register. 3908 * Therefore we load the input and store the output into or from a 3909 * floating-point register irrespective of the type. 3910 */ 3911/* File: mips64/fcvtHeader.S */ 3912 /* 3913 * Loads a specified register from vB. Used primarily for conversions 3914 * from or to a floating-point type. 3915 * 3916 * Sets up a1 = A and a2 = B. a2 is later used by fcvtFooter.S to 3917 * store the result in vA and jump to the next instruction. 3918 * 3919 * For: int-to-float, int-to-double, long-to-float, long-to-double, 3920 * float-to-int, float-to-long, float-to-double, double-to-int, 3921 * double-to-long, double-to-float, neg-float, neg-double. 3922 */ 3923 ext a1, rINST, 8, 4 # a1 <- A 3924 srl a2, rINST, 12 # a2 <- B 3925 GET_VREG_DOUBLE f0, a2 3926 FETCH_ADVANCE_INST 1 # advance rPC, load rINST 3927 3928 cvt.s.d f0, f0 3929/* File: mips64/fcvtFooter.S */ 3930 /* 3931 * Stores a specified register containing the result of conversion 3932 * from or to a floating-point type and jumps to the next instruction. 3933 * 3934 * Expects a1 to contain the destination Dalvik register number. 3935 * a1 is set up by fcvtHeader.S. 3936 * 3937 * For: int-to-float, int-to-double, long-to-float, long-to-double, 3938 * float-to-int, float-to-long, float-to-double, double-to-int, 3939 * double-to-long, double-to-float, neg-float, neg-double. 3940 * 3941 * Note that this file can't be included after a break in other files 3942 * and in those files its contents appear as a copy. 3943 * See: float-to-int, float-to-long, double-to-int, double-to-long. 3944 */ 3945 GET_INST_OPCODE v0 # extract opcode from rINST 3946 SET_VREG_FLOAT f0, a1 3947 GOTO_OPCODE v0 # jump to next instruction 3948 3949 3950/* ------------------------------ */ 3951 .balign 128 3952.L_op_int_to_byte: /* 0x8d */ 3953/* File: mips64/op_int_to_byte.S */ 3954/* File: mips64/unop.S */ 3955 /* 3956 * Generic 32-bit unary operation. Provide an "instr" line that 3957 * specifies an instruction that performs "a0 = op a0". 3958 * 3959 * for: int-to-byte, int-to-char, int-to-short, 3960 * not-int, neg-int 3961 */ 3962 /* unop vA, vB */ 3963 ext a3, rINST, 12, 4 # a3 <- B 3964 GET_VREG a0, a3 # a0 <- vB 3965 ext a2, rINST, 8, 4 # a2 <- A 3966 # optional op 3967 FETCH_ADVANCE_INST 1 # advance rPC, load rINST 3968 seb a0, a0 # a0 <- op, a0-a3 changed 3969 GET_INST_OPCODE v0 # extract opcode from rINST 3970 SET_VREG a0, a2 # vA <- a0 3971 GOTO_OPCODE v0 # jump to next instruction 3972 3973 3974/* ------------------------------ */ 3975 .balign 128 3976.L_op_int_to_char: /* 0x8e */ 3977/* File: mips64/op_int_to_char.S */ 3978/* File: mips64/unop.S */ 3979 /* 3980 * Generic 32-bit unary operation. Provide an "instr" line that 3981 * specifies an instruction that performs "a0 = op a0". 3982 * 3983 * for: int-to-byte, int-to-char, int-to-short, 3984 * not-int, neg-int 3985 */ 3986 /* unop vA, vB */ 3987 ext a3, rINST, 12, 4 # a3 <- B 3988 GET_VREG a0, a3 # a0 <- vB 3989 ext a2, rINST, 8, 4 # a2 <- A 3990 # optional op 3991 FETCH_ADVANCE_INST 1 # advance rPC, load rINST 3992 and a0, a0, 0xffff # a0 <- op, a0-a3 changed 3993 GET_INST_OPCODE v0 # extract opcode from rINST 3994 SET_VREG a0, a2 # vA <- a0 3995 GOTO_OPCODE v0 # jump to next instruction 3996 3997 3998/* ------------------------------ */ 3999 .balign 128 4000.L_op_int_to_short: /* 0x8f */ 4001/* File: mips64/op_int_to_short.S */ 4002/* File: mips64/unop.S */ 4003 /* 4004 * Generic 32-bit unary operation. Provide an "instr" line that 4005 * specifies an instruction that performs "a0 = op a0". 4006 * 4007 * for: int-to-byte, int-to-char, int-to-short, 4008 * not-int, neg-int 4009 */ 4010 /* unop vA, vB */ 4011 ext a3, rINST, 12, 4 # a3 <- B 4012 GET_VREG a0, a3 # a0 <- vB 4013 ext a2, rINST, 8, 4 # a2 <- A 4014 # optional op 4015 FETCH_ADVANCE_INST 1 # advance rPC, load rINST 4016 seh a0, a0 # a0 <- op, a0-a3 changed 4017 GET_INST_OPCODE v0 # extract opcode from rINST 4018 SET_VREG a0, a2 # vA <- a0 4019 GOTO_OPCODE v0 # jump to next instruction 4020 4021 4022/* ------------------------------ */ 4023 .balign 128 4024.L_op_add_int: /* 0x90 */ 4025/* File: mips64/op_add_int.S */ 4026/* File: mips64/binop.S */ 4027 /* 4028 * Generic 32-bit binary operation. Provide an "instr" line that 4029 * specifies an instruction that performs "result = a0 op a1". 4030 * This could be a MIPS instruction or a function call. (If the result 4031 * comes back in a register other than a0, you can override "result".) 4032 * 4033 * If "chkzero" is set to 1, we perform a divide-by-zero check on 4034 * vCC (a1). Useful for integer division and modulus. Note that we 4035 * *don't* check for (INT_MIN / -1) here, because the CPU handles it 4036 * correctly. 4037 * 4038 * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, 4039 * xor-int, shl-int, shr-int, ushr-int 4040 */ 4041 /* binop vAA, vBB, vCC */ 4042 srl a4, rINST, 8 # a4 <- AA 4043 lbu a2, 2(rPC) # a2 <- BB 4044 lbu a3, 3(rPC) # a3 <- CC 4045 GET_VREG a0, a2 # a0 <- vBB 4046 GET_VREG a1, a3 # a1 <- vCC 4047 .if 0 4048 beqz a1, common_errDivideByZero # is second operand zero? 4049 .endif 4050 FETCH_ADVANCE_INST 2 # advance rPC, load rINST 4051 # optional op 4052 addu a0, a0, a1 # a0 <- op, a0-a3 changed 4053 GET_INST_OPCODE v0 # extract opcode from rINST 4054 SET_VREG a0, a4 # vAA <- a0 4055 GOTO_OPCODE v0 # jump to next instruction 4056 4057 4058/* ------------------------------ */ 4059 .balign 128 4060.L_op_sub_int: /* 0x91 */ 4061/* File: mips64/op_sub_int.S */ 4062/* File: mips64/binop.S */ 4063 /* 4064 * Generic 32-bit binary operation. Provide an "instr" line that 4065 * specifies an instruction that performs "result = a0 op a1". 4066 * This could be a MIPS instruction or a function call. (If the result 4067 * comes back in a register other than a0, you can override "result".) 4068 * 4069 * If "chkzero" is set to 1, we perform a divide-by-zero check on 4070 * vCC (a1). Useful for integer division and modulus. Note that we 4071 * *don't* check for (INT_MIN / -1) here, because the CPU handles it 4072 * correctly. 4073 * 4074 * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, 4075 * xor-int, shl-int, shr-int, ushr-int 4076 */ 4077 /* binop vAA, vBB, vCC */ 4078 srl a4, rINST, 8 # a4 <- AA 4079 lbu a2, 2(rPC) # a2 <- BB 4080 lbu a3, 3(rPC) # a3 <- CC 4081 GET_VREG a0, a2 # a0 <- vBB 4082 GET_VREG a1, a3 # a1 <- vCC 4083 .if 0 4084 beqz a1, common_errDivideByZero # is second operand zero? 4085 .endif 4086 FETCH_ADVANCE_INST 2 # advance rPC, load rINST 4087 # optional op 4088 subu a0, a0, a1 # a0 <- op, a0-a3 changed 4089 GET_INST_OPCODE v0 # extract opcode from rINST 4090 SET_VREG a0, a4 # vAA <- a0 4091 GOTO_OPCODE v0 # jump to next instruction 4092 4093 4094/* ------------------------------ */ 4095 .balign 128 4096.L_op_mul_int: /* 0x92 */ 4097/* File: mips64/op_mul_int.S */ 4098/* File: mips64/binop.S */ 4099 /* 4100 * Generic 32-bit binary operation. Provide an "instr" line that 4101 * specifies an instruction that performs "result = a0 op a1". 4102 * This could be a MIPS instruction or a function call. (If the result 4103 * comes back in a register other than a0, you can override "result".) 4104 * 4105 * If "chkzero" is set to 1, we perform a divide-by-zero check on 4106 * vCC (a1). Useful for integer division and modulus. Note that we 4107 * *don't* check for (INT_MIN / -1) here, because the CPU handles it 4108 * correctly. 4109 * 4110 * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, 4111 * xor-int, shl-int, shr-int, ushr-int 4112 */ 4113 /* binop vAA, vBB, vCC */ 4114 srl a4, rINST, 8 # a4 <- AA 4115 lbu a2, 2(rPC) # a2 <- BB 4116 lbu a3, 3(rPC) # a3 <- CC 4117 GET_VREG a0, a2 # a0 <- vBB 4118 GET_VREG a1, a3 # a1 <- vCC 4119 .if 0 4120 beqz a1, common_errDivideByZero # is second operand zero? 4121 .endif 4122 FETCH_ADVANCE_INST 2 # advance rPC, load rINST 4123 # optional op 4124 mul a0, a0, a1 # a0 <- op, a0-a3 changed 4125 GET_INST_OPCODE v0 # extract opcode from rINST 4126 SET_VREG a0, a4 # vAA <- a0 4127 GOTO_OPCODE v0 # jump to next instruction 4128 4129 4130/* ------------------------------ */ 4131 .balign 128 4132.L_op_div_int: /* 0x93 */ 4133/* File: mips64/op_div_int.S */ 4134/* File: mips64/binop.S */ 4135 /* 4136 * Generic 32-bit binary operation. Provide an "instr" line that 4137 * specifies an instruction that performs "result = a0 op a1". 4138 * This could be a MIPS instruction or a function call. (If the result 4139 * comes back in a register other than a0, you can override "result".) 4140 * 4141 * If "chkzero" is set to 1, we perform a divide-by-zero check on 4142 * vCC (a1). Useful for integer division and modulus. Note that we 4143 * *don't* check for (INT_MIN / -1) here, because the CPU handles it 4144 * correctly. 4145 * 4146 * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, 4147 * xor-int, shl-int, shr-int, ushr-int 4148 */ 4149 /* binop vAA, vBB, vCC */ 4150 srl a4, rINST, 8 # a4 <- AA 4151 lbu a2, 2(rPC) # a2 <- BB 4152 lbu a3, 3(rPC) # a3 <- CC 4153 GET_VREG a0, a2 # a0 <- vBB 4154 GET_VREG a1, a3 # a1 <- vCC 4155 .if 1 4156 beqz a1, common_errDivideByZero # is second operand zero? 4157 .endif 4158 FETCH_ADVANCE_INST 2 # advance rPC, load rINST 4159 # optional op 4160 div a0, a0, a1 # a0 <- op, a0-a3 changed 4161 GET_INST_OPCODE v0 # extract opcode from rINST 4162 SET_VREG a0, a4 # vAA <- a0 4163 GOTO_OPCODE v0 # jump to next instruction 4164 4165 4166/* ------------------------------ */ 4167 .balign 128 4168.L_op_rem_int: /* 0x94 */ 4169/* File: mips64/op_rem_int.S */ 4170/* File: mips64/binop.S */ 4171 /* 4172 * Generic 32-bit binary operation. Provide an "instr" line that 4173 * specifies an instruction that performs "result = a0 op a1". 4174 * This could be a MIPS instruction or a function call. (If the result 4175 * comes back in a register other than a0, you can override "result".) 4176 * 4177 * If "chkzero" is set to 1, we perform a divide-by-zero check on 4178 * vCC (a1). Useful for integer division and modulus. Note that we 4179 * *don't* check for (INT_MIN / -1) here, because the CPU handles it 4180 * correctly. 4181 * 4182 * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, 4183 * xor-int, shl-int, shr-int, ushr-int 4184 */ 4185 /* binop vAA, vBB, vCC */ 4186 srl a4, rINST, 8 # a4 <- AA 4187 lbu a2, 2(rPC) # a2 <- BB 4188 lbu a3, 3(rPC) # a3 <- CC 4189 GET_VREG a0, a2 # a0 <- vBB 4190 GET_VREG a1, a3 # a1 <- vCC 4191 .if 1 4192 beqz a1, common_errDivideByZero # is second operand zero? 4193 .endif 4194 FETCH_ADVANCE_INST 2 # advance rPC, load rINST 4195 # optional op 4196 mod a0, a0, a1 # a0 <- op, a0-a3 changed 4197 GET_INST_OPCODE v0 # extract opcode from rINST 4198 SET_VREG a0, a4 # vAA <- a0 4199 GOTO_OPCODE v0 # jump to next instruction 4200 4201 4202/* ------------------------------ */ 4203 .balign 128 4204.L_op_and_int: /* 0x95 */ 4205/* File: mips64/op_and_int.S */ 4206/* File: mips64/binop.S */ 4207 /* 4208 * Generic 32-bit binary operation. Provide an "instr" line that 4209 * specifies an instruction that performs "result = a0 op a1". 4210 * This could be a MIPS instruction or a function call. (If the result 4211 * comes back in a register other than a0, you can override "result".) 4212 * 4213 * If "chkzero" is set to 1, we perform a divide-by-zero check on 4214 * vCC (a1). Useful for integer division and modulus. Note that we 4215 * *don't* check for (INT_MIN / -1) here, because the CPU handles it 4216 * correctly. 4217 * 4218 * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, 4219 * xor-int, shl-int, shr-int, ushr-int 4220 */ 4221 /* binop vAA, vBB, vCC */ 4222 srl a4, rINST, 8 # a4 <- AA 4223 lbu a2, 2(rPC) # a2 <- BB 4224 lbu a3, 3(rPC) # a3 <- CC 4225 GET_VREG a0, a2 # a0 <- vBB 4226 GET_VREG a1, a3 # a1 <- vCC 4227 .if 0 4228 beqz a1, common_errDivideByZero # is second operand zero? 4229 .endif 4230 FETCH_ADVANCE_INST 2 # advance rPC, load rINST 4231 # optional op 4232 and a0, a0, a1 # a0 <- op, a0-a3 changed 4233 GET_INST_OPCODE v0 # extract opcode from rINST 4234 SET_VREG a0, a4 # vAA <- a0 4235 GOTO_OPCODE v0 # jump to next instruction 4236 4237 4238/* ------------------------------ */ 4239 .balign 128 4240.L_op_or_int: /* 0x96 */ 4241/* File: mips64/op_or_int.S */ 4242/* File: mips64/binop.S */ 4243 /* 4244 * Generic 32-bit binary operation. Provide an "instr" line that 4245 * specifies an instruction that performs "result = a0 op a1". 4246 * This could be a MIPS instruction or a function call. (If the result 4247 * comes back in a register other than a0, you can override "result".) 4248 * 4249 * If "chkzero" is set to 1, we perform a divide-by-zero check on 4250 * vCC (a1). Useful for integer division and modulus. Note that we 4251 * *don't* check for (INT_MIN / -1) here, because the CPU handles it 4252 * correctly. 4253 * 4254 * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, 4255 * xor-int, shl-int, shr-int, ushr-int 4256 */ 4257 /* binop vAA, vBB, vCC */ 4258 srl a4, rINST, 8 # a4 <- AA 4259 lbu a2, 2(rPC) # a2 <- BB 4260 lbu a3, 3(rPC) # a3 <- CC 4261 GET_VREG a0, a2 # a0 <- vBB 4262 GET_VREG a1, a3 # a1 <- vCC 4263 .if 0 4264 beqz a1, common_errDivideByZero # is second operand zero? 4265 .endif 4266 FETCH_ADVANCE_INST 2 # advance rPC, load rINST 4267 # optional op 4268 or a0, a0, a1 # a0 <- op, a0-a3 changed 4269 GET_INST_OPCODE v0 # extract opcode from rINST 4270 SET_VREG a0, a4 # vAA <- a0 4271 GOTO_OPCODE v0 # jump to next instruction 4272 4273 4274/* ------------------------------ */ 4275 .balign 128 4276.L_op_xor_int: /* 0x97 */ 4277/* File: mips64/op_xor_int.S */ 4278/* File: mips64/binop.S */ 4279 /* 4280 * Generic 32-bit binary operation. Provide an "instr" line that 4281 * specifies an instruction that performs "result = a0 op a1". 4282 * This could be a MIPS instruction or a function call. (If the result 4283 * comes back in a register other than a0, you can override "result".) 4284 * 4285 * If "chkzero" is set to 1, we perform a divide-by-zero check on 4286 * vCC (a1). Useful for integer division and modulus. Note that we 4287 * *don't* check for (INT_MIN / -1) here, because the CPU handles it 4288 * correctly. 4289 * 4290 * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, 4291 * xor-int, shl-int, shr-int, ushr-int 4292 */ 4293 /* binop vAA, vBB, vCC */ 4294 srl a4, rINST, 8 # a4 <- AA 4295 lbu a2, 2(rPC) # a2 <- BB 4296 lbu a3, 3(rPC) # a3 <- CC 4297 GET_VREG a0, a2 # a0 <- vBB 4298 GET_VREG a1, a3 # a1 <- vCC 4299 .if 0 4300 beqz a1, common_errDivideByZero # is second operand zero? 4301 .endif 4302 FETCH_ADVANCE_INST 2 # advance rPC, load rINST 4303 # optional op 4304 xor a0, a0, a1 # a0 <- op, a0-a3 changed 4305 GET_INST_OPCODE v0 # extract opcode from rINST 4306 SET_VREG a0, a4 # vAA <- a0 4307 GOTO_OPCODE v0 # jump to next instruction 4308 4309 4310/* ------------------------------ */ 4311 .balign 128 4312.L_op_shl_int: /* 0x98 */ 4313/* File: mips64/op_shl_int.S */ 4314/* File: mips64/binop.S */ 4315 /* 4316 * Generic 32-bit binary operation. Provide an "instr" line that 4317 * specifies an instruction that performs "result = a0 op a1". 4318 * This could be a MIPS instruction or a function call. (If the result 4319 * comes back in a register other than a0, you can override "result".) 4320 * 4321 * If "chkzero" is set to 1, we perform a divide-by-zero check on 4322 * vCC (a1). Useful for integer division and modulus. Note that we 4323 * *don't* check for (INT_MIN / -1) here, because the CPU handles it 4324 * correctly. 4325 * 4326 * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, 4327 * xor-int, shl-int, shr-int, ushr-int 4328 */ 4329 /* binop vAA, vBB, vCC */ 4330 srl a4, rINST, 8 # a4 <- AA 4331 lbu a2, 2(rPC) # a2 <- BB 4332 lbu a3, 3(rPC) # a3 <- CC 4333 GET_VREG a0, a2 # a0 <- vBB 4334 GET_VREG a1, a3 # a1 <- vCC 4335 .if 0 4336 beqz a1, common_errDivideByZero # is second operand zero? 4337 .endif 4338 FETCH_ADVANCE_INST 2 # advance rPC, load rINST 4339 # optional op 4340 sll a0, a0, a1 # a0 <- op, a0-a3 changed 4341 GET_INST_OPCODE v0 # extract opcode from rINST 4342 SET_VREG a0, a4 # vAA <- a0 4343 GOTO_OPCODE v0 # jump to next instruction 4344 4345 4346/* ------------------------------ */ 4347 .balign 128 4348.L_op_shr_int: /* 0x99 */ 4349/* File: mips64/op_shr_int.S */ 4350/* File: mips64/binop.S */ 4351 /* 4352 * Generic 32-bit binary operation. Provide an "instr" line that 4353 * specifies an instruction that performs "result = a0 op a1". 4354 * This could be a MIPS instruction or a function call. (If the result 4355 * comes back in a register other than a0, you can override "result".) 4356 * 4357 * If "chkzero" is set to 1, we perform a divide-by-zero check on 4358 * vCC (a1). Useful for integer division and modulus. Note that we 4359 * *don't* check for (INT_MIN / -1) here, because the CPU handles it 4360 * correctly. 4361 * 4362 * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, 4363 * xor-int, shl-int, shr-int, ushr-int 4364 */ 4365 /* binop vAA, vBB, vCC */ 4366 srl a4, rINST, 8 # a4 <- AA 4367 lbu a2, 2(rPC) # a2 <- BB 4368 lbu a3, 3(rPC) # a3 <- CC 4369 GET_VREG a0, a2 # a0 <- vBB 4370 GET_VREG a1, a3 # a1 <- vCC 4371 .if 0 4372 beqz a1, common_errDivideByZero # is second operand zero? 4373 .endif 4374 FETCH_ADVANCE_INST 2 # advance rPC, load rINST 4375 # optional op 4376 sra a0, a0, a1 # a0 <- op, a0-a3 changed 4377 GET_INST_OPCODE v0 # extract opcode from rINST 4378 SET_VREG a0, a4 # vAA <- a0 4379 GOTO_OPCODE v0 # jump to next instruction 4380 4381 4382/* ------------------------------ */ 4383 .balign 128 4384.L_op_ushr_int: /* 0x9a */ 4385/* File: mips64/op_ushr_int.S */ 4386/* File: mips64/binop.S */ 4387 /* 4388 * Generic 32-bit binary operation. Provide an "instr" line that 4389 * specifies an instruction that performs "result = a0 op a1". 4390 * This could be a MIPS instruction or a function call. (If the result 4391 * comes back in a register other than a0, you can override "result".) 4392 * 4393 * If "chkzero" is set to 1, we perform a divide-by-zero check on 4394 * vCC (a1). Useful for integer division and modulus. Note that we 4395 * *don't* check for (INT_MIN / -1) here, because the CPU handles it 4396 * correctly. 4397 * 4398 * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, 4399 * xor-int, shl-int, shr-int, ushr-int 4400 */ 4401 /* binop vAA, vBB, vCC */ 4402 srl a4, rINST, 8 # a4 <- AA 4403 lbu a2, 2(rPC) # a2 <- BB 4404 lbu a3, 3(rPC) # a3 <- CC 4405 GET_VREG a0, a2 # a0 <- vBB 4406 GET_VREG a1, a3 # a1 <- vCC 4407 .if 0 4408 beqz a1, common_errDivideByZero # is second operand zero? 4409 .endif 4410 FETCH_ADVANCE_INST 2 # advance rPC, load rINST 4411 # optional op 4412 srl a0, a0, a1 # a0 <- op, a0-a3 changed 4413 GET_INST_OPCODE v0 # extract opcode from rINST 4414 SET_VREG a0, a4 # vAA <- a0 4415 GOTO_OPCODE v0 # jump to next instruction 4416 4417 4418/* ------------------------------ */ 4419 .balign 128 4420.L_op_add_long: /* 0x9b */ 4421/* File: mips64/op_add_long.S */ 4422/* File: mips64/binopWide.S */ 4423 /* 4424 * Generic 64-bit binary operation. Provide an "instr" line that 4425 * specifies an instruction that performs "result = a0 op a1". 4426 * This could be a MIPS instruction or a function call. (If the result 4427 * comes back in a register other than a0, you can override "result".) 4428 * 4429 * If "chkzero" is set to 1, we perform a divide-by-zero check on 4430 * vCC (a1). Useful for integer division and modulus. Note that we 4431 * *don't* check for (LONG_MIN / -1) here, because the CPU handles it 4432 * correctly. 4433 * 4434 * For: add-long, sub-long, mul-long, div-long, rem-long, and-long, or-long, 4435 * xor-long, shl-long, shr-long, ushr-long 4436 */ 4437 /* binop vAA, vBB, vCC */ 4438 srl a4, rINST, 8 # a4 <- AA 4439 lbu a2, 2(rPC) # a2 <- BB 4440 lbu a3, 3(rPC) # a3 <- CC 4441 GET_VREG_WIDE a0, a2 # a0 <- vBB 4442 GET_VREG_WIDE a1, a3 # a1 <- vCC 4443 .if 0 4444 beqz a1, common_errDivideByZero # is second operand zero? 4445 .endif 4446 FETCH_ADVANCE_INST 2 # advance rPC, load rINST 4447 # optional op 4448 daddu a0, a0, a1 # a0 <- op, a0-a3 changed 4449 GET_INST_OPCODE v0 # extract opcode from rINST 4450 SET_VREG_WIDE a0, a4 # vAA <- a0 4451 GOTO_OPCODE v0 # jump to next instruction 4452 4453 4454/* ------------------------------ */ 4455 .balign 128 4456.L_op_sub_long: /* 0x9c */ 4457/* File: mips64/op_sub_long.S */ 4458/* File: mips64/binopWide.S */ 4459 /* 4460 * Generic 64-bit binary operation. Provide an "instr" line that 4461 * specifies an instruction that performs "result = a0 op a1". 4462 * This could be a MIPS instruction or a function call. (If the result 4463 * comes back in a register other than a0, you can override "result".) 4464 * 4465 * If "chkzero" is set to 1, we perform a divide-by-zero check on 4466 * vCC (a1). Useful for integer division and modulus. Note that we 4467 * *don't* check for (LONG_MIN / -1) here, because the CPU handles it 4468 * correctly. 4469 * 4470 * For: add-long, sub-long, mul-long, div-long, rem-long, and-long, or-long, 4471 * xor-long, shl-long, shr-long, ushr-long 4472 */ 4473 /* binop vAA, vBB, vCC */ 4474 srl a4, rINST, 8 # a4 <- AA 4475 lbu a2, 2(rPC) # a2 <- BB 4476 lbu a3, 3(rPC) # a3 <- CC 4477 GET_VREG_WIDE a0, a2 # a0 <- vBB 4478 GET_VREG_WIDE a1, a3 # a1 <- vCC 4479 .if 0 4480 beqz a1, common_errDivideByZero # is second operand zero? 4481 .endif 4482 FETCH_ADVANCE_INST 2 # advance rPC, load rINST 4483 # optional op 4484 dsubu a0, a0, a1 # a0 <- op, a0-a3 changed 4485 GET_INST_OPCODE v0 # extract opcode from rINST 4486 SET_VREG_WIDE a0, a4 # vAA <- a0 4487 GOTO_OPCODE v0 # jump to next instruction 4488 4489 4490/* ------------------------------ */ 4491 .balign 128 4492.L_op_mul_long: /* 0x9d */ 4493/* File: mips64/op_mul_long.S */ 4494/* File: mips64/binopWide.S */ 4495 /* 4496 * Generic 64-bit binary operation. Provide an "instr" line that 4497 * specifies an instruction that performs "result = a0 op a1". 4498 * This could be a MIPS instruction or a function call. (If the result 4499 * comes back in a register other than a0, you can override "result".) 4500 * 4501 * If "chkzero" is set to 1, we perform a divide-by-zero check on 4502 * vCC (a1). Useful for integer division and modulus. Note that we 4503 * *don't* check for (LONG_MIN / -1) here, because the CPU handles it 4504 * correctly. 4505 * 4506 * For: add-long, sub-long, mul-long, div-long, rem-long, and-long, or-long, 4507 * xor-long, shl-long, shr-long, ushr-long 4508 */ 4509 /* binop vAA, vBB, vCC */ 4510 srl a4, rINST, 8 # a4 <- AA 4511 lbu a2, 2(rPC) # a2 <- BB 4512 lbu a3, 3(rPC) # a3 <- CC 4513 GET_VREG_WIDE a0, a2 # a0 <- vBB 4514 GET_VREG_WIDE a1, a3 # a1 <- vCC 4515 .if 0 4516 beqz a1, common_errDivideByZero # is second operand zero? 4517 .endif 4518 FETCH_ADVANCE_INST 2 # advance rPC, load rINST 4519 # optional op 4520 dmul a0, a0, a1 # a0 <- op, a0-a3 changed 4521 GET_INST_OPCODE v0 # extract opcode from rINST 4522 SET_VREG_WIDE a0, a4 # vAA <- a0 4523 GOTO_OPCODE v0 # jump to next instruction 4524 4525 4526/* ------------------------------ */ 4527 .balign 128 4528.L_op_div_long: /* 0x9e */ 4529/* File: mips64/op_div_long.S */ 4530/* File: mips64/binopWide.S */ 4531 /* 4532 * Generic 64-bit binary operation. Provide an "instr" line that 4533 * specifies an instruction that performs "result = a0 op a1". 4534 * This could be a MIPS instruction or a function call. (If the result 4535 * comes back in a register other than a0, you can override "result".) 4536 * 4537 * If "chkzero" is set to 1, we perform a divide-by-zero check on 4538 * vCC (a1). Useful for integer division and modulus. Note that we 4539 * *don't* check for (LONG_MIN / -1) here, because the CPU handles it 4540 * correctly. 4541 * 4542 * For: add-long, sub-long, mul-long, div-long, rem-long, and-long, or-long, 4543 * xor-long, shl-long, shr-long, ushr-long 4544 */ 4545 /* binop vAA, vBB, vCC */ 4546 srl a4, rINST, 8 # a4 <- AA 4547 lbu a2, 2(rPC) # a2 <- BB 4548 lbu a3, 3(rPC) # a3 <- CC 4549 GET_VREG_WIDE a0, a2 # a0 <- vBB 4550 GET_VREG_WIDE a1, a3 # a1 <- vCC 4551 .if 1 4552 beqz a1, common_errDivideByZero # is second operand zero? 4553 .endif 4554 FETCH_ADVANCE_INST 2 # advance rPC, load rINST 4555 # optional op 4556 ddiv a0, a0, a1 # a0 <- op, a0-a3 changed 4557 GET_INST_OPCODE v0 # extract opcode from rINST 4558 SET_VREG_WIDE a0, a4 # vAA <- a0 4559 GOTO_OPCODE v0 # jump to next instruction 4560 4561 4562/* ------------------------------ */ 4563 .balign 128 4564.L_op_rem_long: /* 0x9f */ 4565/* File: mips64/op_rem_long.S */ 4566/* File: mips64/binopWide.S */ 4567 /* 4568 * Generic 64-bit binary operation. Provide an "instr" line that 4569 * specifies an instruction that performs "result = a0 op a1". 4570 * This could be a MIPS instruction or a function call. (If the result 4571 * comes back in a register other than a0, you can override "result".) 4572 * 4573 * If "chkzero" is set to 1, we perform a divide-by-zero check on 4574 * vCC (a1). Useful for integer division and modulus. Note that we 4575 * *don't* check for (LONG_MIN / -1) here, because the CPU handles it 4576 * correctly. 4577 * 4578 * For: add-long, sub-long, mul-long, div-long, rem-long, and-long, or-long, 4579 * xor-long, shl-long, shr-long, ushr-long 4580 */ 4581 /* binop vAA, vBB, vCC */ 4582 srl a4, rINST, 8 # a4 <- AA 4583 lbu a2, 2(rPC) # a2 <- BB 4584 lbu a3, 3(rPC) # a3 <- CC 4585 GET_VREG_WIDE a0, a2 # a0 <- vBB 4586 GET_VREG_WIDE a1, a3 # a1 <- vCC 4587 .if 1 4588 beqz a1, common_errDivideByZero # is second operand zero? 4589 .endif 4590 FETCH_ADVANCE_INST 2 # advance rPC, load rINST 4591 # optional op 4592 dmod a0, a0, a1 # a0 <- op, a0-a3 changed 4593 GET_INST_OPCODE v0 # extract opcode from rINST 4594 SET_VREG_WIDE a0, a4 # vAA <- a0 4595 GOTO_OPCODE v0 # jump to next instruction 4596 4597 4598/* ------------------------------ */ 4599 .balign 128 4600.L_op_and_long: /* 0xa0 */ 4601/* File: mips64/op_and_long.S */ 4602/* File: mips64/binopWide.S */ 4603 /* 4604 * Generic 64-bit binary operation. Provide an "instr" line that 4605 * specifies an instruction that performs "result = a0 op a1". 4606 * This could be a MIPS instruction or a function call. (If the result 4607 * comes back in a register other than a0, you can override "result".) 4608 * 4609 * If "chkzero" is set to 1, we perform a divide-by-zero check on 4610 * vCC (a1). Useful for integer division and modulus. Note that we 4611 * *don't* check for (LONG_MIN / -1) here, because the CPU handles it 4612 * correctly. 4613 * 4614 * For: add-long, sub-long, mul-long, div-long, rem-long, and-long, or-long, 4615 * xor-long, shl-long, shr-long, ushr-long 4616 */ 4617 /* binop vAA, vBB, vCC */ 4618 srl a4, rINST, 8 # a4 <- AA 4619 lbu a2, 2(rPC) # a2 <- BB 4620 lbu a3, 3(rPC) # a3 <- CC 4621 GET_VREG_WIDE a0, a2 # a0 <- vBB 4622 GET_VREG_WIDE a1, a3 # a1 <- vCC 4623 .if 0 4624 beqz a1, common_errDivideByZero # is second operand zero? 4625 .endif 4626 FETCH_ADVANCE_INST 2 # advance rPC, load rINST 4627 # optional op 4628 and a0, a0, a1 # a0 <- op, a0-a3 changed 4629 GET_INST_OPCODE v0 # extract opcode from rINST 4630 SET_VREG_WIDE a0, a4 # vAA <- a0 4631 GOTO_OPCODE v0 # jump to next instruction 4632 4633 4634/* ------------------------------ */ 4635 .balign 128 4636.L_op_or_long: /* 0xa1 */ 4637/* File: mips64/op_or_long.S */ 4638/* File: mips64/binopWide.S */ 4639 /* 4640 * Generic 64-bit binary operation. Provide an "instr" line that 4641 * specifies an instruction that performs "result = a0 op a1". 4642 * This could be a MIPS instruction or a function call. (If the result 4643 * comes back in a register other than a0, you can override "result".) 4644 * 4645 * If "chkzero" is set to 1, we perform a divide-by-zero check on 4646 * vCC (a1). Useful for integer division and modulus. Note that we 4647 * *don't* check for (LONG_MIN / -1) here, because the CPU handles it 4648 * correctly. 4649 * 4650 * For: add-long, sub-long, mul-long, div-long, rem-long, and-long, or-long, 4651 * xor-long, shl-long, shr-long, ushr-long 4652 */ 4653 /* binop vAA, vBB, vCC */ 4654 srl a4, rINST, 8 # a4 <- AA 4655 lbu a2, 2(rPC) # a2 <- BB 4656 lbu a3, 3(rPC) # a3 <- CC 4657 GET_VREG_WIDE a0, a2 # a0 <- vBB 4658 GET_VREG_WIDE a1, a3 # a1 <- vCC 4659 .if 0 4660 beqz a1, common_errDivideByZero # is second operand zero? 4661 .endif 4662 FETCH_ADVANCE_INST 2 # advance rPC, load rINST 4663 # optional op 4664 or a0, a0, a1 # a0 <- op, a0-a3 changed 4665 GET_INST_OPCODE v0 # extract opcode from rINST 4666 SET_VREG_WIDE a0, a4 # vAA <- a0 4667 GOTO_OPCODE v0 # jump to next instruction 4668 4669 4670/* ------------------------------ */ 4671 .balign 128 4672.L_op_xor_long: /* 0xa2 */ 4673/* File: mips64/op_xor_long.S */ 4674/* File: mips64/binopWide.S */ 4675 /* 4676 * Generic 64-bit binary operation. Provide an "instr" line that 4677 * specifies an instruction that performs "result = a0 op a1". 4678 * This could be a MIPS instruction or a function call. (If the result 4679 * comes back in a register other than a0, you can override "result".) 4680 * 4681 * If "chkzero" is set to 1, we perform a divide-by-zero check on 4682 * vCC (a1). Useful for integer division and modulus. Note that we 4683 * *don't* check for (LONG_MIN / -1) here, because the CPU handles it 4684 * correctly. 4685 * 4686 * For: add-long, sub-long, mul-long, div-long, rem-long, and-long, or-long, 4687 * xor-long, shl-long, shr-long, ushr-long 4688 */ 4689 /* binop vAA, vBB, vCC */ 4690 srl a4, rINST, 8 # a4 <- AA 4691 lbu a2, 2(rPC) # a2 <- BB 4692 lbu a3, 3(rPC) # a3 <- CC 4693 GET_VREG_WIDE a0, a2 # a0 <- vBB 4694 GET_VREG_WIDE a1, a3 # a1 <- vCC 4695 .if 0 4696 beqz a1, common_errDivideByZero # is second operand zero? 4697 .endif 4698 FETCH_ADVANCE_INST 2 # advance rPC, load rINST 4699 # optional op 4700 xor a0, a0, a1 # a0 <- op, a0-a3 changed 4701 GET_INST_OPCODE v0 # extract opcode from rINST 4702 SET_VREG_WIDE a0, a4 # vAA <- a0 4703 GOTO_OPCODE v0 # jump to next instruction 4704 4705 4706/* ------------------------------ */ 4707 .balign 128 4708.L_op_shl_long: /* 0xa3 */ 4709/* File: mips64/op_shl_long.S */ 4710/* File: mips64/binopWide.S */ 4711 /* 4712 * Generic 64-bit binary operation. Provide an "instr" line that 4713 * specifies an instruction that performs "result = a0 op a1". 4714 * This could be a MIPS instruction or a function call. (If the result 4715 * comes back in a register other than a0, you can override "result".) 4716 * 4717 * If "chkzero" is set to 1, we perform a divide-by-zero check on 4718 * vCC (a1). Useful for integer division and modulus. Note that we 4719 * *don't* check for (LONG_MIN / -1) here, because the CPU handles it 4720 * correctly. 4721 * 4722 * For: add-long, sub-long, mul-long, div-long, rem-long, and-long, or-long, 4723 * xor-long, shl-long, shr-long, ushr-long 4724 */ 4725 /* binop vAA, vBB, vCC */ 4726 srl a4, rINST, 8 # a4 <- AA 4727 lbu a2, 2(rPC) # a2 <- BB 4728 lbu a3, 3(rPC) # a3 <- CC 4729 GET_VREG_WIDE a0, a2 # a0 <- vBB 4730 GET_VREG_WIDE a1, a3 # a1 <- vCC 4731 .if 0 4732 beqz a1, common_errDivideByZero # is second operand zero? 4733 .endif 4734 FETCH_ADVANCE_INST 2 # advance rPC, load rINST 4735 # optional op 4736 dsll a0, a0, a1 # a0 <- op, a0-a3 changed 4737 GET_INST_OPCODE v0 # extract opcode from rINST 4738 SET_VREG_WIDE a0, a4 # vAA <- a0 4739 GOTO_OPCODE v0 # jump to next instruction 4740 4741 4742/* ------------------------------ */ 4743 .balign 128 4744.L_op_shr_long: /* 0xa4 */ 4745/* File: mips64/op_shr_long.S */ 4746/* File: mips64/binopWide.S */ 4747 /* 4748 * Generic 64-bit binary operation. Provide an "instr" line that 4749 * specifies an instruction that performs "result = a0 op a1". 4750 * This could be a MIPS instruction or a function call. (If the result 4751 * comes back in a register other than a0, you can override "result".) 4752 * 4753 * If "chkzero" is set to 1, we perform a divide-by-zero check on 4754 * vCC (a1). Useful for integer division and modulus. Note that we 4755 * *don't* check for (LONG_MIN / -1) here, because the CPU handles it 4756 * correctly. 4757 * 4758 * For: add-long, sub-long, mul-long, div-long, rem-long, and-long, or-long, 4759 * xor-long, shl-long, shr-long, ushr-long 4760 */ 4761 /* binop vAA, vBB, vCC */ 4762 srl a4, rINST, 8 # a4 <- AA 4763 lbu a2, 2(rPC) # a2 <- BB 4764 lbu a3, 3(rPC) # a3 <- CC 4765 GET_VREG_WIDE a0, a2 # a0 <- vBB 4766 GET_VREG_WIDE a1, a3 # a1 <- vCC 4767 .if 0 4768 beqz a1, common_errDivideByZero # is second operand zero? 4769 .endif 4770 FETCH_ADVANCE_INST 2 # advance rPC, load rINST 4771 # optional op 4772 dsra a0, a0, a1 # a0 <- op, a0-a3 changed 4773 GET_INST_OPCODE v0 # extract opcode from rINST 4774 SET_VREG_WIDE a0, a4 # vAA <- a0 4775 GOTO_OPCODE v0 # jump to next instruction 4776 4777 4778/* ------------------------------ */ 4779 .balign 128 4780.L_op_ushr_long: /* 0xa5 */ 4781/* File: mips64/op_ushr_long.S */ 4782/* File: mips64/binopWide.S */ 4783 /* 4784 * Generic 64-bit binary operation. Provide an "instr" line that 4785 * specifies an instruction that performs "result = a0 op a1". 4786 * This could be a MIPS instruction or a function call. (If the result 4787 * comes back in a register other than a0, you can override "result".) 4788 * 4789 * If "chkzero" is set to 1, we perform a divide-by-zero check on 4790 * vCC (a1). Useful for integer division and modulus. Note that we 4791 * *don't* check for (LONG_MIN / -1) here, because the CPU handles it 4792 * correctly. 4793 * 4794 * For: add-long, sub-long, mul-long, div-long, rem-long, and-long, or-long, 4795 * xor-long, shl-long, shr-long, ushr-long 4796 */ 4797 /* binop vAA, vBB, vCC */ 4798 srl a4, rINST, 8 # a4 <- AA 4799 lbu a2, 2(rPC) # a2 <- BB 4800 lbu a3, 3(rPC) # a3 <- CC 4801 GET_VREG_WIDE a0, a2 # a0 <- vBB 4802 GET_VREG_WIDE a1, a3 # a1 <- vCC 4803 .if 0 4804 beqz a1, common_errDivideByZero # is second operand zero? 4805 .endif 4806 FETCH_ADVANCE_INST 2 # advance rPC, load rINST 4807 # optional op 4808 dsrl a0, a0, a1 # a0 <- op, a0-a3 changed 4809 GET_INST_OPCODE v0 # extract opcode from rINST 4810 SET_VREG_WIDE a0, a4 # vAA <- a0 4811 GOTO_OPCODE v0 # jump to next instruction 4812 4813 4814/* ------------------------------ */ 4815 .balign 128 4816.L_op_add_float: /* 0xa6 */ 4817/* File: mips64/op_add_float.S */ 4818/* File: mips64/fbinop.S */ 4819 /*: 4820 * Generic 32-bit floating-point operation. 4821 * 4822 * For: add-float, sub-float, mul-float, div-float. 4823 * form: <op> f0, f0, f1 4824 */ 4825 /* binop vAA, vBB, vCC */ 4826 srl a4, rINST, 8 # a4 <- AA 4827 lbu a2, 2(rPC) # a2 <- BB 4828 lbu a3, 3(rPC) # a3 <- CC 4829 GET_VREG_FLOAT f0, a2 # f0 <- vBB 4830 GET_VREG_FLOAT f1, a3 # f1 <- vCC 4831 add.s f0, f0, f1 # f0 <- f0 op f1 4832 FETCH_ADVANCE_INST 2 # advance rPC, load rINST 4833 GET_INST_OPCODE v0 # extract opcode from rINST 4834 SET_VREG_FLOAT f0, a4 # vAA <- f0 4835 GOTO_OPCODE v0 # jump to next instruction 4836 4837 4838/* ------------------------------ */ 4839 .balign 128 4840.L_op_sub_float: /* 0xa7 */ 4841/* File: mips64/op_sub_float.S */ 4842/* File: mips64/fbinop.S */ 4843 /*: 4844 * Generic 32-bit floating-point operation. 4845 * 4846 * For: add-float, sub-float, mul-float, div-float. 4847 * form: <op> f0, f0, f1 4848 */ 4849 /* binop vAA, vBB, vCC */ 4850 srl a4, rINST, 8 # a4 <- AA 4851 lbu a2, 2(rPC) # a2 <- BB 4852 lbu a3, 3(rPC) # a3 <- CC 4853 GET_VREG_FLOAT f0, a2 # f0 <- vBB 4854 GET_VREG_FLOAT f1, a3 # f1 <- vCC 4855 sub.s f0, f0, f1 # f0 <- f0 op f1 4856 FETCH_ADVANCE_INST 2 # advance rPC, load rINST 4857 GET_INST_OPCODE v0 # extract opcode from rINST 4858 SET_VREG_FLOAT f0, a4 # vAA <- f0 4859 GOTO_OPCODE v0 # jump to next instruction 4860 4861 4862/* ------------------------------ */ 4863 .balign 128 4864.L_op_mul_float: /* 0xa8 */ 4865/* File: mips64/op_mul_float.S */ 4866/* File: mips64/fbinop.S */ 4867 /*: 4868 * Generic 32-bit floating-point operation. 4869 * 4870 * For: add-float, sub-float, mul-float, div-float. 4871 * form: <op> f0, f0, f1 4872 */ 4873 /* binop vAA, vBB, vCC */ 4874 srl a4, rINST, 8 # a4 <- AA 4875 lbu a2, 2(rPC) # a2 <- BB 4876 lbu a3, 3(rPC) # a3 <- CC 4877 GET_VREG_FLOAT f0, a2 # f0 <- vBB 4878 GET_VREG_FLOAT f1, a3 # f1 <- vCC 4879 mul.s f0, f0, f1 # f0 <- f0 op f1 4880 FETCH_ADVANCE_INST 2 # advance rPC, load rINST 4881 GET_INST_OPCODE v0 # extract opcode from rINST 4882 SET_VREG_FLOAT f0, a4 # vAA <- f0 4883 GOTO_OPCODE v0 # jump to next instruction 4884 4885 4886/* ------------------------------ */ 4887 .balign 128 4888.L_op_div_float: /* 0xa9 */ 4889/* File: mips64/op_div_float.S */ 4890/* File: mips64/fbinop.S */ 4891 /*: 4892 * Generic 32-bit floating-point operation. 4893 * 4894 * For: add-float, sub-float, mul-float, div-float. 4895 * form: <op> f0, f0, f1 4896 */ 4897 /* binop vAA, vBB, vCC */ 4898 srl a4, rINST, 8 # a4 <- AA 4899 lbu a2, 2(rPC) # a2 <- BB 4900 lbu a3, 3(rPC) # a3 <- CC 4901 GET_VREG_FLOAT f0, a2 # f0 <- vBB 4902 GET_VREG_FLOAT f1, a3 # f1 <- vCC 4903 div.s f0, f0, f1 # f0 <- f0 op f1 4904 FETCH_ADVANCE_INST 2 # advance rPC, load rINST 4905 GET_INST_OPCODE v0 # extract opcode from rINST 4906 SET_VREG_FLOAT f0, a4 # vAA <- f0 4907 GOTO_OPCODE v0 # jump to next instruction 4908 4909 4910/* ------------------------------ */ 4911 .balign 128 4912.L_op_rem_float: /* 0xaa */ 4913/* File: mips64/op_rem_float.S */ 4914 /* rem-float vAA, vBB, vCC */ 4915 .extern fmodf 4916 lbu a2, 2(rPC) # a2 <- BB 4917 lbu a3, 3(rPC) # a3 <- CC 4918 GET_VREG_FLOAT f12, a2 # f12 <- vBB 4919 GET_VREG_FLOAT f13, a3 # f13 <- vCC 4920 jal fmodf # f0 <- f12 op f13 4921 srl a4, rINST, 8 # a4 <- AA 4922 FETCH_ADVANCE_INST 2 # advance rPC, load rINST 4923 GET_INST_OPCODE v0 # extract opcode from rINST 4924 SET_VREG_FLOAT f0, a4 # vAA <- f0 4925 GOTO_OPCODE v0 # jump to next instruction 4926 4927/* ------------------------------ */ 4928 .balign 128 4929.L_op_add_double: /* 0xab */ 4930/* File: mips64/op_add_double.S */ 4931/* File: mips64/fbinopWide.S */ 4932 /*: 4933 * Generic 64-bit floating-point operation. 4934 * 4935 * For: add-double, sub-double, mul-double, div-double. 4936 * form: <op> f0, f0, f1 4937 */ 4938 /* binop vAA, vBB, vCC */ 4939 srl a4, rINST, 8 # a4 <- AA 4940 lbu a2, 2(rPC) # a2 <- BB 4941 lbu a3, 3(rPC) # a3 <- CC 4942 GET_VREG_DOUBLE f0, a2 # f0 <- vBB 4943 GET_VREG_DOUBLE f1, a3 # f1 <- vCC 4944 add.d f0, f0, f1 # f0 <- f0 op f1 4945 FETCH_ADVANCE_INST 2 # advance rPC, load rINST 4946 GET_INST_OPCODE v0 # extract opcode from rINST 4947 SET_VREG_DOUBLE f0, a4 # vAA <- f0 4948 GOTO_OPCODE v0 # jump to next instruction 4949 4950 4951/* ------------------------------ */ 4952 .balign 128 4953.L_op_sub_double: /* 0xac */ 4954/* File: mips64/op_sub_double.S */ 4955/* File: mips64/fbinopWide.S */ 4956 /*: 4957 * Generic 64-bit floating-point operation. 4958 * 4959 * For: add-double, sub-double, mul-double, div-double. 4960 * form: <op> f0, f0, f1 4961 */ 4962 /* binop vAA, vBB, vCC */ 4963 srl a4, rINST, 8 # a4 <- AA 4964 lbu a2, 2(rPC) # a2 <- BB 4965 lbu a3, 3(rPC) # a3 <- CC 4966 GET_VREG_DOUBLE f0, a2 # f0 <- vBB 4967 GET_VREG_DOUBLE f1, a3 # f1 <- vCC 4968 sub.d f0, f0, f1 # f0 <- f0 op f1 4969 FETCH_ADVANCE_INST 2 # advance rPC, load rINST 4970 GET_INST_OPCODE v0 # extract opcode from rINST 4971 SET_VREG_DOUBLE f0, a4 # vAA <- f0 4972 GOTO_OPCODE v0 # jump to next instruction 4973 4974 4975/* ------------------------------ */ 4976 .balign 128 4977.L_op_mul_double: /* 0xad */ 4978/* File: mips64/op_mul_double.S */ 4979/* File: mips64/fbinopWide.S */ 4980 /*: 4981 * Generic 64-bit floating-point operation. 4982 * 4983 * For: add-double, sub-double, mul-double, div-double. 4984 * form: <op> f0, f0, f1 4985 */ 4986 /* binop vAA, vBB, vCC */ 4987 srl a4, rINST, 8 # a4 <- AA 4988 lbu a2, 2(rPC) # a2 <- BB 4989 lbu a3, 3(rPC) # a3 <- CC 4990 GET_VREG_DOUBLE f0, a2 # f0 <- vBB 4991 GET_VREG_DOUBLE f1, a3 # f1 <- vCC 4992 mul.d f0, f0, f1 # f0 <- f0 op f1 4993 FETCH_ADVANCE_INST 2 # advance rPC, load rINST 4994 GET_INST_OPCODE v0 # extract opcode from rINST 4995 SET_VREG_DOUBLE f0, a4 # vAA <- f0 4996 GOTO_OPCODE v0 # jump to next instruction 4997 4998 4999/* ------------------------------ */ 5000 .balign 128 5001.L_op_div_double: /* 0xae */ 5002/* File: mips64/op_div_double.S */ 5003/* File: mips64/fbinopWide.S */ 5004 /*: 5005 * Generic 64-bit floating-point operation. 5006 * 5007 * For: add-double, sub-double, mul-double, div-double. 5008 * form: <op> f0, f0, f1 5009 */ 5010 /* binop vAA, vBB, vCC */ 5011 srl a4, rINST, 8 # a4 <- AA 5012 lbu a2, 2(rPC) # a2 <- BB 5013 lbu a3, 3(rPC) # a3 <- CC 5014 GET_VREG_DOUBLE f0, a2 # f0 <- vBB 5015 GET_VREG_DOUBLE f1, a3 # f1 <- vCC 5016 div.d f0, f0, f1 # f0 <- f0 op f1 5017 FETCH_ADVANCE_INST 2 # advance rPC, load rINST 5018 GET_INST_OPCODE v0 # extract opcode from rINST 5019 SET_VREG_DOUBLE f0, a4 # vAA <- f0 5020 GOTO_OPCODE v0 # jump to next instruction 5021 5022 5023/* ------------------------------ */ 5024 .balign 128 5025.L_op_rem_double: /* 0xaf */ 5026/* File: mips64/op_rem_double.S */ 5027 /* rem-double vAA, vBB, vCC */ 5028 .extern fmod 5029 lbu a2, 2(rPC) # a2 <- BB 5030 lbu a3, 3(rPC) # a3 <- CC 5031 GET_VREG_DOUBLE f12, a2 # f12 <- vBB 5032 GET_VREG_DOUBLE f13, a3 # f13 <- vCC 5033 jal fmod # f0 <- f12 op f13 5034 srl a4, rINST, 8 # a4 <- AA 5035 FETCH_ADVANCE_INST 2 # advance rPC, load rINST 5036 GET_INST_OPCODE v0 # extract opcode from rINST 5037 SET_VREG_DOUBLE f0, a4 # vAA <- f0 5038 GOTO_OPCODE v0 # jump to next instruction 5039 5040/* ------------------------------ */ 5041 .balign 128 5042.L_op_add_int_2addr: /* 0xb0 */ 5043/* File: mips64/op_add_int_2addr.S */ 5044/* File: mips64/binop2addr.S */ 5045 /* 5046 * Generic 32-bit "/2addr" binary operation. Provide an "instr" line 5047 * that specifies an instruction that performs "result = a0 op a1". 5048 * This could be a MIPS instruction or a function call. (If the result 5049 * comes back in a register other than a0, you can override "result".) 5050 * 5051 * If "chkzero" is set to 1, we perform a divide-by-zero check on 5052 * vB (a1). Useful for integer division and modulus. Note that we 5053 * *don't* check for (INT_MIN / -1) here, because the CPU handles it 5054 * correctly. 5055 * 5056 * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, 5057 * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, 5058 * shl-int/2addr, shr-int/2addr, ushr-int/2addr 5059 */ 5060 /* binop/2addr vA, vB */ 5061 ext a2, rINST, 8, 4 # a2 <- A 5062 ext a3, rINST, 12, 4 # a3 <- B 5063 GET_VREG a0, a2 # a0 <- vA 5064 GET_VREG a1, a3 # a1 <- vB 5065 .if 0 5066 beqz a1, common_errDivideByZero # is second operand zero? 5067 .endif 5068 FETCH_ADVANCE_INST 1 # advance rPC, load rINST 5069 # optional op 5070 addu a0, a0, a1 # a0 <- op, a0-a3 changed 5071 GET_INST_OPCODE v0 # extract opcode from rINST 5072 SET_VREG a0, a2 # vA <- a0 5073 GOTO_OPCODE v0 # jump to next instruction 5074 5075 5076/* ------------------------------ */ 5077 .balign 128 5078.L_op_sub_int_2addr: /* 0xb1 */ 5079/* File: mips64/op_sub_int_2addr.S */ 5080/* File: mips64/binop2addr.S */ 5081 /* 5082 * Generic 32-bit "/2addr" binary operation. Provide an "instr" line 5083 * that specifies an instruction that performs "result = a0 op a1". 5084 * This could be a MIPS instruction or a function call. (If the result 5085 * comes back in a register other than a0, you can override "result".) 5086 * 5087 * If "chkzero" is set to 1, we perform a divide-by-zero check on 5088 * vB (a1). Useful for integer division and modulus. Note that we 5089 * *don't* check for (INT_MIN / -1) here, because the CPU handles it 5090 * correctly. 5091 * 5092 * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, 5093 * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, 5094 * shl-int/2addr, shr-int/2addr, ushr-int/2addr 5095 */ 5096 /* binop/2addr vA, vB */ 5097 ext a2, rINST, 8, 4 # a2 <- A 5098 ext a3, rINST, 12, 4 # a3 <- B 5099 GET_VREG a0, a2 # a0 <- vA 5100 GET_VREG a1, a3 # a1 <- vB 5101 .if 0 5102 beqz a1, common_errDivideByZero # is second operand zero? 5103 .endif 5104 FETCH_ADVANCE_INST 1 # advance rPC, load rINST 5105 # optional op 5106 subu a0, a0, a1 # a0 <- op, a0-a3 changed 5107 GET_INST_OPCODE v0 # extract opcode from rINST 5108 SET_VREG a0, a2 # vA <- a0 5109 GOTO_OPCODE v0 # jump to next instruction 5110 5111 5112/* ------------------------------ */ 5113 .balign 128 5114.L_op_mul_int_2addr: /* 0xb2 */ 5115/* File: mips64/op_mul_int_2addr.S */ 5116/* File: mips64/binop2addr.S */ 5117 /* 5118 * Generic 32-bit "/2addr" binary operation. Provide an "instr" line 5119 * that specifies an instruction that performs "result = a0 op a1". 5120 * This could be a MIPS instruction or a function call. (If the result 5121 * comes back in a register other than a0, you can override "result".) 5122 * 5123 * If "chkzero" is set to 1, we perform a divide-by-zero check on 5124 * vB (a1). Useful for integer division and modulus. Note that we 5125 * *don't* check for (INT_MIN / -1) here, because the CPU handles it 5126 * correctly. 5127 * 5128 * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, 5129 * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, 5130 * shl-int/2addr, shr-int/2addr, ushr-int/2addr 5131 */ 5132 /* binop/2addr vA, vB */ 5133 ext a2, rINST, 8, 4 # a2 <- A 5134 ext a3, rINST, 12, 4 # a3 <- B 5135 GET_VREG a0, a2 # a0 <- vA 5136 GET_VREG a1, a3 # a1 <- vB 5137 .if 0 5138 beqz a1, common_errDivideByZero # is second operand zero? 5139 .endif 5140 FETCH_ADVANCE_INST 1 # advance rPC, load rINST 5141 # optional op 5142 mul a0, a0, a1 # a0 <- op, a0-a3 changed 5143 GET_INST_OPCODE v0 # extract opcode from rINST 5144 SET_VREG a0, a2 # vA <- a0 5145 GOTO_OPCODE v0 # jump to next instruction 5146 5147 5148/* ------------------------------ */ 5149 .balign 128 5150.L_op_div_int_2addr: /* 0xb3 */ 5151/* File: mips64/op_div_int_2addr.S */ 5152/* File: mips64/binop2addr.S */ 5153 /* 5154 * Generic 32-bit "/2addr" binary operation. Provide an "instr" line 5155 * that specifies an instruction that performs "result = a0 op a1". 5156 * This could be a MIPS instruction or a function call. (If the result 5157 * comes back in a register other than a0, you can override "result".) 5158 * 5159 * If "chkzero" is set to 1, we perform a divide-by-zero check on 5160 * vB (a1). Useful for integer division and modulus. Note that we 5161 * *don't* check for (INT_MIN / -1) here, because the CPU handles it 5162 * correctly. 5163 * 5164 * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, 5165 * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, 5166 * shl-int/2addr, shr-int/2addr, ushr-int/2addr 5167 */ 5168 /* binop/2addr vA, vB */ 5169 ext a2, rINST, 8, 4 # a2 <- A 5170 ext a3, rINST, 12, 4 # a3 <- B 5171 GET_VREG a0, a2 # a0 <- vA 5172 GET_VREG a1, a3 # a1 <- vB 5173 .if 1 5174 beqz a1, common_errDivideByZero # is second operand zero? 5175 .endif 5176 FETCH_ADVANCE_INST 1 # advance rPC, load rINST 5177 # optional op 5178 div a0, a0, a1 # a0 <- op, a0-a3 changed 5179 GET_INST_OPCODE v0 # extract opcode from rINST 5180 SET_VREG a0, a2 # vA <- a0 5181 GOTO_OPCODE v0 # jump to next instruction 5182 5183 5184/* ------------------------------ */ 5185 .balign 128 5186.L_op_rem_int_2addr: /* 0xb4 */ 5187/* File: mips64/op_rem_int_2addr.S */ 5188/* File: mips64/binop2addr.S */ 5189 /* 5190 * Generic 32-bit "/2addr" binary operation. Provide an "instr" line 5191 * that specifies an instruction that performs "result = a0 op a1". 5192 * This could be a MIPS instruction or a function call. (If the result 5193 * comes back in a register other than a0, you can override "result".) 5194 * 5195 * If "chkzero" is set to 1, we perform a divide-by-zero check on 5196 * vB (a1). Useful for integer division and modulus. Note that we 5197 * *don't* check for (INT_MIN / -1) here, because the CPU handles it 5198 * correctly. 5199 * 5200 * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, 5201 * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, 5202 * shl-int/2addr, shr-int/2addr, ushr-int/2addr 5203 */ 5204 /* binop/2addr vA, vB */ 5205 ext a2, rINST, 8, 4 # a2 <- A 5206 ext a3, rINST, 12, 4 # a3 <- B 5207 GET_VREG a0, a2 # a0 <- vA 5208 GET_VREG a1, a3 # a1 <- vB 5209 .if 1 5210 beqz a1, common_errDivideByZero # is second operand zero? 5211 .endif 5212 FETCH_ADVANCE_INST 1 # advance rPC, load rINST 5213 # optional op 5214 mod a0, a0, a1 # a0 <- op, a0-a3 changed 5215 GET_INST_OPCODE v0 # extract opcode from rINST 5216 SET_VREG a0, a2 # vA <- a0 5217 GOTO_OPCODE v0 # jump to next instruction 5218 5219 5220/* ------------------------------ */ 5221 .balign 128 5222.L_op_and_int_2addr: /* 0xb5 */ 5223/* File: mips64/op_and_int_2addr.S */ 5224/* File: mips64/binop2addr.S */ 5225 /* 5226 * Generic 32-bit "/2addr" binary operation. Provide an "instr" line 5227 * that specifies an instruction that performs "result = a0 op a1". 5228 * This could be a MIPS instruction or a function call. (If the result 5229 * comes back in a register other than a0, you can override "result".) 5230 * 5231 * If "chkzero" is set to 1, we perform a divide-by-zero check on 5232 * vB (a1). Useful for integer division and modulus. Note that we 5233 * *don't* check for (INT_MIN / -1) here, because the CPU handles it 5234 * correctly. 5235 * 5236 * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, 5237 * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, 5238 * shl-int/2addr, shr-int/2addr, ushr-int/2addr 5239 */ 5240 /* binop/2addr vA, vB */ 5241 ext a2, rINST, 8, 4 # a2 <- A 5242 ext a3, rINST, 12, 4 # a3 <- B 5243 GET_VREG a0, a2 # a0 <- vA 5244 GET_VREG a1, a3 # a1 <- vB 5245 .if 0 5246 beqz a1, common_errDivideByZero # is second operand zero? 5247 .endif 5248 FETCH_ADVANCE_INST 1 # advance rPC, load rINST 5249 # optional op 5250 and a0, a0, a1 # a0 <- op, a0-a3 changed 5251 GET_INST_OPCODE v0 # extract opcode from rINST 5252 SET_VREG a0, a2 # vA <- a0 5253 GOTO_OPCODE v0 # jump to next instruction 5254 5255 5256/* ------------------------------ */ 5257 .balign 128 5258.L_op_or_int_2addr: /* 0xb6 */ 5259/* File: mips64/op_or_int_2addr.S */ 5260/* File: mips64/binop2addr.S */ 5261 /* 5262 * Generic 32-bit "/2addr" binary operation. Provide an "instr" line 5263 * that specifies an instruction that performs "result = a0 op a1". 5264 * This could be a MIPS instruction or a function call. (If the result 5265 * comes back in a register other than a0, you can override "result".) 5266 * 5267 * If "chkzero" is set to 1, we perform a divide-by-zero check on 5268 * vB (a1). Useful for integer division and modulus. Note that we 5269 * *don't* check for (INT_MIN / -1) here, because the CPU handles it 5270 * correctly. 5271 * 5272 * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, 5273 * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, 5274 * shl-int/2addr, shr-int/2addr, ushr-int/2addr 5275 */ 5276 /* binop/2addr vA, vB */ 5277 ext a2, rINST, 8, 4 # a2 <- A 5278 ext a3, rINST, 12, 4 # a3 <- B 5279 GET_VREG a0, a2 # a0 <- vA 5280 GET_VREG a1, a3 # a1 <- vB 5281 .if 0 5282 beqz a1, common_errDivideByZero # is second operand zero? 5283 .endif 5284 FETCH_ADVANCE_INST 1 # advance rPC, load rINST 5285 # optional op 5286 or a0, a0, a1 # a0 <- op, a0-a3 changed 5287 GET_INST_OPCODE v0 # extract opcode from rINST 5288 SET_VREG a0, a2 # vA <- a0 5289 GOTO_OPCODE v0 # jump to next instruction 5290 5291 5292/* ------------------------------ */ 5293 .balign 128 5294.L_op_xor_int_2addr: /* 0xb7 */ 5295/* File: mips64/op_xor_int_2addr.S */ 5296/* File: mips64/binop2addr.S */ 5297 /* 5298 * Generic 32-bit "/2addr" binary operation. Provide an "instr" line 5299 * that specifies an instruction that performs "result = a0 op a1". 5300 * This could be a MIPS instruction or a function call. (If the result 5301 * comes back in a register other than a0, you can override "result".) 5302 * 5303 * If "chkzero" is set to 1, we perform a divide-by-zero check on 5304 * vB (a1). Useful for integer division and modulus. Note that we 5305 * *don't* check for (INT_MIN / -1) here, because the CPU handles it 5306 * correctly. 5307 * 5308 * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, 5309 * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, 5310 * shl-int/2addr, shr-int/2addr, ushr-int/2addr 5311 */ 5312 /* binop/2addr vA, vB */ 5313 ext a2, rINST, 8, 4 # a2 <- A 5314 ext a3, rINST, 12, 4 # a3 <- B 5315 GET_VREG a0, a2 # a0 <- vA 5316 GET_VREG a1, a3 # a1 <- vB 5317 .if 0 5318 beqz a1, common_errDivideByZero # is second operand zero? 5319 .endif 5320 FETCH_ADVANCE_INST 1 # advance rPC, load rINST 5321 # optional op 5322 xor a0, a0, a1 # a0 <- op, a0-a3 changed 5323 GET_INST_OPCODE v0 # extract opcode from rINST 5324 SET_VREG a0, a2 # vA <- a0 5325 GOTO_OPCODE v0 # jump to next instruction 5326 5327 5328/* ------------------------------ */ 5329 .balign 128 5330.L_op_shl_int_2addr: /* 0xb8 */ 5331/* File: mips64/op_shl_int_2addr.S */ 5332/* File: mips64/binop2addr.S */ 5333 /* 5334 * Generic 32-bit "/2addr" binary operation. Provide an "instr" line 5335 * that specifies an instruction that performs "result = a0 op a1". 5336 * This could be a MIPS instruction or a function call. (If the result 5337 * comes back in a register other than a0, you can override "result".) 5338 * 5339 * If "chkzero" is set to 1, we perform a divide-by-zero check on 5340 * vB (a1). Useful for integer division and modulus. Note that we 5341 * *don't* check for (INT_MIN / -1) here, because the CPU handles it 5342 * correctly. 5343 * 5344 * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, 5345 * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, 5346 * shl-int/2addr, shr-int/2addr, ushr-int/2addr 5347 */ 5348 /* binop/2addr vA, vB */ 5349 ext a2, rINST, 8, 4 # a2 <- A 5350 ext a3, rINST, 12, 4 # a3 <- B 5351 GET_VREG a0, a2 # a0 <- vA 5352 GET_VREG a1, a3 # a1 <- vB 5353 .if 0 5354 beqz a1, common_errDivideByZero # is second operand zero? 5355 .endif 5356 FETCH_ADVANCE_INST 1 # advance rPC, load rINST 5357 # optional op 5358 sll a0, a0, a1 # a0 <- op, a0-a3 changed 5359 GET_INST_OPCODE v0 # extract opcode from rINST 5360 SET_VREG a0, a2 # vA <- a0 5361 GOTO_OPCODE v0 # jump to next instruction 5362 5363 5364/* ------------------------------ */ 5365 .balign 128 5366.L_op_shr_int_2addr: /* 0xb9 */ 5367/* File: mips64/op_shr_int_2addr.S */ 5368/* File: mips64/binop2addr.S */ 5369 /* 5370 * Generic 32-bit "/2addr" binary operation. Provide an "instr" line 5371 * that specifies an instruction that performs "result = a0 op a1". 5372 * This could be a MIPS instruction or a function call. (If the result 5373 * comes back in a register other than a0, you can override "result".) 5374 * 5375 * If "chkzero" is set to 1, we perform a divide-by-zero check on 5376 * vB (a1). Useful for integer division and modulus. Note that we 5377 * *don't* check for (INT_MIN / -1) here, because the CPU handles it 5378 * correctly. 5379 * 5380 * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, 5381 * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, 5382 * shl-int/2addr, shr-int/2addr, ushr-int/2addr 5383 */ 5384 /* binop/2addr vA, vB */ 5385 ext a2, rINST, 8, 4 # a2 <- A 5386 ext a3, rINST, 12, 4 # a3 <- B 5387 GET_VREG a0, a2 # a0 <- vA 5388 GET_VREG a1, a3 # a1 <- vB 5389 .if 0 5390 beqz a1, common_errDivideByZero # is second operand zero? 5391 .endif 5392 FETCH_ADVANCE_INST 1 # advance rPC, load rINST 5393 # optional op 5394 sra a0, a0, a1 # a0 <- op, a0-a3 changed 5395 GET_INST_OPCODE v0 # extract opcode from rINST 5396 SET_VREG a0, a2 # vA <- a0 5397 GOTO_OPCODE v0 # jump to next instruction 5398 5399 5400/* ------------------------------ */ 5401 .balign 128 5402.L_op_ushr_int_2addr: /* 0xba */ 5403/* File: mips64/op_ushr_int_2addr.S */ 5404/* File: mips64/binop2addr.S */ 5405 /* 5406 * Generic 32-bit "/2addr" binary operation. Provide an "instr" line 5407 * that specifies an instruction that performs "result = a0 op a1". 5408 * This could be a MIPS instruction or a function call. (If the result 5409 * comes back in a register other than a0, you can override "result".) 5410 * 5411 * If "chkzero" is set to 1, we perform a divide-by-zero check on 5412 * vB (a1). Useful for integer division and modulus. Note that we 5413 * *don't* check for (INT_MIN / -1) here, because the CPU handles it 5414 * correctly. 5415 * 5416 * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, 5417 * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, 5418 * shl-int/2addr, shr-int/2addr, ushr-int/2addr 5419 */ 5420 /* binop/2addr vA, vB */ 5421 ext a2, rINST, 8, 4 # a2 <- A 5422 ext a3, rINST, 12, 4 # a3 <- B 5423 GET_VREG a0, a2 # a0 <- vA 5424 GET_VREG a1, a3 # a1 <- vB 5425 .if 0 5426 beqz a1, common_errDivideByZero # is second operand zero? 5427 .endif 5428 FETCH_ADVANCE_INST 1 # advance rPC, load rINST 5429 # optional op 5430 srl a0, a0, a1 # a0 <- op, a0-a3 changed 5431 GET_INST_OPCODE v0 # extract opcode from rINST 5432 SET_VREG a0, a2 # vA <- a0 5433 GOTO_OPCODE v0 # jump to next instruction 5434 5435 5436/* ------------------------------ */ 5437 .balign 128 5438.L_op_add_long_2addr: /* 0xbb */ 5439/* File: mips64/op_add_long_2addr.S */ 5440/* File: mips64/binopWide2addr.S */ 5441 /* 5442 * Generic 64-bit "/2addr" binary operation. Provide an "instr" line 5443 * that specifies an instruction that performs "result = a0 op a1". 5444 * This could be a MIPS instruction or a function call. (If the result 5445 * comes back in a register other than a0, you can override "result".) 5446 * 5447 * If "chkzero" is set to 1, we perform a divide-by-zero check on 5448 * vB (a1). Useful for integer division and modulus. Note that we 5449 * *don't* check for (LONG_MIN / -1) here, because the CPU handles it 5450 * correctly. 5451 * 5452 * For: add-long/2addr, sub-long/2addr, mul-long/2addr, div-long/2addr, 5453 * rem-long/2addr, and-long/2addr, or-long/2addr, xor-long/2addr, 5454 * shl-long/2addr, shr-long/2addr, ushr-long/2addr 5455 */ 5456 /* binop/2addr vA, vB */ 5457 ext a2, rINST, 8, 4 # a2 <- A 5458 ext a3, rINST, 12, 4 # a3 <- B 5459 GET_VREG_WIDE a0, a2 # a0 <- vA 5460 GET_VREG_WIDE a1, a3 # a1 <- vB 5461 .if 0 5462 beqz a1, common_errDivideByZero # is second operand zero? 5463 .endif 5464 FETCH_ADVANCE_INST 1 # advance rPC, load rINST 5465 # optional op 5466 daddu a0, a0, a1 # a0 <- op, a0-a3 changed 5467 GET_INST_OPCODE v0 # extract opcode from rINST 5468 SET_VREG_WIDE a0, a2 # vA <- a0 5469 GOTO_OPCODE v0 # jump to next instruction 5470 5471 5472/* ------------------------------ */ 5473 .balign 128 5474.L_op_sub_long_2addr: /* 0xbc */ 5475/* File: mips64/op_sub_long_2addr.S */ 5476/* File: mips64/binopWide2addr.S */ 5477 /* 5478 * Generic 64-bit "/2addr" binary operation. Provide an "instr" line 5479 * that specifies an instruction that performs "result = a0 op a1". 5480 * This could be a MIPS instruction or a function call. (If the result 5481 * comes back in a register other than a0, you can override "result".) 5482 * 5483 * If "chkzero" is set to 1, we perform a divide-by-zero check on 5484 * vB (a1). Useful for integer division and modulus. Note that we 5485 * *don't* check for (LONG_MIN / -1) here, because the CPU handles it 5486 * correctly. 5487 * 5488 * For: add-long/2addr, sub-long/2addr, mul-long/2addr, div-long/2addr, 5489 * rem-long/2addr, and-long/2addr, or-long/2addr, xor-long/2addr, 5490 * shl-long/2addr, shr-long/2addr, ushr-long/2addr 5491 */ 5492 /* binop/2addr vA, vB */ 5493 ext a2, rINST, 8, 4 # a2 <- A 5494 ext a3, rINST, 12, 4 # a3 <- B 5495 GET_VREG_WIDE a0, a2 # a0 <- vA 5496 GET_VREG_WIDE a1, a3 # a1 <- vB 5497 .if 0 5498 beqz a1, common_errDivideByZero # is second operand zero? 5499 .endif 5500 FETCH_ADVANCE_INST 1 # advance rPC, load rINST 5501 # optional op 5502 dsubu a0, a0, a1 # a0 <- op, a0-a3 changed 5503 GET_INST_OPCODE v0 # extract opcode from rINST 5504 SET_VREG_WIDE a0, a2 # vA <- a0 5505 GOTO_OPCODE v0 # jump to next instruction 5506 5507 5508/* ------------------------------ */ 5509 .balign 128 5510.L_op_mul_long_2addr: /* 0xbd */ 5511/* File: mips64/op_mul_long_2addr.S */ 5512/* File: mips64/binopWide2addr.S */ 5513 /* 5514 * Generic 64-bit "/2addr" binary operation. Provide an "instr" line 5515 * that specifies an instruction that performs "result = a0 op a1". 5516 * This could be a MIPS instruction or a function call. (If the result 5517 * comes back in a register other than a0, you can override "result".) 5518 * 5519 * If "chkzero" is set to 1, we perform a divide-by-zero check on 5520 * vB (a1). Useful for integer division and modulus. Note that we 5521 * *don't* check for (LONG_MIN / -1) here, because the CPU handles it 5522 * correctly. 5523 * 5524 * For: add-long/2addr, sub-long/2addr, mul-long/2addr, div-long/2addr, 5525 * rem-long/2addr, and-long/2addr, or-long/2addr, xor-long/2addr, 5526 * shl-long/2addr, shr-long/2addr, ushr-long/2addr 5527 */ 5528 /* binop/2addr vA, vB */ 5529 ext a2, rINST, 8, 4 # a2 <- A 5530 ext a3, rINST, 12, 4 # a3 <- B 5531 GET_VREG_WIDE a0, a2 # a0 <- vA 5532 GET_VREG_WIDE a1, a3 # a1 <- vB 5533 .if 0 5534 beqz a1, common_errDivideByZero # is second operand zero? 5535 .endif 5536 FETCH_ADVANCE_INST 1 # advance rPC, load rINST 5537 # optional op 5538 dmul a0, a0, a1 # a0 <- op, a0-a3 changed 5539 GET_INST_OPCODE v0 # extract opcode from rINST 5540 SET_VREG_WIDE a0, a2 # vA <- a0 5541 GOTO_OPCODE v0 # jump to next instruction 5542 5543 5544/* ------------------------------ */ 5545 .balign 128 5546.L_op_div_long_2addr: /* 0xbe */ 5547/* File: mips64/op_div_long_2addr.S */ 5548/* File: mips64/binopWide2addr.S */ 5549 /* 5550 * Generic 64-bit "/2addr" binary operation. Provide an "instr" line 5551 * that specifies an instruction that performs "result = a0 op a1". 5552 * This could be a MIPS instruction or a function call. (If the result 5553 * comes back in a register other than a0, you can override "result".) 5554 * 5555 * If "chkzero" is set to 1, we perform a divide-by-zero check on 5556 * vB (a1). Useful for integer division and modulus. Note that we 5557 * *don't* check for (LONG_MIN / -1) here, because the CPU handles it 5558 * correctly. 5559 * 5560 * For: add-long/2addr, sub-long/2addr, mul-long/2addr, div-long/2addr, 5561 * rem-long/2addr, and-long/2addr, or-long/2addr, xor-long/2addr, 5562 * shl-long/2addr, shr-long/2addr, ushr-long/2addr 5563 */ 5564 /* binop/2addr vA, vB */ 5565 ext a2, rINST, 8, 4 # a2 <- A 5566 ext a3, rINST, 12, 4 # a3 <- B 5567 GET_VREG_WIDE a0, a2 # a0 <- vA 5568 GET_VREG_WIDE a1, a3 # a1 <- vB 5569 .if 1 5570 beqz a1, common_errDivideByZero # is second operand zero? 5571 .endif 5572 FETCH_ADVANCE_INST 1 # advance rPC, load rINST 5573 # optional op 5574 ddiv a0, a0, a1 # a0 <- op, a0-a3 changed 5575 GET_INST_OPCODE v0 # extract opcode from rINST 5576 SET_VREG_WIDE a0, a2 # vA <- a0 5577 GOTO_OPCODE v0 # jump to next instruction 5578 5579 5580/* ------------------------------ */ 5581 .balign 128 5582.L_op_rem_long_2addr: /* 0xbf */ 5583/* File: mips64/op_rem_long_2addr.S */ 5584/* File: mips64/binopWide2addr.S */ 5585 /* 5586 * Generic 64-bit "/2addr" binary operation. Provide an "instr" line 5587 * that specifies an instruction that performs "result = a0 op a1". 5588 * This could be a MIPS instruction or a function call. (If the result 5589 * comes back in a register other than a0, you can override "result".) 5590 * 5591 * If "chkzero" is set to 1, we perform a divide-by-zero check on 5592 * vB (a1). Useful for integer division and modulus. Note that we 5593 * *don't* check for (LONG_MIN / -1) here, because the CPU handles it 5594 * correctly. 5595 * 5596 * For: add-long/2addr, sub-long/2addr, mul-long/2addr, div-long/2addr, 5597 * rem-long/2addr, and-long/2addr, or-long/2addr, xor-long/2addr, 5598 * shl-long/2addr, shr-long/2addr, ushr-long/2addr 5599 */ 5600 /* binop/2addr vA, vB */ 5601 ext a2, rINST, 8, 4 # a2 <- A 5602 ext a3, rINST, 12, 4 # a3 <- B 5603 GET_VREG_WIDE a0, a2 # a0 <- vA 5604 GET_VREG_WIDE a1, a3 # a1 <- vB 5605 .if 1 5606 beqz a1, common_errDivideByZero # is second operand zero? 5607 .endif 5608 FETCH_ADVANCE_INST 1 # advance rPC, load rINST 5609 # optional op 5610 dmod a0, a0, a1 # a0 <- op, a0-a3 changed 5611 GET_INST_OPCODE v0 # extract opcode from rINST 5612 SET_VREG_WIDE a0, a2 # vA <- a0 5613 GOTO_OPCODE v0 # jump to next instruction 5614 5615 5616/* ------------------------------ */ 5617 .balign 128 5618.L_op_and_long_2addr: /* 0xc0 */ 5619/* File: mips64/op_and_long_2addr.S */ 5620/* File: mips64/binopWide2addr.S */ 5621 /* 5622 * Generic 64-bit "/2addr" binary operation. Provide an "instr" line 5623 * that specifies an instruction that performs "result = a0 op a1". 5624 * This could be a MIPS instruction or a function call. (If the result 5625 * comes back in a register other than a0, you can override "result".) 5626 * 5627 * If "chkzero" is set to 1, we perform a divide-by-zero check on 5628 * vB (a1). Useful for integer division and modulus. Note that we 5629 * *don't* check for (LONG_MIN / -1) here, because the CPU handles it 5630 * correctly. 5631 * 5632 * For: add-long/2addr, sub-long/2addr, mul-long/2addr, div-long/2addr, 5633 * rem-long/2addr, and-long/2addr, or-long/2addr, xor-long/2addr, 5634 * shl-long/2addr, shr-long/2addr, ushr-long/2addr 5635 */ 5636 /* binop/2addr vA, vB */ 5637 ext a2, rINST, 8, 4 # a2 <- A 5638 ext a3, rINST, 12, 4 # a3 <- B 5639 GET_VREG_WIDE a0, a2 # a0 <- vA 5640 GET_VREG_WIDE a1, a3 # a1 <- vB 5641 .if 0 5642 beqz a1, common_errDivideByZero # is second operand zero? 5643 .endif 5644 FETCH_ADVANCE_INST 1 # advance rPC, load rINST 5645 # optional op 5646 and a0, a0, a1 # a0 <- op, a0-a3 changed 5647 GET_INST_OPCODE v0 # extract opcode from rINST 5648 SET_VREG_WIDE a0, a2 # vA <- a0 5649 GOTO_OPCODE v0 # jump to next instruction 5650 5651 5652/* ------------------------------ */ 5653 .balign 128 5654.L_op_or_long_2addr: /* 0xc1 */ 5655/* File: mips64/op_or_long_2addr.S */ 5656/* File: mips64/binopWide2addr.S */ 5657 /* 5658 * Generic 64-bit "/2addr" binary operation. Provide an "instr" line 5659 * that specifies an instruction that performs "result = a0 op a1". 5660 * This could be a MIPS instruction or a function call. (If the result 5661 * comes back in a register other than a0, you can override "result".) 5662 * 5663 * If "chkzero" is set to 1, we perform a divide-by-zero check on 5664 * vB (a1). Useful for integer division and modulus. Note that we 5665 * *don't* check for (LONG_MIN / -1) here, because the CPU handles it 5666 * correctly. 5667 * 5668 * For: add-long/2addr, sub-long/2addr, mul-long/2addr, div-long/2addr, 5669 * rem-long/2addr, and-long/2addr, or-long/2addr, xor-long/2addr, 5670 * shl-long/2addr, shr-long/2addr, ushr-long/2addr 5671 */ 5672 /* binop/2addr vA, vB */ 5673 ext a2, rINST, 8, 4 # a2 <- A 5674 ext a3, rINST, 12, 4 # a3 <- B 5675 GET_VREG_WIDE a0, a2 # a0 <- vA 5676 GET_VREG_WIDE a1, a3 # a1 <- vB 5677 .if 0 5678 beqz a1, common_errDivideByZero # is second operand zero? 5679 .endif 5680 FETCH_ADVANCE_INST 1 # advance rPC, load rINST 5681 # optional op 5682 or a0, a0, a1 # a0 <- op, a0-a3 changed 5683 GET_INST_OPCODE v0 # extract opcode from rINST 5684 SET_VREG_WIDE a0, a2 # vA <- a0 5685 GOTO_OPCODE v0 # jump to next instruction 5686 5687 5688/* ------------------------------ */ 5689 .balign 128 5690.L_op_xor_long_2addr: /* 0xc2 */ 5691/* File: mips64/op_xor_long_2addr.S */ 5692/* File: mips64/binopWide2addr.S */ 5693 /* 5694 * Generic 64-bit "/2addr" binary operation. Provide an "instr" line 5695 * that specifies an instruction that performs "result = a0 op a1". 5696 * This could be a MIPS instruction or a function call. (If the result 5697 * comes back in a register other than a0, you can override "result".) 5698 * 5699 * If "chkzero" is set to 1, we perform a divide-by-zero check on 5700 * vB (a1). Useful for integer division and modulus. Note that we 5701 * *don't* check for (LONG_MIN / -1) here, because the CPU handles it 5702 * correctly. 5703 * 5704 * For: add-long/2addr, sub-long/2addr, mul-long/2addr, div-long/2addr, 5705 * rem-long/2addr, and-long/2addr, or-long/2addr, xor-long/2addr, 5706 * shl-long/2addr, shr-long/2addr, ushr-long/2addr 5707 */ 5708 /* binop/2addr vA, vB */ 5709 ext a2, rINST, 8, 4 # a2 <- A 5710 ext a3, rINST, 12, 4 # a3 <- B 5711 GET_VREG_WIDE a0, a2 # a0 <- vA 5712 GET_VREG_WIDE a1, a3 # a1 <- vB 5713 .if 0 5714 beqz a1, common_errDivideByZero # is second operand zero? 5715 .endif 5716 FETCH_ADVANCE_INST 1 # advance rPC, load rINST 5717 # optional op 5718 xor a0, a0, a1 # a0 <- op, a0-a3 changed 5719 GET_INST_OPCODE v0 # extract opcode from rINST 5720 SET_VREG_WIDE a0, a2 # vA <- a0 5721 GOTO_OPCODE v0 # jump to next instruction 5722 5723 5724/* ------------------------------ */ 5725 .balign 128 5726.L_op_shl_long_2addr: /* 0xc3 */ 5727/* File: mips64/op_shl_long_2addr.S */ 5728/* File: mips64/binopWide2addr.S */ 5729 /* 5730 * Generic 64-bit "/2addr" binary operation. Provide an "instr" line 5731 * that specifies an instruction that performs "result = a0 op a1". 5732 * This could be a MIPS instruction or a function call. (If the result 5733 * comes back in a register other than a0, you can override "result".) 5734 * 5735 * If "chkzero" is set to 1, we perform a divide-by-zero check on 5736 * vB (a1). Useful for integer division and modulus. Note that we 5737 * *don't* check for (LONG_MIN / -1) here, because the CPU handles it 5738 * correctly. 5739 * 5740 * For: add-long/2addr, sub-long/2addr, mul-long/2addr, div-long/2addr, 5741 * rem-long/2addr, and-long/2addr, or-long/2addr, xor-long/2addr, 5742 * shl-long/2addr, shr-long/2addr, ushr-long/2addr 5743 */ 5744 /* binop/2addr vA, vB */ 5745 ext a2, rINST, 8, 4 # a2 <- A 5746 ext a3, rINST, 12, 4 # a3 <- B 5747 GET_VREG_WIDE a0, a2 # a0 <- vA 5748 GET_VREG_WIDE a1, a3 # a1 <- vB 5749 .if 0 5750 beqz a1, common_errDivideByZero # is second operand zero? 5751 .endif 5752 FETCH_ADVANCE_INST 1 # advance rPC, load rINST 5753 # optional op 5754 dsll a0, a0, a1 # a0 <- op, a0-a3 changed 5755 GET_INST_OPCODE v0 # extract opcode from rINST 5756 SET_VREG_WIDE a0, a2 # vA <- a0 5757 GOTO_OPCODE v0 # jump to next instruction 5758 5759 5760/* ------------------------------ */ 5761 .balign 128 5762.L_op_shr_long_2addr: /* 0xc4 */ 5763/* File: mips64/op_shr_long_2addr.S */ 5764/* File: mips64/binopWide2addr.S */ 5765 /* 5766 * Generic 64-bit "/2addr" binary operation. Provide an "instr" line 5767 * that specifies an instruction that performs "result = a0 op a1". 5768 * This could be a MIPS instruction or a function call. (If the result 5769 * comes back in a register other than a0, you can override "result".) 5770 * 5771 * If "chkzero" is set to 1, we perform a divide-by-zero check on 5772 * vB (a1). Useful for integer division and modulus. Note that we 5773 * *don't* check for (LONG_MIN / -1) here, because the CPU handles it 5774 * correctly. 5775 * 5776 * For: add-long/2addr, sub-long/2addr, mul-long/2addr, div-long/2addr, 5777 * rem-long/2addr, and-long/2addr, or-long/2addr, xor-long/2addr, 5778 * shl-long/2addr, shr-long/2addr, ushr-long/2addr 5779 */ 5780 /* binop/2addr vA, vB */ 5781 ext a2, rINST, 8, 4 # a2 <- A 5782 ext a3, rINST, 12, 4 # a3 <- B 5783 GET_VREG_WIDE a0, a2 # a0 <- vA 5784 GET_VREG_WIDE a1, a3 # a1 <- vB 5785 .if 0 5786 beqz a1, common_errDivideByZero # is second operand zero? 5787 .endif 5788 FETCH_ADVANCE_INST 1 # advance rPC, load rINST 5789 # optional op 5790 dsra a0, a0, a1 # a0 <- op, a0-a3 changed 5791 GET_INST_OPCODE v0 # extract opcode from rINST 5792 SET_VREG_WIDE a0, a2 # vA <- a0 5793 GOTO_OPCODE v0 # jump to next instruction 5794 5795 5796/* ------------------------------ */ 5797 .balign 128 5798.L_op_ushr_long_2addr: /* 0xc5 */ 5799/* File: mips64/op_ushr_long_2addr.S */ 5800/* File: mips64/binopWide2addr.S */ 5801 /* 5802 * Generic 64-bit "/2addr" binary operation. Provide an "instr" line 5803 * that specifies an instruction that performs "result = a0 op a1". 5804 * This could be a MIPS instruction or a function call. (If the result 5805 * comes back in a register other than a0, you can override "result".) 5806 * 5807 * If "chkzero" is set to 1, we perform a divide-by-zero check on 5808 * vB (a1). Useful for integer division and modulus. Note that we 5809 * *don't* check for (LONG_MIN / -1) here, because the CPU handles it 5810 * correctly. 5811 * 5812 * For: add-long/2addr, sub-long/2addr, mul-long/2addr, div-long/2addr, 5813 * rem-long/2addr, and-long/2addr, or-long/2addr, xor-long/2addr, 5814 * shl-long/2addr, shr-long/2addr, ushr-long/2addr 5815 */ 5816 /* binop/2addr vA, vB */ 5817 ext a2, rINST, 8, 4 # a2 <- A 5818 ext a3, rINST, 12, 4 # a3 <- B 5819 GET_VREG_WIDE a0, a2 # a0 <- vA 5820 GET_VREG_WIDE a1, a3 # a1 <- vB 5821 .if 0 5822 beqz a1, common_errDivideByZero # is second operand zero? 5823 .endif 5824 FETCH_ADVANCE_INST 1 # advance rPC, load rINST 5825 # optional op 5826 dsrl a0, a0, a1 # a0 <- op, a0-a3 changed 5827 GET_INST_OPCODE v0 # extract opcode from rINST 5828 SET_VREG_WIDE a0, a2 # vA <- a0 5829 GOTO_OPCODE v0 # jump to next instruction 5830 5831 5832/* ------------------------------ */ 5833 .balign 128 5834.L_op_add_float_2addr: /* 0xc6 */ 5835/* File: mips64/op_add_float_2addr.S */ 5836/* File: mips64/fbinop2addr.S */ 5837 /*: 5838 * Generic 32-bit "/2addr" floating-point operation. 5839 * 5840 * For: add-float/2addr, sub-float/2addr, mul-float/2addr, div-float/2addr. 5841 * form: <op> f0, f0, f1 5842 */ 5843 /* binop/2addr vA, vB */ 5844 ext a2, rINST, 8, 4 # a2 <- A 5845 ext a3, rINST, 12, 4 # a3 <- B 5846 GET_VREG_FLOAT f0, a2 # f0 <- vA 5847 GET_VREG_FLOAT f1, a3 # f1 <- vB 5848 add.s f0, f0, f1 # f0 <- f0 op f1 5849 FETCH_ADVANCE_INST 1 # advance rPC, load rINST 5850 GET_INST_OPCODE v0 # extract opcode from rINST 5851 SET_VREG_FLOAT f0, a2 # vA <- f0 5852 GOTO_OPCODE v0 # jump to next instruction 5853 5854 5855/* ------------------------------ */ 5856 .balign 128 5857.L_op_sub_float_2addr: /* 0xc7 */ 5858/* File: mips64/op_sub_float_2addr.S */ 5859/* File: mips64/fbinop2addr.S */ 5860 /*: 5861 * Generic 32-bit "/2addr" floating-point operation. 5862 * 5863 * For: add-float/2addr, sub-float/2addr, mul-float/2addr, div-float/2addr. 5864 * form: <op> f0, f0, f1 5865 */ 5866 /* binop/2addr vA, vB */ 5867 ext a2, rINST, 8, 4 # a2 <- A 5868 ext a3, rINST, 12, 4 # a3 <- B 5869 GET_VREG_FLOAT f0, a2 # f0 <- vA 5870 GET_VREG_FLOAT f1, a3 # f1 <- vB 5871 sub.s f0, f0, f1 # f0 <- f0 op f1 5872 FETCH_ADVANCE_INST 1 # advance rPC, load rINST 5873 GET_INST_OPCODE v0 # extract opcode from rINST 5874 SET_VREG_FLOAT f0, a2 # vA <- f0 5875 GOTO_OPCODE v0 # jump to next instruction 5876 5877 5878/* ------------------------------ */ 5879 .balign 128 5880.L_op_mul_float_2addr: /* 0xc8 */ 5881/* File: mips64/op_mul_float_2addr.S */ 5882/* File: mips64/fbinop2addr.S */ 5883 /*: 5884 * Generic 32-bit "/2addr" floating-point operation. 5885 * 5886 * For: add-float/2addr, sub-float/2addr, mul-float/2addr, div-float/2addr. 5887 * form: <op> f0, f0, f1 5888 */ 5889 /* binop/2addr vA, vB */ 5890 ext a2, rINST, 8, 4 # a2 <- A 5891 ext a3, rINST, 12, 4 # a3 <- B 5892 GET_VREG_FLOAT f0, a2 # f0 <- vA 5893 GET_VREG_FLOAT f1, a3 # f1 <- vB 5894 mul.s f0, f0, f1 # f0 <- f0 op f1 5895 FETCH_ADVANCE_INST 1 # advance rPC, load rINST 5896 GET_INST_OPCODE v0 # extract opcode from rINST 5897 SET_VREG_FLOAT f0, a2 # vA <- f0 5898 GOTO_OPCODE v0 # jump to next instruction 5899 5900 5901/* ------------------------------ */ 5902 .balign 128 5903.L_op_div_float_2addr: /* 0xc9 */ 5904/* File: mips64/op_div_float_2addr.S */ 5905/* File: mips64/fbinop2addr.S */ 5906 /*: 5907 * Generic 32-bit "/2addr" floating-point operation. 5908 * 5909 * For: add-float/2addr, sub-float/2addr, mul-float/2addr, div-float/2addr. 5910 * form: <op> f0, f0, f1 5911 */ 5912 /* binop/2addr vA, vB */ 5913 ext a2, rINST, 8, 4 # a2 <- A 5914 ext a3, rINST, 12, 4 # a3 <- B 5915 GET_VREG_FLOAT f0, a2 # f0 <- vA 5916 GET_VREG_FLOAT f1, a3 # f1 <- vB 5917 div.s f0, f0, f1 # f0 <- f0 op f1 5918 FETCH_ADVANCE_INST 1 # advance rPC, load rINST 5919 GET_INST_OPCODE v0 # extract opcode from rINST 5920 SET_VREG_FLOAT f0, a2 # vA <- f0 5921 GOTO_OPCODE v0 # jump to next instruction 5922 5923 5924/* ------------------------------ */ 5925 .balign 128 5926.L_op_rem_float_2addr: /* 0xca */ 5927/* File: mips64/op_rem_float_2addr.S */ 5928 /* rem-float/2addr vA, vB */ 5929 .extern fmodf 5930 ext a2, rINST, 8, 4 # a2 <- A 5931 ext a3, rINST, 12, 4 # a3 <- B 5932 GET_VREG_FLOAT f12, a2 # f12 <- vA 5933 GET_VREG_FLOAT f13, a3 # f13 <- vB 5934 jal fmodf # f0 <- f12 op f13 5935 ext a2, rINST, 8, 4 # a2 <- A 5936 FETCH_ADVANCE_INST 1 # advance rPC, load rINST 5937 GET_INST_OPCODE v0 # extract opcode from rINST 5938 SET_VREG_FLOAT f0, a2 # vA <- f0 5939 GOTO_OPCODE v0 # jump to next instruction 5940 5941/* ------------------------------ */ 5942 .balign 128 5943.L_op_add_double_2addr: /* 0xcb */ 5944/* File: mips64/op_add_double_2addr.S */ 5945/* File: mips64/fbinopWide2addr.S */ 5946 /*: 5947 * Generic 64-bit "/2addr" floating-point operation. 5948 * 5949 * For: add-double/2addr, sub-double/2addr, mul-double/2addr, div-double/2addr. 5950 * form: <op> f0, f0, f1 5951 */ 5952 /* binop/2addr vA, vB */ 5953 ext a2, rINST, 8, 4 # a2 <- A 5954 ext a3, rINST, 12, 4 # a3 <- B 5955 GET_VREG_DOUBLE f0, a2 # f0 <- vA 5956 GET_VREG_DOUBLE f1, a3 # f1 <- vB 5957 add.d f0, f0, f1 # f0 <- f0 op f1 5958 FETCH_ADVANCE_INST 1 # advance rPC, load rINST 5959 GET_INST_OPCODE v0 # extract opcode from rINST 5960 SET_VREG_DOUBLE f0, a2 # vA <- f0 5961 GOTO_OPCODE v0 # jump to next instruction 5962 5963 5964/* ------------------------------ */ 5965 .balign 128 5966.L_op_sub_double_2addr: /* 0xcc */ 5967/* File: mips64/op_sub_double_2addr.S */ 5968/* File: mips64/fbinopWide2addr.S */ 5969 /*: 5970 * Generic 64-bit "/2addr" floating-point operation. 5971 * 5972 * For: add-double/2addr, sub-double/2addr, mul-double/2addr, div-double/2addr. 5973 * form: <op> f0, f0, f1 5974 */ 5975 /* binop/2addr vA, vB */ 5976 ext a2, rINST, 8, 4 # a2 <- A 5977 ext a3, rINST, 12, 4 # a3 <- B 5978 GET_VREG_DOUBLE f0, a2 # f0 <- vA 5979 GET_VREG_DOUBLE f1, a3 # f1 <- vB 5980 sub.d f0, f0, f1 # f0 <- f0 op f1 5981 FETCH_ADVANCE_INST 1 # advance rPC, load rINST 5982 GET_INST_OPCODE v0 # extract opcode from rINST 5983 SET_VREG_DOUBLE f0, a2 # vA <- f0 5984 GOTO_OPCODE v0 # jump to next instruction 5985 5986 5987/* ------------------------------ */ 5988 .balign 128 5989.L_op_mul_double_2addr: /* 0xcd */ 5990/* File: mips64/op_mul_double_2addr.S */ 5991/* File: mips64/fbinopWide2addr.S */ 5992 /*: 5993 * Generic 64-bit "/2addr" floating-point operation. 5994 * 5995 * For: add-double/2addr, sub-double/2addr, mul-double/2addr, div-double/2addr. 5996 * form: <op> f0, f0, f1 5997 */ 5998 /* binop/2addr vA, vB */ 5999 ext a2, rINST, 8, 4 # a2 <- A 6000 ext a3, rINST, 12, 4 # a3 <- B 6001 GET_VREG_DOUBLE f0, a2 # f0 <- vA 6002 GET_VREG_DOUBLE f1, a3 # f1 <- vB 6003 mul.d f0, f0, f1 # f0 <- f0 op f1 6004 FETCH_ADVANCE_INST 1 # advance rPC, load rINST 6005 GET_INST_OPCODE v0 # extract opcode from rINST 6006 SET_VREG_DOUBLE f0, a2 # vA <- f0 6007 GOTO_OPCODE v0 # jump to next instruction 6008 6009 6010/* ------------------------------ */ 6011 .balign 128 6012.L_op_div_double_2addr: /* 0xce */ 6013/* File: mips64/op_div_double_2addr.S */ 6014/* File: mips64/fbinopWide2addr.S */ 6015 /*: 6016 * Generic 64-bit "/2addr" floating-point operation. 6017 * 6018 * For: add-double/2addr, sub-double/2addr, mul-double/2addr, div-double/2addr. 6019 * form: <op> f0, f0, f1 6020 */ 6021 /* binop/2addr vA, vB */ 6022 ext a2, rINST, 8, 4 # a2 <- A 6023 ext a3, rINST, 12, 4 # a3 <- B 6024 GET_VREG_DOUBLE f0, a2 # f0 <- vA 6025 GET_VREG_DOUBLE f1, a3 # f1 <- vB 6026 div.d f0, f0, f1 # f0 <- f0 op f1 6027 FETCH_ADVANCE_INST 1 # advance rPC, load rINST 6028 GET_INST_OPCODE v0 # extract opcode from rINST 6029 SET_VREG_DOUBLE f0, a2 # vA <- f0 6030 GOTO_OPCODE v0 # jump to next instruction 6031 6032 6033/* ------------------------------ */ 6034 .balign 128 6035.L_op_rem_double_2addr: /* 0xcf */ 6036/* File: mips64/op_rem_double_2addr.S */ 6037 /* rem-double/2addr vA, vB */ 6038 .extern fmod 6039 ext a2, rINST, 8, 4 # a2 <- A 6040 ext a3, rINST, 12, 4 # a3 <- B 6041 GET_VREG_DOUBLE f12, a2 # f12 <- vA 6042 GET_VREG_DOUBLE f13, a3 # f13 <- vB 6043 jal fmod # f0 <- f12 op f13 6044 ext a2, rINST, 8, 4 # a2 <- A 6045 FETCH_ADVANCE_INST 1 # advance rPC, load rINST 6046 GET_INST_OPCODE v0 # extract opcode from rINST 6047 SET_VREG_DOUBLE f0, a2 # vA <- f0 6048 GOTO_OPCODE v0 # jump to next instruction 6049 6050/* ------------------------------ */ 6051 .balign 128 6052.L_op_add_int_lit16: /* 0xd0 */ 6053/* File: mips64/op_add_int_lit16.S */ 6054/* File: mips64/binopLit16.S */ 6055 /* 6056 * Generic 32-bit "lit16" binary operation. Provide an "instr" line 6057 * that specifies an instruction that performs "result = a0 op a1". 6058 * This could be an MIPS instruction or a function call. (If the result 6059 * comes back in a register other than a0, you can override "result".) 6060 * 6061 * If "chkzero" is set to 1, we perform a divide-by-zero check on 6062 * CCCC (a1). Useful for integer division and modulus. 6063 * 6064 * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16, 6065 * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16 6066 */ 6067 /* binop/lit16 vA, vB, #+CCCC */ 6068 lh a1, 2(rPC) # a1 <- sign-extended CCCC 6069 ext a2, rINST, 8, 4 # a2 <- A 6070 ext a3, rINST, 12, 4 # a3 <- B 6071 GET_VREG a0, a3 # a0 <- vB 6072 .if 0 6073 beqz a1, common_errDivideByZero # is second operand zero? 6074 .endif 6075 FETCH_ADVANCE_INST 2 # advance rPC, load rINST 6076 # optional op 6077 addu a0, a0, a1 # a0 <- op, a0-a3 changed 6078 GET_INST_OPCODE v0 # extract opcode from rINST 6079 SET_VREG a0, a2 # vA <- a0 6080 GOTO_OPCODE v0 # jump to next instruction 6081 6082 6083 6084/* ------------------------------ */ 6085 .balign 128 6086.L_op_rsub_int: /* 0xd1 */ 6087/* File: mips64/op_rsub_int.S */ 6088/* File: mips64/binopLit16.S */ 6089 /* 6090 * Generic 32-bit "lit16" binary operation. Provide an "instr" line 6091 * that specifies an instruction that performs "result = a0 op a1". 6092 * This could be an MIPS instruction or a function call. (If the result 6093 * comes back in a register other than a0, you can override "result".) 6094 * 6095 * If "chkzero" is set to 1, we perform a divide-by-zero check on 6096 * CCCC (a1). Useful for integer division and modulus. 6097 * 6098 * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16, 6099 * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16 6100 */ 6101 /* binop/lit16 vA, vB, #+CCCC */ 6102 lh a1, 2(rPC) # a1 <- sign-extended CCCC 6103 ext a2, rINST, 8, 4 # a2 <- A 6104 ext a3, rINST, 12, 4 # a3 <- B 6105 GET_VREG a0, a3 # a0 <- vB 6106 .if 0 6107 beqz a1, common_errDivideByZero # is second operand zero? 6108 .endif 6109 FETCH_ADVANCE_INST 2 # advance rPC, load rINST 6110 # optional op 6111 subu a0, a1, a0 # a0 <- op, a0-a3 changed 6112 GET_INST_OPCODE v0 # extract opcode from rINST 6113 SET_VREG a0, a2 # vA <- a0 6114 GOTO_OPCODE v0 # jump to next instruction 6115 6116 6117 6118/* ------------------------------ */ 6119 .balign 128 6120.L_op_mul_int_lit16: /* 0xd2 */ 6121/* File: mips64/op_mul_int_lit16.S */ 6122/* File: mips64/binopLit16.S */ 6123 /* 6124 * Generic 32-bit "lit16" binary operation. Provide an "instr" line 6125 * that specifies an instruction that performs "result = a0 op a1". 6126 * This could be an MIPS instruction or a function call. (If the result 6127 * comes back in a register other than a0, you can override "result".) 6128 * 6129 * If "chkzero" is set to 1, we perform a divide-by-zero check on 6130 * CCCC (a1). Useful for integer division and modulus. 6131 * 6132 * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16, 6133 * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16 6134 */ 6135 /* binop/lit16 vA, vB, #+CCCC */ 6136 lh a1, 2(rPC) # a1 <- sign-extended CCCC 6137 ext a2, rINST, 8, 4 # a2 <- A 6138 ext a3, rINST, 12, 4 # a3 <- B 6139 GET_VREG a0, a3 # a0 <- vB 6140 .if 0 6141 beqz a1, common_errDivideByZero # is second operand zero? 6142 .endif 6143 FETCH_ADVANCE_INST 2 # advance rPC, load rINST 6144 # optional op 6145 mul a0, a0, a1 # a0 <- op, a0-a3 changed 6146 GET_INST_OPCODE v0 # extract opcode from rINST 6147 SET_VREG a0, a2 # vA <- a0 6148 GOTO_OPCODE v0 # jump to next instruction 6149 6150 6151 6152/* ------------------------------ */ 6153 .balign 128 6154.L_op_div_int_lit16: /* 0xd3 */ 6155/* File: mips64/op_div_int_lit16.S */ 6156/* File: mips64/binopLit16.S */ 6157 /* 6158 * Generic 32-bit "lit16" binary operation. Provide an "instr" line 6159 * that specifies an instruction that performs "result = a0 op a1". 6160 * This could be an MIPS instruction or a function call. (If the result 6161 * comes back in a register other than a0, you can override "result".) 6162 * 6163 * If "chkzero" is set to 1, we perform a divide-by-zero check on 6164 * CCCC (a1). Useful for integer division and modulus. 6165 * 6166 * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16, 6167 * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16 6168 */ 6169 /* binop/lit16 vA, vB, #+CCCC */ 6170 lh a1, 2(rPC) # a1 <- sign-extended CCCC 6171 ext a2, rINST, 8, 4 # a2 <- A 6172 ext a3, rINST, 12, 4 # a3 <- B 6173 GET_VREG a0, a3 # a0 <- vB 6174 .if 1 6175 beqz a1, common_errDivideByZero # is second operand zero? 6176 .endif 6177 FETCH_ADVANCE_INST 2 # advance rPC, load rINST 6178 # optional op 6179 div a0, a0, a1 # a0 <- op, a0-a3 changed 6180 GET_INST_OPCODE v0 # extract opcode from rINST 6181 SET_VREG a0, a2 # vA <- a0 6182 GOTO_OPCODE v0 # jump to next instruction 6183 6184 6185 6186/* ------------------------------ */ 6187 .balign 128 6188.L_op_rem_int_lit16: /* 0xd4 */ 6189/* File: mips64/op_rem_int_lit16.S */ 6190/* File: mips64/binopLit16.S */ 6191 /* 6192 * Generic 32-bit "lit16" binary operation. Provide an "instr" line 6193 * that specifies an instruction that performs "result = a0 op a1". 6194 * This could be an MIPS instruction or a function call. (If the result 6195 * comes back in a register other than a0, you can override "result".) 6196 * 6197 * If "chkzero" is set to 1, we perform a divide-by-zero check on 6198 * CCCC (a1). Useful for integer division and modulus. 6199 * 6200 * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16, 6201 * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16 6202 */ 6203 /* binop/lit16 vA, vB, #+CCCC */ 6204 lh a1, 2(rPC) # a1 <- sign-extended CCCC 6205 ext a2, rINST, 8, 4 # a2 <- A 6206 ext a3, rINST, 12, 4 # a3 <- B 6207 GET_VREG a0, a3 # a0 <- vB 6208 .if 1 6209 beqz a1, common_errDivideByZero # is second operand zero? 6210 .endif 6211 FETCH_ADVANCE_INST 2 # advance rPC, load rINST 6212 # optional op 6213 mod a0, a0, a1 # a0 <- op, a0-a3 changed 6214 GET_INST_OPCODE v0 # extract opcode from rINST 6215 SET_VREG a0, a2 # vA <- a0 6216 GOTO_OPCODE v0 # jump to next instruction 6217 6218 6219 6220/* ------------------------------ */ 6221 .balign 128 6222.L_op_and_int_lit16: /* 0xd5 */ 6223/* File: mips64/op_and_int_lit16.S */ 6224/* File: mips64/binopLit16.S */ 6225 /* 6226 * Generic 32-bit "lit16" binary operation. Provide an "instr" line 6227 * that specifies an instruction that performs "result = a0 op a1". 6228 * This could be an MIPS instruction or a function call. (If the result 6229 * comes back in a register other than a0, you can override "result".) 6230 * 6231 * If "chkzero" is set to 1, we perform a divide-by-zero check on 6232 * CCCC (a1). Useful for integer division and modulus. 6233 * 6234 * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16, 6235 * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16 6236 */ 6237 /* binop/lit16 vA, vB, #+CCCC */ 6238 lh a1, 2(rPC) # a1 <- sign-extended CCCC 6239 ext a2, rINST, 8, 4 # a2 <- A 6240 ext a3, rINST, 12, 4 # a3 <- B 6241 GET_VREG a0, a3 # a0 <- vB 6242 .if 0 6243 beqz a1, common_errDivideByZero # is second operand zero? 6244 .endif 6245 FETCH_ADVANCE_INST 2 # advance rPC, load rINST 6246 # optional op 6247 and a0, a0, a1 # a0 <- op, a0-a3 changed 6248 GET_INST_OPCODE v0 # extract opcode from rINST 6249 SET_VREG a0, a2 # vA <- a0 6250 GOTO_OPCODE v0 # jump to next instruction 6251 6252 6253 6254/* ------------------------------ */ 6255 .balign 128 6256.L_op_or_int_lit16: /* 0xd6 */ 6257/* File: mips64/op_or_int_lit16.S */ 6258/* File: mips64/binopLit16.S */ 6259 /* 6260 * Generic 32-bit "lit16" binary operation. Provide an "instr" line 6261 * that specifies an instruction that performs "result = a0 op a1". 6262 * This could be an MIPS instruction or a function call. (If the result 6263 * comes back in a register other than a0, you can override "result".) 6264 * 6265 * If "chkzero" is set to 1, we perform a divide-by-zero check on 6266 * CCCC (a1). Useful for integer division and modulus. 6267 * 6268 * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16, 6269 * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16 6270 */ 6271 /* binop/lit16 vA, vB, #+CCCC */ 6272 lh a1, 2(rPC) # a1 <- sign-extended CCCC 6273 ext a2, rINST, 8, 4 # a2 <- A 6274 ext a3, rINST, 12, 4 # a3 <- B 6275 GET_VREG a0, a3 # a0 <- vB 6276 .if 0 6277 beqz a1, common_errDivideByZero # is second operand zero? 6278 .endif 6279 FETCH_ADVANCE_INST 2 # advance rPC, load rINST 6280 # optional op 6281 or a0, a0, a1 # a0 <- op, a0-a3 changed 6282 GET_INST_OPCODE v0 # extract opcode from rINST 6283 SET_VREG a0, a2 # vA <- a0 6284 GOTO_OPCODE v0 # jump to next instruction 6285 6286 6287 6288/* ------------------------------ */ 6289 .balign 128 6290.L_op_xor_int_lit16: /* 0xd7 */ 6291/* File: mips64/op_xor_int_lit16.S */ 6292/* File: mips64/binopLit16.S */ 6293 /* 6294 * Generic 32-bit "lit16" binary operation. Provide an "instr" line 6295 * that specifies an instruction that performs "result = a0 op a1". 6296 * This could be an MIPS instruction or a function call. (If the result 6297 * comes back in a register other than a0, you can override "result".) 6298 * 6299 * If "chkzero" is set to 1, we perform a divide-by-zero check on 6300 * CCCC (a1). Useful for integer division and modulus. 6301 * 6302 * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16, 6303 * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16 6304 */ 6305 /* binop/lit16 vA, vB, #+CCCC */ 6306 lh a1, 2(rPC) # a1 <- sign-extended CCCC 6307 ext a2, rINST, 8, 4 # a2 <- A 6308 ext a3, rINST, 12, 4 # a3 <- B 6309 GET_VREG a0, a3 # a0 <- vB 6310 .if 0 6311 beqz a1, common_errDivideByZero # is second operand zero? 6312 .endif 6313 FETCH_ADVANCE_INST 2 # advance rPC, load rINST 6314 # optional op 6315 xor a0, a0, a1 # a0 <- op, a0-a3 changed 6316 GET_INST_OPCODE v0 # extract opcode from rINST 6317 SET_VREG a0, a2 # vA <- a0 6318 GOTO_OPCODE v0 # jump to next instruction 6319 6320 6321 6322/* ------------------------------ */ 6323 .balign 128 6324.L_op_add_int_lit8: /* 0xd8 */ 6325/* File: mips64/op_add_int_lit8.S */ 6326/* File: mips64/binopLit8.S */ 6327 /* 6328 * Generic 32-bit "lit8" binary operation. Provide an "instr" line 6329 * that specifies an instruction that performs "result = a0 op a1". 6330 * This could be an MIPS instruction or a function call. (If the result 6331 * comes back in a register other than a0, you can override "result".) 6332 * 6333 * If "chkzero" is set to 1, we perform a divide-by-zero check on 6334 * CC (a1). Useful for integer division and modulus. 6335 * 6336 * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, 6337 * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, 6338 * shl-int/lit8, shr-int/lit8, ushr-int/lit8 6339 */ 6340 /* binop/lit8 vAA, vBB, #+CC */ 6341 lbu a3, 2(rPC) # a3 <- BB 6342 lb a1, 3(rPC) # a1 <- sign-extended CC 6343 srl a2, rINST, 8 # a2 <- AA 6344 GET_VREG a0, a3 # a0 <- vBB 6345 .if 0 6346 beqz a1, common_errDivideByZero # is second operand zero? 6347 .endif 6348 FETCH_ADVANCE_INST 2 # advance rPC, load rINST 6349 # optional op 6350 addu a0, a0, a1 # a0 <- op, a0-a3 changed 6351 GET_INST_OPCODE v0 # extract opcode from rINST 6352 SET_VREG a0, a2 # vAA <- a0 6353 GOTO_OPCODE v0 # jump to next instruction 6354 6355 6356 6357/* ------------------------------ */ 6358 .balign 128 6359.L_op_rsub_int_lit8: /* 0xd9 */ 6360/* File: mips64/op_rsub_int_lit8.S */ 6361/* File: mips64/binopLit8.S */ 6362 /* 6363 * Generic 32-bit "lit8" binary operation. Provide an "instr" line 6364 * that specifies an instruction that performs "result = a0 op a1". 6365 * This could be an MIPS instruction or a function call. (If the result 6366 * comes back in a register other than a0, you can override "result".) 6367 * 6368 * If "chkzero" is set to 1, we perform a divide-by-zero check on 6369 * CC (a1). Useful for integer division and modulus. 6370 * 6371 * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, 6372 * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, 6373 * shl-int/lit8, shr-int/lit8, ushr-int/lit8 6374 */ 6375 /* binop/lit8 vAA, vBB, #+CC */ 6376 lbu a3, 2(rPC) # a3 <- BB 6377 lb a1, 3(rPC) # a1 <- sign-extended CC 6378 srl a2, rINST, 8 # a2 <- AA 6379 GET_VREG a0, a3 # a0 <- vBB 6380 .if 0 6381 beqz a1, common_errDivideByZero # is second operand zero? 6382 .endif 6383 FETCH_ADVANCE_INST 2 # advance rPC, load rINST 6384 # optional op 6385 subu a0, a1, a0 # a0 <- op, a0-a3 changed 6386 GET_INST_OPCODE v0 # extract opcode from rINST 6387 SET_VREG a0, a2 # vAA <- a0 6388 GOTO_OPCODE v0 # jump to next instruction 6389 6390 6391 6392/* ------------------------------ */ 6393 .balign 128 6394.L_op_mul_int_lit8: /* 0xda */ 6395/* File: mips64/op_mul_int_lit8.S */ 6396/* File: mips64/binopLit8.S */ 6397 /* 6398 * Generic 32-bit "lit8" binary operation. Provide an "instr" line 6399 * that specifies an instruction that performs "result = a0 op a1". 6400 * This could be an MIPS instruction or a function call. (If the result 6401 * comes back in a register other than a0, you can override "result".) 6402 * 6403 * If "chkzero" is set to 1, we perform a divide-by-zero check on 6404 * CC (a1). Useful for integer division and modulus. 6405 * 6406 * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, 6407 * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, 6408 * shl-int/lit8, shr-int/lit8, ushr-int/lit8 6409 */ 6410 /* binop/lit8 vAA, vBB, #+CC */ 6411 lbu a3, 2(rPC) # a3 <- BB 6412 lb a1, 3(rPC) # a1 <- sign-extended CC 6413 srl a2, rINST, 8 # a2 <- AA 6414 GET_VREG a0, a3 # a0 <- vBB 6415 .if 0 6416 beqz a1, common_errDivideByZero # is second operand zero? 6417 .endif 6418 FETCH_ADVANCE_INST 2 # advance rPC, load rINST 6419 # optional op 6420 mul a0, a0, a1 # a0 <- op, a0-a3 changed 6421 GET_INST_OPCODE v0 # extract opcode from rINST 6422 SET_VREG a0, a2 # vAA <- a0 6423 GOTO_OPCODE v0 # jump to next instruction 6424 6425 6426 6427/* ------------------------------ */ 6428 .balign 128 6429.L_op_div_int_lit8: /* 0xdb */ 6430/* File: mips64/op_div_int_lit8.S */ 6431/* File: mips64/binopLit8.S */ 6432 /* 6433 * Generic 32-bit "lit8" binary operation. Provide an "instr" line 6434 * that specifies an instruction that performs "result = a0 op a1". 6435 * This could be an MIPS instruction or a function call. (If the result 6436 * comes back in a register other than a0, you can override "result".) 6437 * 6438 * If "chkzero" is set to 1, we perform a divide-by-zero check on 6439 * CC (a1). Useful for integer division and modulus. 6440 * 6441 * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, 6442 * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, 6443 * shl-int/lit8, shr-int/lit8, ushr-int/lit8 6444 */ 6445 /* binop/lit8 vAA, vBB, #+CC */ 6446 lbu a3, 2(rPC) # a3 <- BB 6447 lb a1, 3(rPC) # a1 <- sign-extended CC 6448 srl a2, rINST, 8 # a2 <- AA 6449 GET_VREG a0, a3 # a0 <- vBB 6450 .if 1 6451 beqz a1, common_errDivideByZero # is second operand zero? 6452 .endif 6453 FETCH_ADVANCE_INST 2 # advance rPC, load rINST 6454 # optional op 6455 div a0, a0, a1 # a0 <- op, a0-a3 changed 6456 GET_INST_OPCODE v0 # extract opcode from rINST 6457 SET_VREG a0, a2 # vAA <- a0 6458 GOTO_OPCODE v0 # jump to next instruction 6459 6460 6461 6462/* ------------------------------ */ 6463 .balign 128 6464.L_op_rem_int_lit8: /* 0xdc */ 6465/* File: mips64/op_rem_int_lit8.S */ 6466/* File: mips64/binopLit8.S */ 6467 /* 6468 * Generic 32-bit "lit8" binary operation. Provide an "instr" line 6469 * that specifies an instruction that performs "result = a0 op a1". 6470 * This could be an MIPS instruction or a function call. (If the result 6471 * comes back in a register other than a0, you can override "result".) 6472 * 6473 * If "chkzero" is set to 1, we perform a divide-by-zero check on 6474 * CC (a1). Useful for integer division and modulus. 6475 * 6476 * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, 6477 * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, 6478 * shl-int/lit8, shr-int/lit8, ushr-int/lit8 6479 */ 6480 /* binop/lit8 vAA, vBB, #+CC */ 6481 lbu a3, 2(rPC) # a3 <- BB 6482 lb a1, 3(rPC) # a1 <- sign-extended CC 6483 srl a2, rINST, 8 # a2 <- AA 6484 GET_VREG a0, a3 # a0 <- vBB 6485 .if 1 6486 beqz a1, common_errDivideByZero # is second operand zero? 6487 .endif 6488 FETCH_ADVANCE_INST 2 # advance rPC, load rINST 6489 # optional op 6490 mod a0, a0, a1 # a0 <- op, a0-a3 changed 6491 GET_INST_OPCODE v0 # extract opcode from rINST 6492 SET_VREG a0, a2 # vAA <- a0 6493 GOTO_OPCODE v0 # jump to next instruction 6494 6495 6496 6497/* ------------------------------ */ 6498 .balign 128 6499.L_op_and_int_lit8: /* 0xdd */ 6500/* File: mips64/op_and_int_lit8.S */ 6501/* File: mips64/binopLit8.S */ 6502 /* 6503 * Generic 32-bit "lit8" binary operation. Provide an "instr" line 6504 * that specifies an instruction that performs "result = a0 op a1". 6505 * This could be an MIPS instruction or a function call. (If the result 6506 * comes back in a register other than a0, you can override "result".) 6507 * 6508 * If "chkzero" is set to 1, we perform a divide-by-zero check on 6509 * CC (a1). Useful for integer division and modulus. 6510 * 6511 * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, 6512 * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, 6513 * shl-int/lit8, shr-int/lit8, ushr-int/lit8 6514 */ 6515 /* binop/lit8 vAA, vBB, #+CC */ 6516 lbu a3, 2(rPC) # a3 <- BB 6517 lb a1, 3(rPC) # a1 <- sign-extended CC 6518 srl a2, rINST, 8 # a2 <- AA 6519 GET_VREG a0, a3 # a0 <- vBB 6520 .if 0 6521 beqz a1, common_errDivideByZero # is second operand zero? 6522 .endif 6523 FETCH_ADVANCE_INST 2 # advance rPC, load rINST 6524 # optional op 6525 and a0, a0, a1 # a0 <- op, a0-a3 changed 6526 GET_INST_OPCODE v0 # extract opcode from rINST 6527 SET_VREG a0, a2 # vAA <- a0 6528 GOTO_OPCODE v0 # jump to next instruction 6529 6530 6531 6532/* ------------------------------ */ 6533 .balign 128 6534.L_op_or_int_lit8: /* 0xde */ 6535/* File: mips64/op_or_int_lit8.S */ 6536/* File: mips64/binopLit8.S */ 6537 /* 6538 * Generic 32-bit "lit8" binary operation. Provide an "instr" line 6539 * that specifies an instruction that performs "result = a0 op a1". 6540 * This could be an MIPS instruction or a function call. (If the result 6541 * comes back in a register other than a0, you can override "result".) 6542 * 6543 * If "chkzero" is set to 1, we perform a divide-by-zero check on 6544 * CC (a1). Useful for integer division and modulus. 6545 * 6546 * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, 6547 * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, 6548 * shl-int/lit8, shr-int/lit8, ushr-int/lit8 6549 */ 6550 /* binop/lit8 vAA, vBB, #+CC */ 6551 lbu a3, 2(rPC) # a3 <- BB 6552 lb a1, 3(rPC) # a1 <- sign-extended CC 6553 srl a2, rINST, 8 # a2 <- AA 6554 GET_VREG a0, a3 # a0 <- vBB 6555 .if 0 6556 beqz a1, common_errDivideByZero # is second operand zero? 6557 .endif 6558 FETCH_ADVANCE_INST 2 # advance rPC, load rINST 6559 # optional op 6560 or a0, a0, a1 # a0 <- op, a0-a3 changed 6561 GET_INST_OPCODE v0 # extract opcode from rINST 6562 SET_VREG a0, a2 # vAA <- a0 6563 GOTO_OPCODE v0 # jump to next instruction 6564 6565 6566 6567/* ------------------------------ */ 6568 .balign 128 6569.L_op_xor_int_lit8: /* 0xdf */ 6570/* File: mips64/op_xor_int_lit8.S */ 6571/* File: mips64/binopLit8.S */ 6572 /* 6573 * Generic 32-bit "lit8" binary operation. Provide an "instr" line 6574 * that specifies an instruction that performs "result = a0 op a1". 6575 * This could be an MIPS instruction or a function call. (If the result 6576 * comes back in a register other than a0, you can override "result".) 6577 * 6578 * If "chkzero" is set to 1, we perform a divide-by-zero check on 6579 * CC (a1). Useful for integer division and modulus. 6580 * 6581 * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, 6582 * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, 6583 * shl-int/lit8, shr-int/lit8, ushr-int/lit8 6584 */ 6585 /* binop/lit8 vAA, vBB, #+CC */ 6586 lbu a3, 2(rPC) # a3 <- BB 6587 lb a1, 3(rPC) # a1 <- sign-extended CC 6588 srl a2, rINST, 8 # a2 <- AA 6589 GET_VREG a0, a3 # a0 <- vBB 6590 .if 0 6591 beqz a1, common_errDivideByZero # is second operand zero? 6592 .endif 6593 FETCH_ADVANCE_INST 2 # advance rPC, load rINST 6594 # optional op 6595 xor a0, a0, a1 # a0 <- op, a0-a3 changed 6596 GET_INST_OPCODE v0 # extract opcode from rINST 6597 SET_VREG a0, a2 # vAA <- a0 6598 GOTO_OPCODE v0 # jump to next instruction 6599 6600 6601 6602/* ------------------------------ */ 6603 .balign 128 6604.L_op_shl_int_lit8: /* 0xe0 */ 6605/* File: mips64/op_shl_int_lit8.S */ 6606/* File: mips64/binopLit8.S */ 6607 /* 6608 * Generic 32-bit "lit8" binary operation. Provide an "instr" line 6609 * that specifies an instruction that performs "result = a0 op a1". 6610 * This could be an MIPS instruction or a function call. (If the result 6611 * comes back in a register other than a0, you can override "result".) 6612 * 6613 * If "chkzero" is set to 1, we perform a divide-by-zero check on 6614 * CC (a1). Useful for integer division and modulus. 6615 * 6616 * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, 6617 * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, 6618 * shl-int/lit8, shr-int/lit8, ushr-int/lit8 6619 */ 6620 /* binop/lit8 vAA, vBB, #+CC */ 6621 lbu a3, 2(rPC) # a3 <- BB 6622 lb a1, 3(rPC) # a1 <- sign-extended CC 6623 srl a2, rINST, 8 # a2 <- AA 6624 GET_VREG a0, a3 # a0 <- vBB 6625 .if 0 6626 beqz a1, common_errDivideByZero # is second operand zero? 6627 .endif 6628 FETCH_ADVANCE_INST 2 # advance rPC, load rINST 6629 # optional op 6630 sll a0, a0, a1 # a0 <- op, a0-a3 changed 6631 GET_INST_OPCODE v0 # extract opcode from rINST 6632 SET_VREG a0, a2 # vAA <- a0 6633 GOTO_OPCODE v0 # jump to next instruction 6634 6635 6636 6637/* ------------------------------ */ 6638 .balign 128 6639.L_op_shr_int_lit8: /* 0xe1 */ 6640/* File: mips64/op_shr_int_lit8.S */ 6641/* File: mips64/binopLit8.S */ 6642 /* 6643 * Generic 32-bit "lit8" binary operation. Provide an "instr" line 6644 * that specifies an instruction that performs "result = a0 op a1". 6645 * This could be an MIPS instruction or a function call. (If the result 6646 * comes back in a register other than a0, you can override "result".) 6647 * 6648 * If "chkzero" is set to 1, we perform a divide-by-zero check on 6649 * CC (a1). Useful for integer division and modulus. 6650 * 6651 * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, 6652 * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, 6653 * shl-int/lit8, shr-int/lit8, ushr-int/lit8 6654 */ 6655 /* binop/lit8 vAA, vBB, #+CC */ 6656 lbu a3, 2(rPC) # a3 <- BB 6657 lb a1, 3(rPC) # a1 <- sign-extended CC 6658 srl a2, rINST, 8 # a2 <- AA 6659 GET_VREG a0, a3 # a0 <- vBB 6660 .if 0 6661 beqz a1, common_errDivideByZero # is second operand zero? 6662 .endif 6663 FETCH_ADVANCE_INST 2 # advance rPC, load rINST 6664 # optional op 6665 sra a0, a0, a1 # a0 <- op, a0-a3 changed 6666 GET_INST_OPCODE v0 # extract opcode from rINST 6667 SET_VREG a0, a2 # vAA <- a0 6668 GOTO_OPCODE v0 # jump to next instruction 6669 6670 6671 6672/* ------------------------------ */ 6673 .balign 128 6674.L_op_ushr_int_lit8: /* 0xe2 */ 6675/* File: mips64/op_ushr_int_lit8.S */ 6676/* File: mips64/binopLit8.S */ 6677 /* 6678 * Generic 32-bit "lit8" binary operation. Provide an "instr" line 6679 * that specifies an instruction that performs "result = a0 op a1". 6680 * This could be an MIPS instruction or a function call. (If the result 6681 * comes back in a register other than a0, you can override "result".) 6682 * 6683 * If "chkzero" is set to 1, we perform a divide-by-zero check on 6684 * CC (a1). Useful for integer division and modulus. 6685 * 6686 * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, 6687 * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, 6688 * shl-int/lit8, shr-int/lit8, ushr-int/lit8 6689 */ 6690 /* binop/lit8 vAA, vBB, #+CC */ 6691 lbu a3, 2(rPC) # a3 <- BB 6692 lb a1, 3(rPC) # a1 <- sign-extended CC 6693 srl a2, rINST, 8 # a2 <- AA 6694 GET_VREG a0, a3 # a0 <- vBB 6695 .if 0 6696 beqz a1, common_errDivideByZero # is second operand zero? 6697 .endif 6698 FETCH_ADVANCE_INST 2 # advance rPC, load rINST 6699 # optional op 6700 srl a0, a0, a1 # a0 <- op, a0-a3 changed 6701 GET_INST_OPCODE v0 # extract opcode from rINST 6702 SET_VREG a0, a2 # vAA <- a0 6703 GOTO_OPCODE v0 # jump to next instruction 6704 6705 6706 6707/* ------------------------------ */ 6708 .balign 128 6709.L_op_iget_quick: /* 0xe3 */ 6710/* File: mips64/op_iget_quick.S */ 6711 /* For: iget-quick, iget-boolean-quick, iget-byte-quick, iget-char-quick, iget-short-quick */ 6712 /* op vA, vB, offset//CCCC */ 6713 srl a2, rINST, 12 # a2 <- B 6714 lhu a1, 2(rPC) # a1 <- field byte offset 6715 GET_VREG_U a3, a2 # a3 <- object we're operating on 6716 ext a4, rINST, 8, 4 # a4 <- A 6717 daddu a1, a1, a3 6718 beqz a3, common_errNullObject # object was null 6719 lw a0, 0(a1) # a0 <- obj.field 6720 FETCH_ADVANCE_INST 2 # advance rPC, load rINST 6721 SET_VREG a0, a4 # fp[A] <- a0 6722 GET_INST_OPCODE v0 # extract opcode from rINST 6723 GOTO_OPCODE v0 # jump to next instruction 6724 6725/* ------------------------------ */ 6726 .balign 128 6727.L_op_iget_wide_quick: /* 0xe4 */ 6728/* File: mips64/op_iget_wide_quick.S */ 6729 /* iget-wide-quick vA, vB, offset//CCCC */ 6730 srl a2, rINST, 12 # a2 <- B 6731 lhu a4, 2(rPC) # a4 <- field byte offset 6732 GET_VREG_U a3, a2 # a3 <- object we're operating on 6733 ext a2, rINST, 8, 4 # a2 <- A 6734 beqz a3, common_errNullObject # object was null 6735 daddu a4, a3, a4 # create direct pointer 6736 lw a0, 0(a4) 6737 lw a1, 4(a4) 6738 dinsu a0, a1, 32, 32 6739 FETCH_ADVANCE_INST 2 # advance rPC, load rINST 6740 SET_VREG_WIDE a0, a2 6741 GET_INST_OPCODE v0 # extract opcode from rINST 6742 GOTO_OPCODE v0 # jump to next instruction 6743 6744/* ------------------------------ */ 6745 .balign 128 6746.L_op_iget_object_quick: /* 0xe5 */ 6747/* File: mips64/op_iget_object_quick.S */ 6748 /* For: iget-object-quick */ 6749 /* op vA, vB, offset//CCCC */ 6750 .extern artIGetObjectFromMterp 6751 srl a2, rINST, 12 # a2 <- B 6752 lhu a1, 2(rPC) # a1 <- field byte offset 6753 EXPORT_PC 6754 GET_VREG_U a0, a2 # a0 <- object we're operating on 6755 jal artIGetObjectFromMterp # (obj, offset) 6756 ld a3, THREAD_EXCEPTION_OFFSET(rSELF) 6757 ext a2, rINST, 8, 4 # a2 <- A 6758 PREFETCH_INST 2 6759 bnez a3, MterpPossibleException # bail out 6760 SET_VREG_OBJECT v0, a2 # fp[A] <- v0 6761 ADVANCE 2 # advance rPC 6762 GET_INST_OPCODE v0 # extract opcode from rINST 6763 GOTO_OPCODE v0 # jump to next instruction 6764 6765/* ------------------------------ */ 6766 .balign 128 6767.L_op_iput_quick: /* 0xe6 */ 6768/* File: mips64/op_iput_quick.S */ 6769 /* For: iput-quick, iput-boolean-quick, iput-byte-quick, iput-char-quick, iput-short-quick */ 6770 /* op vA, vB, offset//CCCC */ 6771 srl a2, rINST, 12 # a2 <- B 6772 lhu a1, 2(rPC) # a1 <- field byte offset 6773 GET_VREG_U a3, a2 # a3 <- fp[B], the object pointer 6774 ext a2, rINST, 8, 4 # a2 <- A 6775 beqz a3, common_errNullObject # object was null 6776 GET_VREG a0, a2 # a0 <- fp[A] 6777 FETCH_ADVANCE_INST 2 # advance rPC, load rINST 6778 daddu a1, a1, a3 6779 sw a0, 0(a1) # obj.field <- a0 6780 GET_INST_OPCODE v0 # extract opcode from rINST 6781 GOTO_OPCODE v0 # jump to next instruction 6782 6783/* ------------------------------ */ 6784 .balign 128 6785.L_op_iput_wide_quick: /* 0xe7 */ 6786/* File: mips64/op_iput_wide_quick.S */ 6787 /* iput-wide-quick vA, vB, offset//CCCC */ 6788 srl a2, rINST, 12 # a2 <- B 6789 lhu a3, 2(rPC) # a3 <- field byte offset 6790 GET_VREG_U a2, a2 # a2 <- fp[B], the object pointer 6791 ext a0, rINST, 8, 4 # a0 <- A 6792 beqz a2, common_errNullObject # object was null 6793 GET_VREG_WIDE a0, a0 # a0 <- fp[A] 6794 FETCH_ADVANCE_INST 2 # advance rPC, load rINST 6795 daddu a1, a2, a3 # create a direct pointer 6796 sw a0, 0(a1) 6797 dsrl32 a0, a0, 0 6798 sw a0, 4(a1) 6799 GET_INST_OPCODE v0 # extract opcode from rINST 6800 GOTO_OPCODE v0 # jump to next instruction 6801 6802/* ------------------------------ */ 6803 .balign 128 6804.L_op_iput_object_quick: /* 0xe8 */ 6805/* File: mips64/op_iput_object_quick.S */ 6806 .extern MterpIputObjectQuick 6807 EXPORT_PC 6808 daddu a0, rFP, OFF_FP_SHADOWFRAME 6809 move a1, rPC 6810 move a2, rINST 6811 jal MterpIputObjectQuick 6812 beqzc v0, MterpException 6813 FETCH_ADVANCE_INST 2 # advance rPC, load rINST 6814 GET_INST_OPCODE v0 # extract opcode from rINST 6815 GOTO_OPCODE v0 # jump to next instruction 6816 6817/* ------------------------------ */ 6818 .balign 128 6819.L_op_invoke_virtual_quick: /* 0xe9 */ 6820/* File: mips64/op_invoke_virtual_quick.S */ 6821/* File: mips64/invoke.S */ 6822 /* 6823 * Generic invoke handler wrapper. 6824 */ 6825 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 6826 /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 6827 .extern MterpInvokeVirtualQuick 6828 .extern MterpShouldSwitchInterpreters 6829 EXPORT_PC 6830 move a0, rSELF 6831 daddu a1, rFP, OFF_FP_SHADOWFRAME 6832 move a2, rPC 6833 move a3, rINST 6834 jal MterpInvokeVirtualQuick 6835 beqzc v0, MterpException 6836 FETCH_ADVANCE_INST 3 6837 jal MterpShouldSwitchInterpreters 6838 bnezc v0, MterpFallback 6839 GET_INST_OPCODE v0 6840 GOTO_OPCODE v0 6841 6842 6843/* ------------------------------ */ 6844 .balign 128 6845.L_op_invoke_virtual_range_quick: /* 0xea */ 6846/* File: mips64/op_invoke_virtual_range_quick.S */ 6847/* File: mips64/invoke.S */ 6848 /* 6849 * Generic invoke handler wrapper. 6850 */ 6851 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 6852 /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 6853 .extern MterpInvokeVirtualQuickRange 6854 .extern MterpShouldSwitchInterpreters 6855 EXPORT_PC 6856 move a0, rSELF 6857 daddu a1, rFP, OFF_FP_SHADOWFRAME 6858 move a2, rPC 6859 move a3, rINST 6860 jal MterpInvokeVirtualQuickRange 6861 beqzc v0, MterpException 6862 FETCH_ADVANCE_INST 3 6863 jal MterpShouldSwitchInterpreters 6864 bnezc v0, MterpFallback 6865 GET_INST_OPCODE v0 6866 GOTO_OPCODE v0 6867 6868 6869/* ------------------------------ */ 6870 .balign 128 6871.L_op_iput_boolean_quick: /* 0xeb */ 6872/* File: mips64/op_iput_boolean_quick.S */ 6873/* File: mips64/op_iput_quick.S */ 6874 /* For: iput-quick, iput-boolean-quick, iput-byte-quick, iput-char-quick, iput-short-quick */ 6875 /* op vA, vB, offset//CCCC */ 6876 srl a2, rINST, 12 # a2 <- B 6877 lhu a1, 2(rPC) # a1 <- field byte offset 6878 GET_VREG_U a3, a2 # a3 <- fp[B], the object pointer 6879 ext a2, rINST, 8, 4 # a2 <- A 6880 beqz a3, common_errNullObject # object was null 6881 GET_VREG a0, a2 # a0 <- fp[A] 6882 FETCH_ADVANCE_INST 2 # advance rPC, load rINST 6883 daddu a1, a1, a3 6884 sb a0, 0(a1) # obj.field <- a0 6885 GET_INST_OPCODE v0 # extract opcode from rINST 6886 GOTO_OPCODE v0 # jump to next instruction 6887 6888 6889/* ------------------------------ */ 6890 .balign 128 6891.L_op_iput_byte_quick: /* 0xec */ 6892/* File: mips64/op_iput_byte_quick.S */ 6893/* File: mips64/op_iput_quick.S */ 6894 /* For: iput-quick, iput-boolean-quick, iput-byte-quick, iput-char-quick, iput-short-quick */ 6895 /* op vA, vB, offset//CCCC */ 6896 srl a2, rINST, 12 # a2 <- B 6897 lhu a1, 2(rPC) # a1 <- field byte offset 6898 GET_VREG_U a3, a2 # a3 <- fp[B], the object pointer 6899 ext a2, rINST, 8, 4 # a2 <- A 6900 beqz a3, common_errNullObject # object was null 6901 GET_VREG a0, a2 # a0 <- fp[A] 6902 FETCH_ADVANCE_INST 2 # advance rPC, load rINST 6903 daddu a1, a1, a3 6904 sb a0, 0(a1) # obj.field <- a0 6905 GET_INST_OPCODE v0 # extract opcode from rINST 6906 GOTO_OPCODE v0 # jump to next instruction 6907 6908 6909/* ------------------------------ */ 6910 .balign 128 6911.L_op_iput_char_quick: /* 0xed */ 6912/* File: mips64/op_iput_char_quick.S */ 6913/* File: mips64/op_iput_quick.S */ 6914 /* For: iput-quick, iput-boolean-quick, iput-byte-quick, iput-char-quick, iput-short-quick */ 6915 /* op vA, vB, offset//CCCC */ 6916 srl a2, rINST, 12 # a2 <- B 6917 lhu a1, 2(rPC) # a1 <- field byte offset 6918 GET_VREG_U a3, a2 # a3 <- fp[B], the object pointer 6919 ext a2, rINST, 8, 4 # a2 <- A 6920 beqz a3, common_errNullObject # object was null 6921 GET_VREG a0, a2 # a0 <- fp[A] 6922 FETCH_ADVANCE_INST 2 # advance rPC, load rINST 6923 daddu a1, a1, a3 6924 sh a0, 0(a1) # obj.field <- a0 6925 GET_INST_OPCODE v0 # extract opcode from rINST 6926 GOTO_OPCODE v0 # jump to next instruction 6927 6928 6929/* ------------------------------ */ 6930 .balign 128 6931.L_op_iput_short_quick: /* 0xee */ 6932/* File: mips64/op_iput_short_quick.S */ 6933/* File: mips64/op_iput_quick.S */ 6934 /* For: iput-quick, iput-boolean-quick, iput-byte-quick, iput-char-quick, iput-short-quick */ 6935 /* op vA, vB, offset//CCCC */ 6936 srl a2, rINST, 12 # a2 <- B 6937 lhu a1, 2(rPC) # a1 <- field byte offset 6938 GET_VREG_U a3, a2 # a3 <- fp[B], the object pointer 6939 ext a2, rINST, 8, 4 # a2 <- A 6940 beqz a3, common_errNullObject # object was null 6941 GET_VREG a0, a2 # a0 <- fp[A] 6942 FETCH_ADVANCE_INST 2 # advance rPC, load rINST 6943 daddu a1, a1, a3 6944 sh a0, 0(a1) # obj.field <- a0 6945 GET_INST_OPCODE v0 # extract opcode from rINST 6946 GOTO_OPCODE v0 # jump to next instruction 6947 6948 6949/* ------------------------------ */ 6950 .balign 128 6951.L_op_iget_boolean_quick: /* 0xef */ 6952/* File: mips64/op_iget_boolean_quick.S */ 6953/* File: mips64/op_iget_quick.S */ 6954 /* For: iget-quick, iget-boolean-quick, iget-byte-quick, iget-char-quick, iget-short-quick */ 6955 /* op vA, vB, offset//CCCC */ 6956 srl a2, rINST, 12 # a2 <- B 6957 lhu a1, 2(rPC) # a1 <- field byte offset 6958 GET_VREG_U a3, a2 # a3 <- object we're operating on 6959 ext a4, rINST, 8, 4 # a4 <- A 6960 daddu a1, a1, a3 6961 beqz a3, common_errNullObject # object was null 6962 lbu a0, 0(a1) # a0 <- obj.field 6963 FETCH_ADVANCE_INST 2 # advance rPC, load rINST 6964 SET_VREG a0, a4 # fp[A] <- a0 6965 GET_INST_OPCODE v0 # extract opcode from rINST 6966 GOTO_OPCODE v0 # jump to next instruction 6967 6968 6969/* ------------------------------ */ 6970 .balign 128 6971.L_op_iget_byte_quick: /* 0xf0 */ 6972/* File: mips64/op_iget_byte_quick.S */ 6973/* File: mips64/op_iget_quick.S */ 6974 /* For: iget-quick, iget-boolean-quick, iget-byte-quick, iget-char-quick, iget-short-quick */ 6975 /* op vA, vB, offset//CCCC */ 6976 srl a2, rINST, 12 # a2 <- B 6977 lhu a1, 2(rPC) # a1 <- field byte offset 6978 GET_VREG_U a3, a2 # a3 <- object we're operating on 6979 ext a4, rINST, 8, 4 # a4 <- A 6980 daddu a1, a1, a3 6981 beqz a3, common_errNullObject # object was null 6982 lb a0, 0(a1) # a0 <- obj.field 6983 FETCH_ADVANCE_INST 2 # advance rPC, load rINST 6984 SET_VREG a0, a4 # fp[A] <- a0 6985 GET_INST_OPCODE v0 # extract opcode from rINST 6986 GOTO_OPCODE v0 # jump to next instruction 6987 6988 6989/* ------------------------------ */ 6990 .balign 128 6991.L_op_iget_char_quick: /* 0xf1 */ 6992/* File: mips64/op_iget_char_quick.S */ 6993/* File: mips64/op_iget_quick.S */ 6994 /* For: iget-quick, iget-boolean-quick, iget-byte-quick, iget-char-quick, iget-short-quick */ 6995 /* op vA, vB, offset//CCCC */ 6996 srl a2, rINST, 12 # a2 <- B 6997 lhu a1, 2(rPC) # a1 <- field byte offset 6998 GET_VREG_U a3, a2 # a3 <- object we're operating on 6999 ext a4, rINST, 8, 4 # a4 <- A 7000 daddu a1, a1, a3 7001 beqz a3, common_errNullObject # object was null 7002 lhu a0, 0(a1) # a0 <- obj.field 7003 FETCH_ADVANCE_INST 2 # advance rPC, load rINST 7004 SET_VREG a0, a4 # fp[A] <- a0 7005 GET_INST_OPCODE v0 # extract opcode from rINST 7006 GOTO_OPCODE v0 # jump to next instruction 7007 7008 7009/* ------------------------------ */ 7010 .balign 128 7011.L_op_iget_short_quick: /* 0xf2 */ 7012/* File: mips64/op_iget_short_quick.S */ 7013/* File: mips64/op_iget_quick.S */ 7014 /* For: iget-quick, iget-boolean-quick, iget-byte-quick, iget-char-quick, iget-short-quick */ 7015 /* op vA, vB, offset//CCCC */ 7016 srl a2, rINST, 12 # a2 <- B 7017 lhu a1, 2(rPC) # a1 <- field byte offset 7018 GET_VREG_U a3, a2 # a3 <- object we're operating on 7019 ext a4, rINST, 8, 4 # a4 <- A 7020 daddu a1, a1, a3 7021 beqz a3, common_errNullObject # object was null 7022 lh a0, 0(a1) # a0 <- obj.field 7023 FETCH_ADVANCE_INST 2 # advance rPC, load rINST 7024 SET_VREG a0, a4 # fp[A] <- a0 7025 GET_INST_OPCODE v0 # extract opcode from rINST 7026 GOTO_OPCODE v0 # jump to next instruction 7027 7028 7029/* ------------------------------ */ 7030 .balign 128 7031.L_op_unused_f3: /* 0xf3 */ 7032/* File: mips64/op_unused_f3.S */ 7033/* File: mips64/unused.S */ 7034/* 7035 * Bail to reference interpreter to throw. 7036 */ 7037 b MterpFallback 7038 7039 7040/* ------------------------------ */ 7041 .balign 128 7042.L_op_unused_f4: /* 0xf4 */ 7043/* File: mips64/op_unused_f4.S */ 7044/* File: mips64/unused.S */ 7045/* 7046 * Bail to reference interpreter to throw. 7047 */ 7048 b MterpFallback 7049 7050 7051/* ------------------------------ */ 7052 .balign 128 7053.L_op_unused_f5: /* 0xf5 */ 7054/* File: mips64/op_unused_f5.S */ 7055/* File: mips64/unused.S */ 7056/* 7057 * Bail to reference interpreter to throw. 7058 */ 7059 b MterpFallback 7060 7061 7062/* ------------------------------ */ 7063 .balign 128 7064.L_op_unused_f6: /* 0xf6 */ 7065/* File: mips64/op_unused_f6.S */ 7066/* File: mips64/unused.S */ 7067/* 7068 * Bail to reference interpreter to throw. 7069 */ 7070 b MterpFallback 7071 7072 7073/* ------------------------------ */ 7074 .balign 128 7075.L_op_unused_f7: /* 0xf7 */ 7076/* File: mips64/op_unused_f7.S */ 7077/* File: mips64/unused.S */ 7078/* 7079 * Bail to reference interpreter to throw. 7080 */ 7081 b MterpFallback 7082 7083 7084/* ------------------------------ */ 7085 .balign 128 7086.L_op_unused_f8: /* 0xf8 */ 7087/* File: mips64/op_unused_f8.S */ 7088/* File: mips64/unused.S */ 7089/* 7090 * Bail to reference interpreter to throw. 7091 */ 7092 b MterpFallback 7093 7094 7095/* ------------------------------ */ 7096 .balign 128 7097.L_op_unused_f9: /* 0xf9 */ 7098/* File: mips64/op_unused_f9.S */ 7099/* File: mips64/unused.S */ 7100/* 7101 * Bail to reference interpreter to throw. 7102 */ 7103 b MterpFallback 7104 7105 7106/* ------------------------------ */ 7107 .balign 128 7108.L_op_invoke_polymorphic: /* 0xfa */ 7109/* Transfer stub to alternate interpreter */ 7110 b MterpFallback 7111 7112/* ------------------------------ */ 7113 .balign 128 7114.L_op_invoke_polymorphic_range: /* 0xfb */ 7115/* Transfer stub to alternate interpreter */ 7116 b MterpFallback 7117 7118/* ------------------------------ */ 7119 .balign 128 7120.L_op_invoke_custom: /* 0xfc */ 7121/* Transfer stub to alternate interpreter */ 7122 b MterpFallback 7123 7124/* ------------------------------ */ 7125 .balign 128 7126.L_op_invoke_custom_range: /* 0xfd */ 7127/* Transfer stub to alternate interpreter */ 7128 b MterpFallback 7129 7130/* ------------------------------ */ 7131 .balign 128 7132.L_op_unused_fe: /* 0xfe */ 7133/* File: mips64/op_unused_fe.S */ 7134/* File: mips64/unused.S */ 7135/* 7136 * Bail to reference interpreter to throw. 7137 */ 7138 b MterpFallback 7139 7140 7141/* ------------------------------ */ 7142 .balign 128 7143.L_op_unused_ff: /* 0xff */ 7144/* File: mips64/op_unused_ff.S */ 7145/* File: mips64/unused.S */ 7146/* 7147 * Bail to reference interpreter to throw. 7148 */ 7149 b MterpFallback 7150 7151 7152 .balign 128 7153 .size artMterpAsmInstructionStart, .-artMterpAsmInstructionStart 7154 .global artMterpAsmInstructionEnd 7155artMterpAsmInstructionEnd: 7156 7157/* 7158 * =========================================================================== 7159 * Sister implementations 7160 * =========================================================================== 7161 */ 7162 .global artMterpAsmSisterStart 7163 .type artMterpAsmSisterStart, %function 7164 .text 7165 .balign 4 7166artMterpAsmSisterStart: 7167 7168 .size artMterpAsmSisterStart, .-artMterpAsmSisterStart 7169 .global artMterpAsmSisterEnd 7170artMterpAsmSisterEnd: 7171 7172 7173 .global artMterpAsmAltInstructionStart 7174 .type artMterpAsmAltInstructionStart, %function 7175 .text 7176 7177artMterpAsmAltInstructionStart = .L_ALT_op_nop 7178/* ------------------------------ */ 7179 .balign 128 7180.L_ALT_op_nop: /* 0x00 */ 7181/* File: mips64/alt_stub.S */ 7182/* 7183 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 7184 * any interesting requests and then jump to the real instruction 7185 * handler. Note that the call to MterpCheckBefore is done as a tail call. 7186 */ 7187 .extern MterpCheckBefore 7188 REFRESH_IBASE 7189 dla ra, artMterpAsmInstructionStart 7190 dla t9, MterpCheckBefore 7191 move a0, rSELF 7192 daddu a1, rFP, OFF_FP_SHADOWFRAME 7193 move a2, rPC 7194 daddu ra, ra, (0 * 128) # Addr of primary handler. 7195 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 7196 7197/* ------------------------------ */ 7198 .balign 128 7199.L_ALT_op_move: /* 0x01 */ 7200/* File: mips64/alt_stub.S */ 7201/* 7202 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 7203 * any interesting requests and then jump to the real instruction 7204 * handler. Note that the call to MterpCheckBefore is done as a tail call. 7205 */ 7206 .extern MterpCheckBefore 7207 REFRESH_IBASE 7208 dla ra, artMterpAsmInstructionStart 7209 dla t9, MterpCheckBefore 7210 move a0, rSELF 7211 daddu a1, rFP, OFF_FP_SHADOWFRAME 7212 move a2, rPC 7213 daddu ra, ra, (1 * 128) # Addr of primary handler. 7214 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 7215 7216/* ------------------------------ */ 7217 .balign 128 7218.L_ALT_op_move_from16: /* 0x02 */ 7219/* File: mips64/alt_stub.S */ 7220/* 7221 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 7222 * any interesting requests and then jump to the real instruction 7223 * handler. Note that the call to MterpCheckBefore is done as a tail call. 7224 */ 7225 .extern MterpCheckBefore 7226 REFRESH_IBASE 7227 dla ra, artMterpAsmInstructionStart 7228 dla t9, MterpCheckBefore 7229 move a0, rSELF 7230 daddu a1, rFP, OFF_FP_SHADOWFRAME 7231 move a2, rPC 7232 daddu ra, ra, (2 * 128) # Addr of primary handler. 7233 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 7234 7235/* ------------------------------ */ 7236 .balign 128 7237.L_ALT_op_move_16: /* 0x03 */ 7238/* File: mips64/alt_stub.S */ 7239/* 7240 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 7241 * any interesting requests and then jump to the real instruction 7242 * handler. Note that the call to MterpCheckBefore is done as a tail call. 7243 */ 7244 .extern MterpCheckBefore 7245 REFRESH_IBASE 7246 dla ra, artMterpAsmInstructionStart 7247 dla t9, MterpCheckBefore 7248 move a0, rSELF 7249 daddu a1, rFP, OFF_FP_SHADOWFRAME 7250 move a2, rPC 7251 daddu ra, ra, (3 * 128) # Addr of primary handler. 7252 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 7253 7254/* ------------------------------ */ 7255 .balign 128 7256.L_ALT_op_move_wide: /* 0x04 */ 7257/* File: mips64/alt_stub.S */ 7258/* 7259 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 7260 * any interesting requests and then jump to the real instruction 7261 * handler. Note that the call to MterpCheckBefore is done as a tail call. 7262 */ 7263 .extern MterpCheckBefore 7264 REFRESH_IBASE 7265 dla ra, artMterpAsmInstructionStart 7266 dla t9, MterpCheckBefore 7267 move a0, rSELF 7268 daddu a1, rFP, OFF_FP_SHADOWFRAME 7269 move a2, rPC 7270 daddu ra, ra, (4 * 128) # Addr of primary handler. 7271 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 7272 7273/* ------------------------------ */ 7274 .balign 128 7275.L_ALT_op_move_wide_from16: /* 0x05 */ 7276/* File: mips64/alt_stub.S */ 7277/* 7278 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 7279 * any interesting requests and then jump to the real instruction 7280 * handler. Note that the call to MterpCheckBefore is done as a tail call. 7281 */ 7282 .extern MterpCheckBefore 7283 REFRESH_IBASE 7284 dla ra, artMterpAsmInstructionStart 7285 dla t9, MterpCheckBefore 7286 move a0, rSELF 7287 daddu a1, rFP, OFF_FP_SHADOWFRAME 7288 move a2, rPC 7289 daddu ra, ra, (5 * 128) # Addr of primary handler. 7290 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 7291 7292/* ------------------------------ */ 7293 .balign 128 7294.L_ALT_op_move_wide_16: /* 0x06 */ 7295/* File: mips64/alt_stub.S */ 7296/* 7297 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 7298 * any interesting requests and then jump to the real instruction 7299 * handler. Note that the call to MterpCheckBefore is done as a tail call. 7300 */ 7301 .extern MterpCheckBefore 7302 REFRESH_IBASE 7303 dla ra, artMterpAsmInstructionStart 7304 dla t9, MterpCheckBefore 7305 move a0, rSELF 7306 daddu a1, rFP, OFF_FP_SHADOWFRAME 7307 move a2, rPC 7308 daddu ra, ra, (6 * 128) # Addr of primary handler. 7309 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 7310 7311/* ------------------------------ */ 7312 .balign 128 7313.L_ALT_op_move_object: /* 0x07 */ 7314/* File: mips64/alt_stub.S */ 7315/* 7316 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 7317 * any interesting requests and then jump to the real instruction 7318 * handler. Note that the call to MterpCheckBefore is done as a tail call. 7319 */ 7320 .extern MterpCheckBefore 7321 REFRESH_IBASE 7322 dla ra, artMterpAsmInstructionStart 7323 dla t9, MterpCheckBefore 7324 move a0, rSELF 7325 daddu a1, rFP, OFF_FP_SHADOWFRAME 7326 move a2, rPC 7327 daddu ra, ra, (7 * 128) # Addr of primary handler. 7328 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 7329 7330/* ------------------------------ */ 7331 .balign 128 7332.L_ALT_op_move_object_from16: /* 0x08 */ 7333/* File: mips64/alt_stub.S */ 7334/* 7335 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 7336 * any interesting requests and then jump to the real instruction 7337 * handler. Note that the call to MterpCheckBefore is done as a tail call. 7338 */ 7339 .extern MterpCheckBefore 7340 REFRESH_IBASE 7341 dla ra, artMterpAsmInstructionStart 7342 dla t9, MterpCheckBefore 7343 move a0, rSELF 7344 daddu a1, rFP, OFF_FP_SHADOWFRAME 7345 move a2, rPC 7346 daddu ra, ra, (8 * 128) # Addr of primary handler. 7347 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 7348 7349/* ------------------------------ */ 7350 .balign 128 7351.L_ALT_op_move_object_16: /* 0x09 */ 7352/* File: mips64/alt_stub.S */ 7353/* 7354 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 7355 * any interesting requests and then jump to the real instruction 7356 * handler. Note that the call to MterpCheckBefore is done as a tail call. 7357 */ 7358 .extern MterpCheckBefore 7359 REFRESH_IBASE 7360 dla ra, artMterpAsmInstructionStart 7361 dla t9, MterpCheckBefore 7362 move a0, rSELF 7363 daddu a1, rFP, OFF_FP_SHADOWFRAME 7364 move a2, rPC 7365 daddu ra, ra, (9 * 128) # Addr of primary handler. 7366 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 7367 7368/* ------------------------------ */ 7369 .balign 128 7370.L_ALT_op_move_result: /* 0x0a */ 7371/* File: mips64/alt_stub.S */ 7372/* 7373 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 7374 * any interesting requests and then jump to the real instruction 7375 * handler. Note that the call to MterpCheckBefore is done as a tail call. 7376 */ 7377 .extern MterpCheckBefore 7378 REFRESH_IBASE 7379 dla ra, artMterpAsmInstructionStart 7380 dla t9, MterpCheckBefore 7381 move a0, rSELF 7382 daddu a1, rFP, OFF_FP_SHADOWFRAME 7383 move a2, rPC 7384 daddu ra, ra, (10 * 128) # Addr of primary handler. 7385 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 7386 7387/* ------------------------------ */ 7388 .balign 128 7389.L_ALT_op_move_result_wide: /* 0x0b */ 7390/* File: mips64/alt_stub.S */ 7391/* 7392 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 7393 * any interesting requests and then jump to the real instruction 7394 * handler. Note that the call to MterpCheckBefore is done as a tail call. 7395 */ 7396 .extern MterpCheckBefore 7397 REFRESH_IBASE 7398 dla ra, artMterpAsmInstructionStart 7399 dla t9, MterpCheckBefore 7400 move a0, rSELF 7401 daddu a1, rFP, OFF_FP_SHADOWFRAME 7402 move a2, rPC 7403 daddu ra, ra, (11 * 128) # Addr of primary handler. 7404 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 7405 7406/* ------------------------------ */ 7407 .balign 128 7408.L_ALT_op_move_result_object: /* 0x0c */ 7409/* File: mips64/alt_stub.S */ 7410/* 7411 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 7412 * any interesting requests and then jump to the real instruction 7413 * handler. Note that the call to MterpCheckBefore is done as a tail call. 7414 */ 7415 .extern MterpCheckBefore 7416 REFRESH_IBASE 7417 dla ra, artMterpAsmInstructionStart 7418 dla t9, MterpCheckBefore 7419 move a0, rSELF 7420 daddu a1, rFP, OFF_FP_SHADOWFRAME 7421 move a2, rPC 7422 daddu ra, ra, (12 * 128) # Addr of primary handler. 7423 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 7424 7425/* ------------------------------ */ 7426 .balign 128 7427.L_ALT_op_move_exception: /* 0x0d */ 7428/* File: mips64/alt_stub.S */ 7429/* 7430 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 7431 * any interesting requests and then jump to the real instruction 7432 * handler. Note that the call to MterpCheckBefore is done as a tail call. 7433 */ 7434 .extern MterpCheckBefore 7435 REFRESH_IBASE 7436 dla ra, artMterpAsmInstructionStart 7437 dla t9, MterpCheckBefore 7438 move a0, rSELF 7439 daddu a1, rFP, OFF_FP_SHADOWFRAME 7440 move a2, rPC 7441 daddu ra, ra, (13 * 128) # Addr of primary handler. 7442 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 7443 7444/* ------------------------------ */ 7445 .balign 128 7446.L_ALT_op_return_void: /* 0x0e */ 7447/* File: mips64/alt_stub.S */ 7448/* 7449 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 7450 * any interesting requests and then jump to the real instruction 7451 * handler. Note that the call to MterpCheckBefore is done as a tail call. 7452 */ 7453 .extern MterpCheckBefore 7454 REFRESH_IBASE 7455 dla ra, artMterpAsmInstructionStart 7456 dla t9, MterpCheckBefore 7457 move a0, rSELF 7458 daddu a1, rFP, OFF_FP_SHADOWFRAME 7459 move a2, rPC 7460 daddu ra, ra, (14 * 128) # Addr of primary handler. 7461 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 7462 7463/* ------------------------------ */ 7464 .balign 128 7465.L_ALT_op_return: /* 0x0f */ 7466/* File: mips64/alt_stub.S */ 7467/* 7468 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 7469 * any interesting requests and then jump to the real instruction 7470 * handler. Note that the call to MterpCheckBefore is done as a tail call. 7471 */ 7472 .extern MterpCheckBefore 7473 REFRESH_IBASE 7474 dla ra, artMterpAsmInstructionStart 7475 dla t9, MterpCheckBefore 7476 move a0, rSELF 7477 daddu a1, rFP, OFF_FP_SHADOWFRAME 7478 move a2, rPC 7479 daddu ra, ra, (15 * 128) # Addr of primary handler. 7480 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 7481 7482/* ------------------------------ */ 7483 .balign 128 7484.L_ALT_op_return_wide: /* 0x10 */ 7485/* File: mips64/alt_stub.S */ 7486/* 7487 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 7488 * any interesting requests and then jump to the real instruction 7489 * handler. Note that the call to MterpCheckBefore is done as a tail call. 7490 */ 7491 .extern MterpCheckBefore 7492 REFRESH_IBASE 7493 dla ra, artMterpAsmInstructionStart 7494 dla t9, MterpCheckBefore 7495 move a0, rSELF 7496 daddu a1, rFP, OFF_FP_SHADOWFRAME 7497 move a2, rPC 7498 daddu ra, ra, (16 * 128) # Addr of primary handler. 7499 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 7500 7501/* ------------------------------ */ 7502 .balign 128 7503.L_ALT_op_return_object: /* 0x11 */ 7504/* File: mips64/alt_stub.S */ 7505/* 7506 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 7507 * any interesting requests and then jump to the real instruction 7508 * handler. Note that the call to MterpCheckBefore is done as a tail call. 7509 */ 7510 .extern MterpCheckBefore 7511 REFRESH_IBASE 7512 dla ra, artMterpAsmInstructionStart 7513 dla t9, MterpCheckBefore 7514 move a0, rSELF 7515 daddu a1, rFP, OFF_FP_SHADOWFRAME 7516 move a2, rPC 7517 daddu ra, ra, (17 * 128) # Addr of primary handler. 7518 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 7519 7520/* ------------------------------ */ 7521 .balign 128 7522.L_ALT_op_const_4: /* 0x12 */ 7523/* File: mips64/alt_stub.S */ 7524/* 7525 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 7526 * any interesting requests and then jump to the real instruction 7527 * handler. Note that the call to MterpCheckBefore is done as a tail call. 7528 */ 7529 .extern MterpCheckBefore 7530 REFRESH_IBASE 7531 dla ra, artMterpAsmInstructionStart 7532 dla t9, MterpCheckBefore 7533 move a0, rSELF 7534 daddu a1, rFP, OFF_FP_SHADOWFRAME 7535 move a2, rPC 7536 daddu ra, ra, (18 * 128) # Addr of primary handler. 7537 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 7538 7539/* ------------------------------ */ 7540 .balign 128 7541.L_ALT_op_const_16: /* 0x13 */ 7542/* File: mips64/alt_stub.S */ 7543/* 7544 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 7545 * any interesting requests and then jump to the real instruction 7546 * handler. Note that the call to MterpCheckBefore is done as a tail call. 7547 */ 7548 .extern MterpCheckBefore 7549 REFRESH_IBASE 7550 dla ra, artMterpAsmInstructionStart 7551 dla t9, MterpCheckBefore 7552 move a0, rSELF 7553 daddu a1, rFP, OFF_FP_SHADOWFRAME 7554 move a2, rPC 7555 daddu ra, ra, (19 * 128) # Addr of primary handler. 7556 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 7557 7558/* ------------------------------ */ 7559 .balign 128 7560.L_ALT_op_const: /* 0x14 */ 7561/* File: mips64/alt_stub.S */ 7562/* 7563 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 7564 * any interesting requests and then jump to the real instruction 7565 * handler. Note that the call to MterpCheckBefore is done as a tail call. 7566 */ 7567 .extern MterpCheckBefore 7568 REFRESH_IBASE 7569 dla ra, artMterpAsmInstructionStart 7570 dla t9, MterpCheckBefore 7571 move a0, rSELF 7572 daddu a1, rFP, OFF_FP_SHADOWFRAME 7573 move a2, rPC 7574 daddu ra, ra, (20 * 128) # Addr of primary handler. 7575 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 7576 7577/* ------------------------------ */ 7578 .balign 128 7579.L_ALT_op_const_high16: /* 0x15 */ 7580/* File: mips64/alt_stub.S */ 7581/* 7582 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 7583 * any interesting requests and then jump to the real instruction 7584 * handler. Note that the call to MterpCheckBefore is done as a tail call. 7585 */ 7586 .extern MterpCheckBefore 7587 REFRESH_IBASE 7588 dla ra, artMterpAsmInstructionStart 7589 dla t9, MterpCheckBefore 7590 move a0, rSELF 7591 daddu a1, rFP, OFF_FP_SHADOWFRAME 7592 move a2, rPC 7593 daddu ra, ra, (21 * 128) # Addr of primary handler. 7594 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 7595 7596/* ------------------------------ */ 7597 .balign 128 7598.L_ALT_op_const_wide_16: /* 0x16 */ 7599/* File: mips64/alt_stub.S */ 7600/* 7601 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 7602 * any interesting requests and then jump to the real instruction 7603 * handler. Note that the call to MterpCheckBefore is done as a tail call. 7604 */ 7605 .extern MterpCheckBefore 7606 REFRESH_IBASE 7607 dla ra, artMterpAsmInstructionStart 7608 dla t9, MterpCheckBefore 7609 move a0, rSELF 7610 daddu a1, rFP, OFF_FP_SHADOWFRAME 7611 move a2, rPC 7612 daddu ra, ra, (22 * 128) # Addr of primary handler. 7613 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 7614 7615/* ------------------------------ */ 7616 .balign 128 7617.L_ALT_op_const_wide_32: /* 0x17 */ 7618/* File: mips64/alt_stub.S */ 7619/* 7620 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 7621 * any interesting requests and then jump to the real instruction 7622 * handler. Note that the call to MterpCheckBefore is done as a tail call. 7623 */ 7624 .extern MterpCheckBefore 7625 REFRESH_IBASE 7626 dla ra, artMterpAsmInstructionStart 7627 dla t9, MterpCheckBefore 7628 move a0, rSELF 7629 daddu a1, rFP, OFF_FP_SHADOWFRAME 7630 move a2, rPC 7631 daddu ra, ra, (23 * 128) # Addr of primary handler. 7632 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 7633 7634/* ------------------------------ */ 7635 .balign 128 7636.L_ALT_op_const_wide: /* 0x18 */ 7637/* File: mips64/alt_stub.S */ 7638/* 7639 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 7640 * any interesting requests and then jump to the real instruction 7641 * handler. Note that the call to MterpCheckBefore is done as a tail call. 7642 */ 7643 .extern MterpCheckBefore 7644 REFRESH_IBASE 7645 dla ra, artMterpAsmInstructionStart 7646 dla t9, MterpCheckBefore 7647 move a0, rSELF 7648 daddu a1, rFP, OFF_FP_SHADOWFRAME 7649 move a2, rPC 7650 daddu ra, ra, (24 * 128) # Addr of primary handler. 7651 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 7652 7653/* ------------------------------ */ 7654 .balign 128 7655.L_ALT_op_const_wide_high16: /* 0x19 */ 7656/* File: mips64/alt_stub.S */ 7657/* 7658 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 7659 * any interesting requests and then jump to the real instruction 7660 * handler. Note that the call to MterpCheckBefore is done as a tail call. 7661 */ 7662 .extern MterpCheckBefore 7663 REFRESH_IBASE 7664 dla ra, artMterpAsmInstructionStart 7665 dla t9, MterpCheckBefore 7666 move a0, rSELF 7667 daddu a1, rFP, OFF_FP_SHADOWFRAME 7668 move a2, rPC 7669 daddu ra, ra, (25 * 128) # Addr of primary handler. 7670 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 7671 7672/* ------------------------------ */ 7673 .balign 128 7674.L_ALT_op_const_string: /* 0x1a */ 7675/* File: mips64/alt_stub.S */ 7676/* 7677 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 7678 * any interesting requests and then jump to the real instruction 7679 * handler. Note that the call to MterpCheckBefore is done as a tail call. 7680 */ 7681 .extern MterpCheckBefore 7682 REFRESH_IBASE 7683 dla ra, artMterpAsmInstructionStart 7684 dla t9, MterpCheckBefore 7685 move a0, rSELF 7686 daddu a1, rFP, OFF_FP_SHADOWFRAME 7687 move a2, rPC 7688 daddu ra, ra, (26 * 128) # Addr of primary handler. 7689 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 7690 7691/* ------------------------------ */ 7692 .balign 128 7693.L_ALT_op_const_string_jumbo: /* 0x1b */ 7694/* File: mips64/alt_stub.S */ 7695/* 7696 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 7697 * any interesting requests and then jump to the real instruction 7698 * handler. Note that the call to MterpCheckBefore is done as a tail call. 7699 */ 7700 .extern MterpCheckBefore 7701 REFRESH_IBASE 7702 dla ra, artMterpAsmInstructionStart 7703 dla t9, MterpCheckBefore 7704 move a0, rSELF 7705 daddu a1, rFP, OFF_FP_SHADOWFRAME 7706 move a2, rPC 7707 daddu ra, ra, (27 * 128) # Addr of primary handler. 7708 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 7709 7710/* ------------------------------ */ 7711 .balign 128 7712.L_ALT_op_const_class: /* 0x1c */ 7713/* File: mips64/alt_stub.S */ 7714/* 7715 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 7716 * any interesting requests and then jump to the real instruction 7717 * handler. Note that the call to MterpCheckBefore is done as a tail call. 7718 */ 7719 .extern MterpCheckBefore 7720 REFRESH_IBASE 7721 dla ra, artMterpAsmInstructionStart 7722 dla t9, MterpCheckBefore 7723 move a0, rSELF 7724 daddu a1, rFP, OFF_FP_SHADOWFRAME 7725 move a2, rPC 7726 daddu ra, ra, (28 * 128) # Addr of primary handler. 7727 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 7728 7729/* ------------------------------ */ 7730 .balign 128 7731.L_ALT_op_monitor_enter: /* 0x1d */ 7732/* File: mips64/alt_stub.S */ 7733/* 7734 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 7735 * any interesting requests and then jump to the real instruction 7736 * handler. Note that the call to MterpCheckBefore is done as a tail call. 7737 */ 7738 .extern MterpCheckBefore 7739 REFRESH_IBASE 7740 dla ra, artMterpAsmInstructionStart 7741 dla t9, MterpCheckBefore 7742 move a0, rSELF 7743 daddu a1, rFP, OFF_FP_SHADOWFRAME 7744 move a2, rPC 7745 daddu ra, ra, (29 * 128) # Addr of primary handler. 7746 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 7747 7748/* ------------------------------ */ 7749 .balign 128 7750.L_ALT_op_monitor_exit: /* 0x1e */ 7751/* File: mips64/alt_stub.S */ 7752/* 7753 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 7754 * any interesting requests and then jump to the real instruction 7755 * handler. Note that the call to MterpCheckBefore is done as a tail call. 7756 */ 7757 .extern MterpCheckBefore 7758 REFRESH_IBASE 7759 dla ra, artMterpAsmInstructionStart 7760 dla t9, MterpCheckBefore 7761 move a0, rSELF 7762 daddu a1, rFP, OFF_FP_SHADOWFRAME 7763 move a2, rPC 7764 daddu ra, ra, (30 * 128) # Addr of primary handler. 7765 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 7766 7767/* ------------------------------ */ 7768 .balign 128 7769.L_ALT_op_check_cast: /* 0x1f */ 7770/* File: mips64/alt_stub.S */ 7771/* 7772 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 7773 * any interesting requests and then jump to the real instruction 7774 * handler. Note that the call to MterpCheckBefore is done as a tail call. 7775 */ 7776 .extern MterpCheckBefore 7777 REFRESH_IBASE 7778 dla ra, artMterpAsmInstructionStart 7779 dla t9, MterpCheckBefore 7780 move a0, rSELF 7781 daddu a1, rFP, OFF_FP_SHADOWFRAME 7782 move a2, rPC 7783 daddu ra, ra, (31 * 128) # Addr of primary handler. 7784 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 7785 7786/* ------------------------------ */ 7787 .balign 128 7788.L_ALT_op_instance_of: /* 0x20 */ 7789/* File: mips64/alt_stub.S */ 7790/* 7791 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 7792 * any interesting requests and then jump to the real instruction 7793 * handler. Note that the call to MterpCheckBefore is done as a tail call. 7794 */ 7795 .extern MterpCheckBefore 7796 REFRESH_IBASE 7797 dla ra, artMterpAsmInstructionStart 7798 dla t9, MterpCheckBefore 7799 move a0, rSELF 7800 daddu a1, rFP, OFF_FP_SHADOWFRAME 7801 move a2, rPC 7802 daddu ra, ra, (32 * 128) # Addr of primary handler. 7803 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 7804 7805/* ------------------------------ */ 7806 .balign 128 7807.L_ALT_op_array_length: /* 0x21 */ 7808/* File: mips64/alt_stub.S */ 7809/* 7810 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 7811 * any interesting requests and then jump to the real instruction 7812 * handler. Note that the call to MterpCheckBefore is done as a tail call. 7813 */ 7814 .extern MterpCheckBefore 7815 REFRESH_IBASE 7816 dla ra, artMterpAsmInstructionStart 7817 dla t9, MterpCheckBefore 7818 move a0, rSELF 7819 daddu a1, rFP, OFF_FP_SHADOWFRAME 7820 move a2, rPC 7821 daddu ra, ra, (33 * 128) # Addr of primary handler. 7822 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 7823 7824/* ------------------------------ */ 7825 .balign 128 7826.L_ALT_op_new_instance: /* 0x22 */ 7827/* File: mips64/alt_stub.S */ 7828/* 7829 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 7830 * any interesting requests and then jump to the real instruction 7831 * handler. Note that the call to MterpCheckBefore is done as a tail call. 7832 */ 7833 .extern MterpCheckBefore 7834 REFRESH_IBASE 7835 dla ra, artMterpAsmInstructionStart 7836 dla t9, MterpCheckBefore 7837 move a0, rSELF 7838 daddu a1, rFP, OFF_FP_SHADOWFRAME 7839 move a2, rPC 7840 daddu ra, ra, (34 * 128) # Addr of primary handler. 7841 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 7842 7843/* ------------------------------ */ 7844 .balign 128 7845.L_ALT_op_new_array: /* 0x23 */ 7846/* File: mips64/alt_stub.S */ 7847/* 7848 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 7849 * any interesting requests and then jump to the real instruction 7850 * handler. Note that the call to MterpCheckBefore is done as a tail call. 7851 */ 7852 .extern MterpCheckBefore 7853 REFRESH_IBASE 7854 dla ra, artMterpAsmInstructionStart 7855 dla t9, MterpCheckBefore 7856 move a0, rSELF 7857 daddu a1, rFP, OFF_FP_SHADOWFRAME 7858 move a2, rPC 7859 daddu ra, ra, (35 * 128) # Addr of primary handler. 7860 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 7861 7862/* ------------------------------ */ 7863 .balign 128 7864.L_ALT_op_filled_new_array: /* 0x24 */ 7865/* File: mips64/alt_stub.S */ 7866/* 7867 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 7868 * any interesting requests and then jump to the real instruction 7869 * handler. Note that the call to MterpCheckBefore is done as a tail call. 7870 */ 7871 .extern MterpCheckBefore 7872 REFRESH_IBASE 7873 dla ra, artMterpAsmInstructionStart 7874 dla t9, MterpCheckBefore 7875 move a0, rSELF 7876 daddu a1, rFP, OFF_FP_SHADOWFRAME 7877 move a2, rPC 7878 daddu ra, ra, (36 * 128) # Addr of primary handler. 7879 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 7880 7881/* ------------------------------ */ 7882 .balign 128 7883.L_ALT_op_filled_new_array_range: /* 0x25 */ 7884/* File: mips64/alt_stub.S */ 7885/* 7886 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 7887 * any interesting requests and then jump to the real instruction 7888 * handler. Note that the call to MterpCheckBefore is done as a tail call. 7889 */ 7890 .extern MterpCheckBefore 7891 REFRESH_IBASE 7892 dla ra, artMterpAsmInstructionStart 7893 dla t9, MterpCheckBefore 7894 move a0, rSELF 7895 daddu a1, rFP, OFF_FP_SHADOWFRAME 7896 move a2, rPC 7897 daddu ra, ra, (37 * 128) # Addr of primary handler. 7898 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 7899 7900/* ------------------------------ */ 7901 .balign 128 7902.L_ALT_op_fill_array_data: /* 0x26 */ 7903/* File: mips64/alt_stub.S */ 7904/* 7905 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 7906 * any interesting requests and then jump to the real instruction 7907 * handler. Note that the call to MterpCheckBefore is done as a tail call. 7908 */ 7909 .extern MterpCheckBefore 7910 REFRESH_IBASE 7911 dla ra, artMterpAsmInstructionStart 7912 dla t9, MterpCheckBefore 7913 move a0, rSELF 7914 daddu a1, rFP, OFF_FP_SHADOWFRAME 7915 move a2, rPC 7916 daddu ra, ra, (38 * 128) # Addr of primary handler. 7917 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 7918 7919/* ------------------------------ */ 7920 .balign 128 7921.L_ALT_op_throw: /* 0x27 */ 7922/* File: mips64/alt_stub.S */ 7923/* 7924 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 7925 * any interesting requests and then jump to the real instruction 7926 * handler. Note that the call to MterpCheckBefore is done as a tail call. 7927 */ 7928 .extern MterpCheckBefore 7929 REFRESH_IBASE 7930 dla ra, artMterpAsmInstructionStart 7931 dla t9, MterpCheckBefore 7932 move a0, rSELF 7933 daddu a1, rFP, OFF_FP_SHADOWFRAME 7934 move a2, rPC 7935 daddu ra, ra, (39 * 128) # Addr of primary handler. 7936 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 7937 7938/* ------------------------------ */ 7939 .balign 128 7940.L_ALT_op_goto: /* 0x28 */ 7941/* File: mips64/alt_stub.S */ 7942/* 7943 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 7944 * any interesting requests and then jump to the real instruction 7945 * handler. Note that the call to MterpCheckBefore is done as a tail call. 7946 */ 7947 .extern MterpCheckBefore 7948 REFRESH_IBASE 7949 dla ra, artMterpAsmInstructionStart 7950 dla t9, MterpCheckBefore 7951 move a0, rSELF 7952 daddu a1, rFP, OFF_FP_SHADOWFRAME 7953 move a2, rPC 7954 daddu ra, ra, (40 * 128) # Addr of primary handler. 7955 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 7956 7957/* ------------------------------ */ 7958 .balign 128 7959.L_ALT_op_goto_16: /* 0x29 */ 7960/* File: mips64/alt_stub.S */ 7961/* 7962 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 7963 * any interesting requests and then jump to the real instruction 7964 * handler. Note that the call to MterpCheckBefore is done as a tail call. 7965 */ 7966 .extern MterpCheckBefore 7967 REFRESH_IBASE 7968 dla ra, artMterpAsmInstructionStart 7969 dla t9, MterpCheckBefore 7970 move a0, rSELF 7971 daddu a1, rFP, OFF_FP_SHADOWFRAME 7972 move a2, rPC 7973 daddu ra, ra, (41 * 128) # Addr of primary handler. 7974 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 7975 7976/* ------------------------------ */ 7977 .balign 128 7978.L_ALT_op_goto_32: /* 0x2a */ 7979/* File: mips64/alt_stub.S */ 7980/* 7981 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 7982 * any interesting requests and then jump to the real instruction 7983 * handler. Note that the call to MterpCheckBefore is done as a tail call. 7984 */ 7985 .extern MterpCheckBefore 7986 REFRESH_IBASE 7987 dla ra, artMterpAsmInstructionStart 7988 dla t9, MterpCheckBefore 7989 move a0, rSELF 7990 daddu a1, rFP, OFF_FP_SHADOWFRAME 7991 move a2, rPC 7992 daddu ra, ra, (42 * 128) # Addr of primary handler. 7993 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 7994 7995/* ------------------------------ */ 7996 .balign 128 7997.L_ALT_op_packed_switch: /* 0x2b */ 7998/* File: mips64/alt_stub.S */ 7999/* 8000 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8001 * any interesting requests and then jump to the real instruction 8002 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8003 */ 8004 .extern MterpCheckBefore 8005 REFRESH_IBASE 8006 dla ra, artMterpAsmInstructionStart 8007 dla t9, MterpCheckBefore 8008 move a0, rSELF 8009 daddu a1, rFP, OFF_FP_SHADOWFRAME 8010 move a2, rPC 8011 daddu ra, ra, (43 * 128) # Addr of primary handler. 8012 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 8013 8014/* ------------------------------ */ 8015 .balign 128 8016.L_ALT_op_sparse_switch: /* 0x2c */ 8017/* File: mips64/alt_stub.S */ 8018/* 8019 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8020 * any interesting requests and then jump to the real instruction 8021 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8022 */ 8023 .extern MterpCheckBefore 8024 REFRESH_IBASE 8025 dla ra, artMterpAsmInstructionStart 8026 dla t9, MterpCheckBefore 8027 move a0, rSELF 8028 daddu a1, rFP, OFF_FP_SHADOWFRAME 8029 move a2, rPC 8030 daddu ra, ra, (44 * 128) # Addr of primary handler. 8031 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 8032 8033/* ------------------------------ */ 8034 .balign 128 8035.L_ALT_op_cmpl_float: /* 0x2d */ 8036/* File: mips64/alt_stub.S */ 8037/* 8038 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8039 * any interesting requests and then jump to the real instruction 8040 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8041 */ 8042 .extern MterpCheckBefore 8043 REFRESH_IBASE 8044 dla ra, artMterpAsmInstructionStart 8045 dla t9, MterpCheckBefore 8046 move a0, rSELF 8047 daddu a1, rFP, OFF_FP_SHADOWFRAME 8048 move a2, rPC 8049 daddu ra, ra, (45 * 128) # Addr of primary handler. 8050 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 8051 8052/* ------------------------------ */ 8053 .balign 128 8054.L_ALT_op_cmpg_float: /* 0x2e */ 8055/* File: mips64/alt_stub.S */ 8056/* 8057 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8058 * any interesting requests and then jump to the real instruction 8059 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8060 */ 8061 .extern MterpCheckBefore 8062 REFRESH_IBASE 8063 dla ra, artMterpAsmInstructionStart 8064 dla t9, MterpCheckBefore 8065 move a0, rSELF 8066 daddu a1, rFP, OFF_FP_SHADOWFRAME 8067 move a2, rPC 8068 daddu ra, ra, (46 * 128) # Addr of primary handler. 8069 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 8070 8071/* ------------------------------ */ 8072 .balign 128 8073.L_ALT_op_cmpl_double: /* 0x2f */ 8074/* File: mips64/alt_stub.S */ 8075/* 8076 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8077 * any interesting requests and then jump to the real instruction 8078 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8079 */ 8080 .extern MterpCheckBefore 8081 REFRESH_IBASE 8082 dla ra, artMterpAsmInstructionStart 8083 dla t9, MterpCheckBefore 8084 move a0, rSELF 8085 daddu a1, rFP, OFF_FP_SHADOWFRAME 8086 move a2, rPC 8087 daddu ra, ra, (47 * 128) # Addr of primary handler. 8088 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 8089 8090/* ------------------------------ */ 8091 .balign 128 8092.L_ALT_op_cmpg_double: /* 0x30 */ 8093/* File: mips64/alt_stub.S */ 8094/* 8095 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8096 * any interesting requests and then jump to the real instruction 8097 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8098 */ 8099 .extern MterpCheckBefore 8100 REFRESH_IBASE 8101 dla ra, artMterpAsmInstructionStart 8102 dla t9, MterpCheckBefore 8103 move a0, rSELF 8104 daddu a1, rFP, OFF_FP_SHADOWFRAME 8105 move a2, rPC 8106 daddu ra, ra, (48 * 128) # Addr of primary handler. 8107 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 8108 8109/* ------------------------------ */ 8110 .balign 128 8111.L_ALT_op_cmp_long: /* 0x31 */ 8112/* File: mips64/alt_stub.S */ 8113/* 8114 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8115 * any interesting requests and then jump to the real instruction 8116 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8117 */ 8118 .extern MterpCheckBefore 8119 REFRESH_IBASE 8120 dla ra, artMterpAsmInstructionStart 8121 dla t9, MterpCheckBefore 8122 move a0, rSELF 8123 daddu a1, rFP, OFF_FP_SHADOWFRAME 8124 move a2, rPC 8125 daddu ra, ra, (49 * 128) # Addr of primary handler. 8126 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 8127 8128/* ------------------------------ */ 8129 .balign 128 8130.L_ALT_op_if_eq: /* 0x32 */ 8131/* File: mips64/alt_stub.S */ 8132/* 8133 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8134 * any interesting requests and then jump to the real instruction 8135 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8136 */ 8137 .extern MterpCheckBefore 8138 REFRESH_IBASE 8139 dla ra, artMterpAsmInstructionStart 8140 dla t9, MterpCheckBefore 8141 move a0, rSELF 8142 daddu a1, rFP, OFF_FP_SHADOWFRAME 8143 move a2, rPC 8144 daddu ra, ra, (50 * 128) # Addr of primary handler. 8145 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 8146 8147/* ------------------------------ */ 8148 .balign 128 8149.L_ALT_op_if_ne: /* 0x33 */ 8150/* File: mips64/alt_stub.S */ 8151/* 8152 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8153 * any interesting requests and then jump to the real instruction 8154 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8155 */ 8156 .extern MterpCheckBefore 8157 REFRESH_IBASE 8158 dla ra, artMterpAsmInstructionStart 8159 dla t9, MterpCheckBefore 8160 move a0, rSELF 8161 daddu a1, rFP, OFF_FP_SHADOWFRAME 8162 move a2, rPC 8163 daddu ra, ra, (51 * 128) # Addr of primary handler. 8164 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 8165 8166/* ------------------------------ */ 8167 .balign 128 8168.L_ALT_op_if_lt: /* 0x34 */ 8169/* File: mips64/alt_stub.S */ 8170/* 8171 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8172 * any interesting requests and then jump to the real instruction 8173 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8174 */ 8175 .extern MterpCheckBefore 8176 REFRESH_IBASE 8177 dla ra, artMterpAsmInstructionStart 8178 dla t9, MterpCheckBefore 8179 move a0, rSELF 8180 daddu a1, rFP, OFF_FP_SHADOWFRAME 8181 move a2, rPC 8182 daddu ra, ra, (52 * 128) # Addr of primary handler. 8183 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 8184 8185/* ------------------------------ */ 8186 .balign 128 8187.L_ALT_op_if_ge: /* 0x35 */ 8188/* File: mips64/alt_stub.S */ 8189/* 8190 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8191 * any interesting requests and then jump to the real instruction 8192 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8193 */ 8194 .extern MterpCheckBefore 8195 REFRESH_IBASE 8196 dla ra, artMterpAsmInstructionStart 8197 dla t9, MterpCheckBefore 8198 move a0, rSELF 8199 daddu a1, rFP, OFF_FP_SHADOWFRAME 8200 move a2, rPC 8201 daddu ra, ra, (53 * 128) # Addr of primary handler. 8202 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 8203 8204/* ------------------------------ */ 8205 .balign 128 8206.L_ALT_op_if_gt: /* 0x36 */ 8207/* File: mips64/alt_stub.S */ 8208/* 8209 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8210 * any interesting requests and then jump to the real instruction 8211 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8212 */ 8213 .extern MterpCheckBefore 8214 REFRESH_IBASE 8215 dla ra, artMterpAsmInstructionStart 8216 dla t9, MterpCheckBefore 8217 move a0, rSELF 8218 daddu a1, rFP, OFF_FP_SHADOWFRAME 8219 move a2, rPC 8220 daddu ra, ra, (54 * 128) # Addr of primary handler. 8221 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 8222 8223/* ------------------------------ */ 8224 .balign 128 8225.L_ALT_op_if_le: /* 0x37 */ 8226/* File: mips64/alt_stub.S */ 8227/* 8228 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8229 * any interesting requests and then jump to the real instruction 8230 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8231 */ 8232 .extern MterpCheckBefore 8233 REFRESH_IBASE 8234 dla ra, artMterpAsmInstructionStart 8235 dla t9, MterpCheckBefore 8236 move a0, rSELF 8237 daddu a1, rFP, OFF_FP_SHADOWFRAME 8238 move a2, rPC 8239 daddu ra, ra, (55 * 128) # Addr of primary handler. 8240 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 8241 8242/* ------------------------------ */ 8243 .balign 128 8244.L_ALT_op_if_eqz: /* 0x38 */ 8245/* File: mips64/alt_stub.S */ 8246/* 8247 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8248 * any interesting requests and then jump to the real instruction 8249 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8250 */ 8251 .extern MterpCheckBefore 8252 REFRESH_IBASE 8253 dla ra, artMterpAsmInstructionStart 8254 dla t9, MterpCheckBefore 8255 move a0, rSELF 8256 daddu a1, rFP, OFF_FP_SHADOWFRAME 8257 move a2, rPC 8258 daddu ra, ra, (56 * 128) # Addr of primary handler. 8259 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 8260 8261/* ------------------------------ */ 8262 .balign 128 8263.L_ALT_op_if_nez: /* 0x39 */ 8264/* File: mips64/alt_stub.S */ 8265/* 8266 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8267 * any interesting requests and then jump to the real instruction 8268 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8269 */ 8270 .extern MterpCheckBefore 8271 REFRESH_IBASE 8272 dla ra, artMterpAsmInstructionStart 8273 dla t9, MterpCheckBefore 8274 move a0, rSELF 8275 daddu a1, rFP, OFF_FP_SHADOWFRAME 8276 move a2, rPC 8277 daddu ra, ra, (57 * 128) # Addr of primary handler. 8278 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 8279 8280/* ------------------------------ */ 8281 .balign 128 8282.L_ALT_op_if_ltz: /* 0x3a */ 8283/* File: mips64/alt_stub.S */ 8284/* 8285 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8286 * any interesting requests and then jump to the real instruction 8287 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8288 */ 8289 .extern MterpCheckBefore 8290 REFRESH_IBASE 8291 dla ra, artMterpAsmInstructionStart 8292 dla t9, MterpCheckBefore 8293 move a0, rSELF 8294 daddu a1, rFP, OFF_FP_SHADOWFRAME 8295 move a2, rPC 8296 daddu ra, ra, (58 * 128) # Addr of primary handler. 8297 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 8298 8299/* ------------------------------ */ 8300 .balign 128 8301.L_ALT_op_if_gez: /* 0x3b */ 8302/* File: mips64/alt_stub.S */ 8303/* 8304 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8305 * any interesting requests and then jump to the real instruction 8306 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8307 */ 8308 .extern MterpCheckBefore 8309 REFRESH_IBASE 8310 dla ra, artMterpAsmInstructionStart 8311 dla t9, MterpCheckBefore 8312 move a0, rSELF 8313 daddu a1, rFP, OFF_FP_SHADOWFRAME 8314 move a2, rPC 8315 daddu ra, ra, (59 * 128) # Addr of primary handler. 8316 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 8317 8318/* ------------------------------ */ 8319 .balign 128 8320.L_ALT_op_if_gtz: /* 0x3c */ 8321/* File: mips64/alt_stub.S */ 8322/* 8323 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8324 * any interesting requests and then jump to the real instruction 8325 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8326 */ 8327 .extern MterpCheckBefore 8328 REFRESH_IBASE 8329 dla ra, artMterpAsmInstructionStart 8330 dla t9, MterpCheckBefore 8331 move a0, rSELF 8332 daddu a1, rFP, OFF_FP_SHADOWFRAME 8333 move a2, rPC 8334 daddu ra, ra, (60 * 128) # Addr of primary handler. 8335 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 8336 8337/* ------------------------------ */ 8338 .balign 128 8339.L_ALT_op_if_lez: /* 0x3d */ 8340/* File: mips64/alt_stub.S */ 8341/* 8342 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8343 * any interesting requests and then jump to the real instruction 8344 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8345 */ 8346 .extern MterpCheckBefore 8347 REFRESH_IBASE 8348 dla ra, artMterpAsmInstructionStart 8349 dla t9, MterpCheckBefore 8350 move a0, rSELF 8351 daddu a1, rFP, OFF_FP_SHADOWFRAME 8352 move a2, rPC 8353 daddu ra, ra, (61 * 128) # Addr of primary handler. 8354 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 8355 8356/* ------------------------------ */ 8357 .balign 128 8358.L_ALT_op_unused_3e: /* 0x3e */ 8359/* File: mips64/alt_stub.S */ 8360/* 8361 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8362 * any interesting requests and then jump to the real instruction 8363 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8364 */ 8365 .extern MterpCheckBefore 8366 REFRESH_IBASE 8367 dla ra, artMterpAsmInstructionStart 8368 dla t9, MterpCheckBefore 8369 move a0, rSELF 8370 daddu a1, rFP, OFF_FP_SHADOWFRAME 8371 move a2, rPC 8372 daddu ra, ra, (62 * 128) # Addr of primary handler. 8373 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 8374 8375/* ------------------------------ */ 8376 .balign 128 8377.L_ALT_op_unused_3f: /* 0x3f */ 8378/* File: mips64/alt_stub.S */ 8379/* 8380 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8381 * any interesting requests and then jump to the real instruction 8382 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8383 */ 8384 .extern MterpCheckBefore 8385 REFRESH_IBASE 8386 dla ra, artMterpAsmInstructionStart 8387 dla t9, MterpCheckBefore 8388 move a0, rSELF 8389 daddu a1, rFP, OFF_FP_SHADOWFRAME 8390 move a2, rPC 8391 daddu ra, ra, (63 * 128) # Addr of primary handler. 8392 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 8393 8394/* ------------------------------ */ 8395 .balign 128 8396.L_ALT_op_unused_40: /* 0x40 */ 8397/* File: mips64/alt_stub.S */ 8398/* 8399 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8400 * any interesting requests and then jump to the real instruction 8401 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8402 */ 8403 .extern MterpCheckBefore 8404 REFRESH_IBASE 8405 dla ra, artMterpAsmInstructionStart 8406 dla t9, MterpCheckBefore 8407 move a0, rSELF 8408 daddu a1, rFP, OFF_FP_SHADOWFRAME 8409 move a2, rPC 8410 daddu ra, ra, (64 * 128) # Addr of primary handler. 8411 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 8412 8413/* ------------------------------ */ 8414 .balign 128 8415.L_ALT_op_unused_41: /* 0x41 */ 8416/* File: mips64/alt_stub.S */ 8417/* 8418 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8419 * any interesting requests and then jump to the real instruction 8420 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8421 */ 8422 .extern MterpCheckBefore 8423 REFRESH_IBASE 8424 dla ra, artMterpAsmInstructionStart 8425 dla t9, MterpCheckBefore 8426 move a0, rSELF 8427 daddu a1, rFP, OFF_FP_SHADOWFRAME 8428 move a2, rPC 8429 daddu ra, ra, (65 * 128) # Addr of primary handler. 8430 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 8431 8432/* ------------------------------ */ 8433 .balign 128 8434.L_ALT_op_unused_42: /* 0x42 */ 8435/* File: mips64/alt_stub.S */ 8436/* 8437 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8438 * any interesting requests and then jump to the real instruction 8439 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8440 */ 8441 .extern MterpCheckBefore 8442 REFRESH_IBASE 8443 dla ra, artMterpAsmInstructionStart 8444 dla t9, MterpCheckBefore 8445 move a0, rSELF 8446 daddu a1, rFP, OFF_FP_SHADOWFRAME 8447 move a2, rPC 8448 daddu ra, ra, (66 * 128) # Addr of primary handler. 8449 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 8450 8451/* ------------------------------ */ 8452 .balign 128 8453.L_ALT_op_unused_43: /* 0x43 */ 8454/* File: mips64/alt_stub.S */ 8455/* 8456 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8457 * any interesting requests and then jump to the real instruction 8458 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8459 */ 8460 .extern MterpCheckBefore 8461 REFRESH_IBASE 8462 dla ra, artMterpAsmInstructionStart 8463 dla t9, MterpCheckBefore 8464 move a0, rSELF 8465 daddu a1, rFP, OFF_FP_SHADOWFRAME 8466 move a2, rPC 8467 daddu ra, ra, (67 * 128) # Addr of primary handler. 8468 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 8469 8470/* ------------------------------ */ 8471 .balign 128 8472.L_ALT_op_aget: /* 0x44 */ 8473/* File: mips64/alt_stub.S */ 8474/* 8475 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8476 * any interesting requests and then jump to the real instruction 8477 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8478 */ 8479 .extern MterpCheckBefore 8480 REFRESH_IBASE 8481 dla ra, artMterpAsmInstructionStart 8482 dla t9, MterpCheckBefore 8483 move a0, rSELF 8484 daddu a1, rFP, OFF_FP_SHADOWFRAME 8485 move a2, rPC 8486 daddu ra, ra, (68 * 128) # Addr of primary handler. 8487 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 8488 8489/* ------------------------------ */ 8490 .balign 128 8491.L_ALT_op_aget_wide: /* 0x45 */ 8492/* File: mips64/alt_stub.S */ 8493/* 8494 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8495 * any interesting requests and then jump to the real instruction 8496 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8497 */ 8498 .extern MterpCheckBefore 8499 REFRESH_IBASE 8500 dla ra, artMterpAsmInstructionStart 8501 dla t9, MterpCheckBefore 8502 move a0, rSELF 8503 daddu a1, rFP, OFF_FP_SHADOWFRAME 8504 move a2, rPC 8505 daddu ra, ra, (69 * 128) # Addr of primary handler. 8506 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 8507 8508/* ------------------------------ */ 8509 .balign 128 8510.L_ALT_op_aget_object: /* 0x46 */ 8511/* File: mips64/alt_stub.S */ 8512/* 8513 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8514 * any interesting requests and then jump to the real instruction 8515 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8516 */ 8517 .extern MterpCheckBefore 8518 REFRESH_IBASE 8519 dla ra, artMterpAsmInstructionStart 8520 dla t9, MterpCheckBefore 8521 move a0, rSELF 8522 daddu a1, rFP, OFF_FP_SHADOWFRAME 8523 move a2, rPC 8524 daddu ra, ra, (70 * 128) # Addr of primary handler. 8525 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 8526 8527/* ------------------------------ */ 8528 .balign 128 8529.L_ALT_op_aget_boolean: /* 0x47 */ 8530/* File: mips64/alt_stub.S */ 8531/* 8532 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8533 * any interesting requests and then jump to the real instruction 8534 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8535 */ 8536 .extern MterpCheckBefore 8537 REFRESH_IBASE 8538 dla ra, artMterpAsmInstructionStart 8539 dla t9, MterpCheckBefore 8540 move a0, rSELF 8541 daddu a1, rFP, OFF_FP_SHADOWFRAME 8542 move a2, rPC 8543 daddu ra, ra, (71 * 128) # Addr of primary handler. 8544 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 8545 8546/* ------------------------------ */ 8547 .balign 128 8548.L_ALT_op_aget_byte: /* 0x48 */ 8549/* File: mips64/alt_stub.S */ 8550/* 8551 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8552 * any interesting requests and then jump to the real instruction 8553 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8554 */ 8555 .extern MterpCheckBefore 8556 REFRESH_IBASE 8557 dla ra, artMterpAsmInstructionStart 8558 dla t9, MterpCheckBefore 8559 move a0, rSELF 8560 daddu a1, rFP, OFF_FP_SHADOWFRAME 8561 move a2, rPC 8562 daddu ra, ra, (72 * 128) # Addr of primary handler. 8563 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 8564 8565/* ------------------------------ */ 8566 .balign 128 8567.L_ALT_op_aget_char: /* 0x49 */ 8568/* File: mips64/alt_stub.S */ 8569/* 8570 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8571 * any interesting requests and then jump to the real instruction 8572 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8573 */ 8574 .extern MterpCheckBefore 8575 REFRESH_IBASE 8576 dla ra, artMterpAsmInstructionStart 8577 dla t9, MterpCheckBefore 8578 move a0, rSELF 8579 daddu a1, rFP, OFF_FP_SHADOWFRAME 8580 move a2, rPC 8581 daddu ra, ra, (73 * 128) # Addr of primary handler. 8582 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 8583 8584/* ------------------------------ */ 8585 .balign 128 8586.L_ALT_op_aget_short: /* 0x4a */ 8587/* File: mips64/alt_stub.S */ 8588/* 8589 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8590 * any interesting requests and then jump to the real instruction 8591 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8592 */ 8593 .extern MterpCheckBefore 8594 REFRESH_IBASE 8595 dla ra, artMterpAsmInstructionStart 8596 dla t9, MterpCheckBefore 8597 move a0, rSELF 8598 daddu a1, rFP, OFF_FP_SHADOWFRAME 8599 move a2, rPC 8600 daddu ra, ra, (74 * 128) # Addr of primary handler. 8601 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 8602 8603/* ------------------------------ */ 8604 .balign 128 8605.L_ALT_op_aput: /* 0x4b */ 8606/* File: mips64/alt_stub.S */ 8607/* 8608 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8609 * any interesting requests and then jump to the real instruction 8610 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8611 */ 8612 .extern MterpCheckBefore 8613 REFRESH_IBASE 8614 dla ra, artMterpAsmInstructionStart 8615 dla t9, MterpCheckBefore 8616 move a0, rSELF 8617 daddu a1, rFP, OFF_FP_SHADOWFRAME 8618 move a2, rPC 8619 daddu ra, ra, (75 * 128) # Addr of primary handler. 8620 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 8621 8622/* ------------------------------ */ 8623 .balign 128 8624.L_ALT_op_aput_wide: /* 0x4c */ 8625/* File: mips64/alt_stub.S */ 8626/* 8627 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8628 * any interesting requests and then jump to the real instruction 8629 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8630 */ 8631 .extern MterpCheckBefore 8632 REFRESH_IBASE 8633 dla ra, artMterpAsmInstructionStart 8634 dla t9, MterpCheckBefore 8635 move a0, rSELF 8636 daddu a1, rFP, OFF_FP_SHADOWFRAME 8637 move a2, rPC 8638 daddu ra, ra, (76 * 128) # Addr of primary handler. 8639 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 8640 8641/* ------------------------------ */ 8642 .balign 128 8643.L_ALT_op_aput_object: /* 0x4d */ 8644/* File: mips64/alt_stub.S */ 8645/* 8646 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8647 * any interesting requests and then jump to the real instruction 8648 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8649 */ 8650 .extern MterpCheckBefore 8651 REFRESH_IBASE 8652 dla ra, artMterpAsmInstructionStart 8653 dla t9, MterpCheckBefore 8654 move a0, rSELF 8655 daddu a1, rFP, OFF_FP_SHADOWFRAME 8656 move a2, rPC 8657 daddu ra, ra, (77 * 128) # Addr of primary handler. 8658 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 8659 8660/* ------------------------------ */ 8661 .balign 128 8662.L_ALT_op_aput_boolean: /* 0x4e */ 8663/* File: mips64/alt_stub.S */ 8664/* 8665 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8666 * any interesting requests and then jump to the real instruction 8667 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8668 */ 8669 .extern MterpCheckBefore 8670 REFRESH_IBASE 8671 dla ra, artMterpAsmInstructionStart 8672 dla t9, MterpCheckBefore 8673 move a0, rSELF 8674 daddu a1, rFP, OFF_FP_SHADOWFRAME 8675 move a2, rPC 8676 daddu ra, ra, (78 * 128) # Addr of primary handler. 8677 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 8678 8679/* ------------------------------ */ 8680 .balign 128 8681.L_ALT_op_aput_byte: /* 0x4f */ 8682/* File: mips64/alt_stub.S */ 8683/* 8684 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8685 * any interesting requests and then jump to the real instruction 8686 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8687 */ 8688 .extern MterpCheckBefore 8689 REFRESH_IBASE 8690 dla ra, artMterpAsmInstructionStart 8691 dla t9, MterpCheckBefore 8692 move a0, rSELF 8693 daddu a1, rFP, OFF_FP_SHADOWFRAME 8694 move a2, rPC 8695 daddu ra, ra, (79 * 128) # Addr of primary handler. 8696 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 8697 8698/* ------------------------------ */ 8699 .balign 128 8700.L_ALT_op_aput_char: /* 0x50 */ 8701/* File: mips64/alt_stub.S */ 8702/* 8703 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8704 * any interesting requests and then jump to the real instruction 8705 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8706 */ 8707 .extern MterpCheckBefore 8708 REFRESH_IBASE 8709 dla ra, artMterpAsmInstructionStart 8710 dla t9, MterpCheckBefore 8711 move a0, rSELF 8712 daddu a1, rFP, OFF_FP_SHADOWFRAME 8713 move a2, rPC 8714 daddu ra, ra, (80 * 128) # Addr of primary handler. 8715 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 8716 8717/* ------------------------------ */ 8718 .balign 128 8719.L_ALT_op_aput_short: /* 0x51 */ 8720/* File: mips64/alt_stub.S */ 8721/* 8722 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8723 * any interesting requests and then jump to the real instruction 8724 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8725 */ 8726 .extern MterpCheckBefore 8727 REFRESH_IBASE 8728 dla ra, artMterpAsmInstructionStart 8729 dla t9, MterpCheckBefore 8730 move a0, rSELF 8731 daddu a1, rFP, OFF_FP_SHADOWFRAME 8732 move a2, rPC 8733 daddu ra, ra, (81 * 128) # Addr of primary handler. 8734 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 8735 8736/* ------------------------------ */ 8737 .balign 128 8738.L_ALT_op_iget: /* 0x52 */ 8739/* File: mips64/alt_stub.S */ 8740/* 8741 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8742 * any interesting requests and then jump to the real instruction 8743 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8744 */ 8745 .extern MterpCheckBefore 8746 REFRESH_IBASE 8747 dla ra, artMterpAsmInstructionStart 8748 dla t9, MterpCheckBefore 8749 move a0, rSELF 8750 daddu a1, rFP, OFF_FP_SHADOWFRAME 8751 move a2, rPC 8752 daddu ra, ra, (82 * 128) # Addr of primary handler. 8753 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 8754 8755/* ------------------------------ */ 8756 .balign 128 8757.L_ALT_op_iget_wide: /* 0x53 */ 8758/* File: mips64/alt_stub.S */ 8759/* 8760 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8761 * any interesting requests and then jump to the real instruction 8762 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8763 */ 8764 .extern MterpCheckBefore 8765 REFRESH_IBASE 8766 dla ra, artMterpAsmInstructionStart 8767 dla t9, MterpCheckBefore 8768 move a0, rSELF 8769 daddu a1, rFP, OFF_FP_SHADOWFRAME 8770 move a2, rPC 8771 daddu ra, ra, (83 * 128) # Addr of primary handler. 8772 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 8773 8774/* ------------------------------ */ 8775 .balign 128 8776.L_ALT_op_iget_object: /* 0x54 */ 8777/* File: mips64/alt_stub.S */ 8778/* 8779 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8780 * any interesting requests and then jump to the real instruction 8781 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8782 */ 8783 .extern MterpCheckBefore 8784 REFRESH_IBASE 8785 dla ra, artMterpAsmInstructionStart 8786 dla t9, MterpCheckBefore 8787 move a0, rSELF 8788 daddu a1, rFP, OFF_FP_SHADOWFRAME 8789 move a2, rPC 8790 daddu ra, ra, (84 * 128) # Addr of primary handler. 8791 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 8792 8793/* ------------------------------ */ 8794 .balign 128 8795.L_ALT_op_iget_boolean: /* 0x55 */ 8796/* File: mips64/alt_stub.S */ 8797/* 8798 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8799 * any interesting requests and then jump to the real instruction 8800 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8801 */ 8802 .extern MterpCheckBefore 8803 REFRESH_IBASE 8804 dla ra, artMterpAsmInstructionStart 8805 dla t9, MterpCheckBefore 8806 move a0, rSELF 8807 daddu a1, rFP, OFF_FP_SHADOWFRAME 8808 move a2, rPC 8809 daddu ra, ra, (85 * 128) # Addr of primary handler. 8810 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 8811 8812/* ------------------------------ */ 8813 .balign 128 8814.L_ALT_op_iget_byte: /* 0x56 */ 8815/* File: mips64/alt_stub.S */ 8816/* 8817 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8818 * any interesting requests and then jump to the real instruction 8819 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8820 */ 8821 .extern MterpCheckBefore 8822 REFRESH_IBASE 8823 dla ra, artMterpAsmInstructionStart 8824 dla t9, MterpCheckBefore 8825 move a0, rSELF 8826 daddu a1, rFP, OFF_FP_SHADOWFRAME 8827 move a2, rPC 8828 daddu ra, ra, (86 * 128) # Addr of primary handler. 8829 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 8830 8831/* ------------------------------ */ 8832 .balign 128 8833.L_ALT_op_iget_char: /* 0x57 */ 8834/* File: mips64/alt_stub.S */ 8835/* 8836 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8837 * any interesting requests and then jump to the real instruction 8838 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8839 */ 8840 .extern MterpCheckBefore 8841 REFRESH_IBASE 8842 dla ra, artMterpAsmInstructionStart 8843 dla t9, MterpCheckBefore 8844 move a0, rSELF 8845 daddu a1, rFP, OFF_FP_SHADOWFRAME 8846 move a2, rPC 8847 daddu ra, ra, (87 * 128) # Addr of primary handler. 8848 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 8849 8850/* ------------------------------ */ 8851 .balign 128 8852.L_ALT_op_iget_short: /* 0x58 */ 8853/* File: mips64/alt_stub.S */ 8854/* 8855 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8856 * any interesting requests and then jump to the real instruction 8857 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8858 */ 8859 .extern MterpCheckBefore 8860 REFRESH_IBASE 8861 dla ra, artMterpAsmInstructionStart 8862 dla t9, MterpCheckBefore 8863 move a0, rSELF 8864 daddu a1, rFP, OFF_FP_SHADOWFRAME 8865 move a2, rPC 8866 daddu ra, ra, (88 * 128) # Addr of primary handler. 8867 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 8868 8869/* ------------------------------ */ 8870 .balign 128 8871.L_ALT_op_iput: /* 0x59 */ 8872/* File: mips64/alt_stub.S */ 8873/* 8874 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8875 * any interesting requests and then jump to the real instruction 8876 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8877 */ 8878 .extern MterpCheckBefore 8879 REFRESH_IBASE 8880 dla ra, artMterpAsmInstructionStart 8881 dla t9, MterpCheckBefore 8882 move a0, rSELF 8883 daddu a1, rFP, OFF_FP_SHADOWFRAME 8884 move a2, rPC 8885 daddu ra, ra, (89 * 128) # Addr of primary handler. 8886 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 8887 8888/* ------------------------------ */ 8889 .balign 128 8890.L_ALT_op_iput_wide: /* 0x5a */ 8891/* File: mips64/alt_stub.S */ 8892/* 8893 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8894 * any interesting requests and then jump to the real instruction 8895 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8896 */ 8897 .extern MterpCheckBefore 8898 REFRESH_IBASE 8899 dla ra, artMterpAsmInstructionStart 8900 dla t9, MterpCheckBefore 8901 move a0, rSELF 8902 daddu a1, rFP, OFF_FP_SHADOWFRAME 8903 move a2, rPC 8904 daddu ra, ra, (90 * 128) # Addr of primary handler. 8905 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 8906 8907/* ------------------------------ */ 8908 .balign 128 8909.L_ALT_op_iput_object: /* 0x5b */ 8910/* File: mips64/alt_stub.S */ 8911/* 8912 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8913 * any interesting requests and then jump to the real instruction 8914 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8915 */ 8916 .extern MterpCheckBefore 8917 REFRESH_IBASE 8918 dla ra, artMterpAsmInstructionStart 8919 dla t9, MterpCheckBefore 8920 move a0, rSELF 8921 daddu a1, rFP, OFF_FP_SHADOWFRAME 8922 move a2, rPC 8923 daddu ra, ra, (91 * 128) # Addr of primary handler. 8924 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 8925 8926/* ------------------------------ */ 8927 .balign 128 8928.L_ALT_op_iput_boolean: /* 0x5c */ 8929/* File: mips64/alt_stub.S */ 8930/* 8931 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8932 * any interesting requests and then jump to the real instruction 8933 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8934 */ 8935 .extern MterpCheckBefore 8936 REFRESH_IBASE 8937 dla ra, artMterpAsmInstructionStart 8938 dla t9, MterpCheckBefore 8939 move a0, rSELF 8940 daddu a1, rFP, OFF_FP_SHADOWFRAME 8941 move a2, rPC 8942 daddu ra, ra, (92 * 128) # Addr of primary handler. 8943 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 8944 8945/* ------------------------------ */ 8946 .balign 128 8947.L_ALT_op_iput_byte: /* 0x5d */ 8948/* File: mips64/alt_stub.S */ 8949/* 8950 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8951 * any interesting requests and then jump to the real instruction 8952 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8953 */ 8954 .extern MterpCheckBefore 8955 REFRESH_IBASE 8956 dla ra, artMterpAsmInstructionStart 8957 dla t9, MterpCheckBefore 8958 move a0, rSELF 8959 daddu a1, rFP, OFF_FP_SHADOWFRAME 8960 move a2, rPC 8961 daddu ra, ra, (93 * 128) # Addr of primary handler. 8962 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 8963 8964/* ------------------------------ */ 8965 .balign 128 8966.L_ALT_op_iput_char: /* 0x5e */ 8967/* File: mips64/alt_stub.S */ 8968/* 8969 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8970 * any interesting requests and then jump to the real instruction 8971 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8972 */ 8973 .extern MterpCheckBefore 8974 REFRESH_IBASE 8975 dla ra, artMterpAsmInstructionStart 8976 dla t9, MterpCheckBefore 8977 move a0, rSELF 8978 daddu a1, rFP, OFF_FP_SHADOWFRAME 8979 move a2, rPC 8980 daddu ra, ra, (94 * 128) # Addr of primary handler. 8981 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 8982 8983/* ------------------------------ */ 8984 .balign 128 8985.L_ALT_op_iput_short: /* 0x5f */ 8986/* File: mips64/alt_stub.S */ 8987/* 8988 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8989 * any interesting requests and then jump to the real instruction 8990 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8991 */ 8992 .extern MterpCheckBefore 8993 REFRESH_IBASE 8994 dla ra, artMterpAsmInstructionStart 8995 dla t9, MterpCheckBefore 8996 move a0, rSELF 8997 daddu a1, rFP, OFF_FP_SHADOWFRAME 8998 move a2, rPC 8999 daddu ra, ra, (95 * 128) # Addr of primary handler. 9000 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 9001 9002/* ------------------------------ */ 9003 .balign 128 9004.L_ALT_op_sget: /* 0x60 */ 9005/* File: mips64/alt_stub.S */ 9006/* 9007 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9008 * any interesting requests and then jump to the real instruction 9009 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9010 */ 9011 .extern MterpCheckBefore 9012 REFRESH_IBASE 9013 dla ra, artMterpAsmInstructionStart 9014 dla t9, MterpCheckBefore 9015 move a0, rSELF 9016 daddu a1, rFP, OFF_FP_SHADOWFRAME 9017 move a2, rPC 9018 daddu ra, ra, (96 * 128) # Addr of primary handler. 9019 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 9020 9021/* ------------------------------ */ 9022 .balign 128 9023.L_ALT_op_sget_wide: /* 0x61 */ 9024/* File: mips64/alt_stub.S */ 9025/* 9026 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9027 * any interesting requests and then jump to the real instruction 9028 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9029 */ 9030 .extern MterpCheckBefore 9031 REFRESH_IBASE 9032 dla ra, artMterpAsmInstructionStart 9033 dla t9, MterpCheckBefore 9034 move a0, rSELF 9035 daddu a1, rFP, OFF_FP_SHADOWFRAME 9036 move a2, rPC 9037 daddu ra, ra, (97 * 128) # Addr of primary handler. 9038 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 9039 9040/* ------------------------------ */ 9041 .balign 128 9042.L_ALT_op_sget_object: /* 0x62 */ 9043/* File: mips64/alt_stub.S */ 9044/* 9045 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9046 * any interesting requests and then jump to the real instruction 9047 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9048 */ 9049 .extern MterpCheckBefore 9050 REFRESH_IBASE 9051 dla ra, artMterpAsmInstructionStart 9052 dla t9, MterpCheckBefore 9053 move a0, rSELF 9054 daddu a1, rFP, OFF_FP_SHADOWFRAME 9055 move a2, rPC 9056 daddu ra, ra, (98 * 128) # Addr of primary handler. 9057 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 9058 9059/* ------------------------------ */ 9060 .balign 128 9061.L_ALT_op_sget_boolean: /* 0x63 */ 9062/* File: mips64/alt_stub.S */ 9063/* 9064 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9065 * any interesting requests and then jump to the real instruction 9066 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9067 */ 9068 .extern MterpCheckBefore 9069 REFRESH_IBASE 9070 dla ra, artMterpAsmInstructionStart 9071 dla t9, MterpCheckBefore 9072 move a0, rSELF 9073 daddu a1, rFP, OFF_FP_SHADOWFRAME 9074 move a2, rPC 9075 daddu ra, ra, (99 * 128) # Addr of primary handler. 9076 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 9077 9078/* ------------------------------ */ 9079 .balign 128 9080.L_ALT_op_sget_byte: /* 0x64 */ 9081/* File: mips64/alt_stub.S */ 9082/* 9083 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9084 * any interesting requests and then jump to the real instruction 9085 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9086 */ 9087 .extern MterpCheckBefore 9088 REFRESH_IBASE 9089 dla ra, artMterpAsmInstructionStart 9090 dla t9, MterpCheckBefore 9091 move a0, rSELF 9092 daddu a1, rFP, OFF_FP_SHADOWFRAME 9093 move a2, rPC 9094 daddu ra, ra, (100 * 128) # Addr of primary handler. 9095 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 9096 9097/* ------------------------------ */ 9098 .balign 128 9099.L_ALT_op_sget_char: /* 0x65 */ 9100/* File: mips64/alt_stub.S */ 9101/* 9102 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9103 * any interesting requests and then jump to the real instruction 9104 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9105 */ 9106 .extern MterpCheckBefore 9107 REFRESH_IBASE 9108 dla ra, artMterpAsmInstructionStart 9109 dla t9, MterpCheckBefore 9110 move a0, rSELF 9111 daddu a1, rFP, OFF_FP_SHADOWFRAME 9112 move a2, rPC 9113 daddu ra, ra, (101 * 128) # Addr of primary handler. 9114 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 9115 9116/* ------------------------------ */ 9117 .balign 128 9118.L_ALT_op_sget_short: /* 0x66 */ 9119/* File: mips64/alt_stub.S */ 9120/* 9121 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9122 * any interesting requests and then jump to the real instruction 9123 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9124 */ 9125 .extern MterpCheckBefore 9126 REFRESH_IBASE 9127 dla ra, artMterpAsmInstructionStart 9128 dla t9, MterpCheckBefore 9129 move a0, rSELF 9130 daddu a1, rFP, OFF_FP_SHADOWFRAME 9131 move a2, rPC 9132 daddu ra, ra, (102 * 128) # Addr of primary handler. 9133 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 9134 9135/* ------------------------------ */ 9136 .balign 128 9137.L_ALT_op_sput: /* 0x67 */ 9138/* File: mips64/alt_stub.S */ 9139/* 9140 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9141 * any interesting requests and then jump to the real instruction 9142 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9143 */ 9144 .extern MterpCheckBefore 9145 REFRESH_IBASE 9146 dla ra, artMterpAsmInstructionStart 9147 dla t9, MterpCheckBefore 9148 move a0, rSELF 9149 daddu a1, rFP, OFF_FP_SHADOWFRAME 9150 move a2, rPC 9151 daddu ra, ra, (103 * 128) # Addr of primary handler. 9152 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 9153 9154/* ------------------------------ */ 9155 .balign 128 9156.L_ALT_op_sput_wide: /* 0x68 */ 9157/* File: mips64/alt_stub.S */ 9158/* 9159 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9160 * any interesting requests and then jump to the real instruction 9161 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9162 */ 9163 .extern MterpCheckBefore 9164 REFRESH_IBASE 9165 dla ra, artMterpAsmInstructionStart 9166 dla t9, MterpCheckBefore 9167 move a0, rSELF 9168 daddu a1, rFP, OFF_FP_SHADOWFRAME 9169 move a2, rPC 9170 daddu ra, ra, (104 * 128) # Addr of primary handler. 9171 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 9172 9173/* ------------------------------ */ 9174 .balign 128 9175.L_ALT_op_sput_object: /* 0x69 */ 9176/* File: mips64/alt_stub.S */ 9177/* 9178 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9179 * any interesting requests and then jump to the real instruction 9180 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9181 */ 9182 .extern MterpCheckBefore 9183 REFRESH_IBASE 9184 dla ra, artMterpAsmInstructionStart 9185 dla t9, MterpCheckBefore 9186 move a0, rSELF 9187 daddu a1, rFP, OFF_FP_SHADOWFRAME 9188 move a2, rPC 9189 daddu ra, ra, (105 * 128) # Addr of primary handler. 9190 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 9191 9192/* ------------------------------ */ 9193 .balign 128 9194.L_ALT_op_sput_boolean: /* 0x6a */ 9195/* File: mips64/alt_stub.S */ 9196/* 9197 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9198 * any interesting requests and then jump to the real instruction 9199 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9200 */ 9201 .extern MterpCheckBefore 9202 REFRESH_IBASE 9203 dla ra, artMterpAsmInstructionStart 9204 dla t9, MterpCheckBefore 9205 move a0, rSELF 9206 daddu a1, rFP, OFF_FP_SHADOWFRAME 9207 move a2, rPC 9208 daddu ra, ra, (106 * 128) # Addr of primary handler. 9209 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 9210 9211/* ------------------------------ */ 9212 .balign 128 9213.L_ALT_op_sput_byte: /* 0x6b */ 9214/* File: mips64/alt_stub.S */ 9215/* 9216 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9217 * any interesting requests and then jump to the real instruction 9218 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9219 */ 9220 .extern MterpCheckBefore 9221 REFRESH_IBASE 9222 dla ra, artMterpAsmInstructionStart 9223 dla t9, MterpCheckBefore 9224 move a0, rSELF 9225 daddu a1, rFP, OFF_FP_SHADOWFRAME 9226 move a2, rPC 9227 daddu ra, ra, (107 * 128) # Addr of primary handler. 9228 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 9229 9230/* ------------------------------ */ 9231 .balign 128 9232.L_ALT_op_sput_char: /* 0x6c */ 9233/* File: mips64/alt_stub.S */ 9234/* 9235 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9236 * any interesting requests and then jump to the real instruction 9237 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9238 */ 9239 .extern MterpCheckBefore 9240 REFRESH_IBASE 9241 dla ra, artMterpAsmInstructionStart 9242 dla t9, MterpCheckBefore 9243 move a0, rSELF 9244 daddu a1, rFP, OFF_FP_SHADOWFRAME 9245 move a2, rPC 9246 daddu ra, ra, (108 * 128) # Addr of primary handler. 9247 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 9248 9249/* ------------------------------ */ 9250 .balign 128 9251.L_ALT_op_sput_short: /* 0x6d */ 9252/* File: mips64/alt_stub.S */ 9253/* 9254 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9255 * any interesting requests and then jump to the real instruction 9256 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9257 */ 9258 .extern MterpCheckBefore 9259 REFRESH_IBASE 9260 dla ra, artMterpAsmInstructionStart 9261 dla t9, MterpCheckBefore 9262 move a0, rSELF 9263 daddu a1, rFP, OFF_FP_SHADOWFRAME 9264 move a2, rPC 9265 daddu ra, ra, (109 * 128) # Addr of primary handler. 9266 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 9267 9268/* ------------------------------ */ 9269 .balign 128 9270.L_ALT_op_invoke_virtual: /* 0x6e */ 9271/* File: mips64/alt_stub.S */ 9272/* 9273 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9274 * any interesting requests and then jump to the real instruction 9275 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9276 */ 9277 .extern MterpCheckBefore 9278 REFRESH_IBASE 9279 dla ra, artMterpAsmInstructionStart 9280 dla t9, MterpCheckBefore 9281 move a0, rSELF 9282 daddu a1, rFP, OFF_FP_SHADOWFRAME 9283 move a2, rPC 9284 daddu ra, ra, (110 * 128) # Addr of primary handler. 9285 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 9286 9287/* ------------------------------ */ 9288 .balign 128 9289.L_ALT_op_invoke_super: /* 0x6f */ 9290/* File: mips64/alt_stub.S */ 9291/* 9292 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9293 * any interesting requests and then jump to the real instruction 9294 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9295 */ 9296 .extern MterpCheckBefore 9297 REFRESH_IBASE 9298 dla ra, artMterpAsmInstructionStart 9299 dla t9, MterpCheckBefore 9300 move a0, rSELF 9301 daddu a1, rFP, OFF_FP_SHADOWFRAME 9302 move a2, rPC 9303 daddu ra, ra, (111 * 128) # Addr of primary handler. 9304 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 9305 9306/* ------------------------------ */ 9307 .balign 128 9308.L_ALT_op_invoke_direct: /* 0x70 */ 9309/* File: mips64/alt_stub.S */ 9310/* 9311 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9312 * any interesting requests and then jump to the real instruction 9313 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9314 */ 9315 .extern MterpCheckBefore 9316 REFRESH_IBASE 9317 dla ra, artMterpAsmInstructionStart 9318 dla t9, MterpCheckBefore 9319 move a0, rSELF 9320 daddu a1, rFP, OFF_FP_SHADOWFRAME 9321 move a2, rPC 9322 daddu ra, ra, (112 * 128) # Addr of primary handler. 9323 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 9324 9325/* ------------------------------ */ 9326 .balign 128 9327.L_ALT_op_invoke_static: /* 0x71 */ 9328/* File: mips64/alt_stub.S */ 9329/* 9330 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9331 * any interesting requests and then jump to the real instruction 9332 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9333 */ 9334 .extern MterpCheckBefore 9335 REFRESH_IBASE 9336 dla ra, artMterpAsmInstructionStart 9337 dla t9, MterpCheckBefore 9338 move a0, rSELF 9339 daddu a1, rFP, OFF_FP_SHADOWFRAME 9340 move a2, rPC 9341 daddu ra, ra, (113 * 128) # Addr of primary handler. 9342 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 9343 9344/* ------------------------------ */ 9345 .balign 128 9346.L_ALT_op_invoke_interface: /* 0x72 */ 9347/* File: mips64/alt_stub.S */ 9348/* 9349 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9350 * any interesting requests and then jump to the real instruction 9351 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9352 */ 9353 .extern MterpCheckBefore 9354 REFRESH_IBASE 9355 dla ra, artMterpAsmInstructionStart 9356 dla t9, MterpCheckBefore 9357 move a0, rSELF 9358 daddu a1, rFP, OFF_FP_SHADOWFRAME 9359 move a2, rPC 9360 daddu ra, ra, (114 * 128) # Addr of primary handler. 9361 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 9362 9363/* ------------------------------ */ 9364 .balign 128 9365.L_ALT_op_return_void_no_barrier: /* 0x73 */ 9366/* File: mips64/alt_stub.S */ 9367/* 9368 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9369 * any interesting requests and then jump to the real instruction 9370 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9371 */ 9372 .extern MterpCheckBefore 9373 REFRESH_IBASE 9374 dla ra, artMterpAsmInstructionStart 9375 dla t9, MterpCheckBefore 9376 move a0, rSELF 9377 daddu a1, rFP, OFF_FP_SHADOWFRAME 9378 move a2, rPC 9379 daddu ra, ra, (115 * 128) # Addr of primary handler. 9380 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 9381 9382/* ------------------------------ */ 9383 .balign 128 9384.L_ALT_op_invoke_virtual_range: /* 0x74 */ 9385/* File: mips64/alt_stub.S */ 9386/* 9387 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9388 * any interesting requests and then jump to the real instruction 9389 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9390 */ 9391 .extern MterpCheckBefore 9392 REFRESH_IBASE 9393 dla ra, artMterpAsmInstructionStart 9394 dla t9, MterpCheckBefore 9395 move a0, rSELF 9396 daddu a1, rFP, OFF_FP_SHADOWFRAME 9397 move a2, rPC 9398 daddu ra, ra, (116 * 128) # Addr of primary handler. 9399 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 9400 9401/* ------------------------------ */ 9402 .balign 128 9403.L_ALT_op_invoke_super_range: /* 0x75 */ 9404/* File: mips64/alt_stub.S */ 9405/* 9406 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9407 * any interesting requests and then jump to the real instruction 9408 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9409 */ 9410 .extern MterpCheckBefore 9411 REFRESH_IBASE 9412 dla ra, artMterpAsmInstructionStart 9413 dla t9, MterpCheckBefore 9414 move a0, rSELF 9415 daddu a1, rFP, OFF_FP_SHADOWFRAME 9416 move a2, rPC 9417 daddu ra, ra, (117 * 128) # Addr of primary handler. 9418 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 9419 9420/* ------------------------------ */ 9421 .balign 128 9422.L_ALT_op_invoke_direct_range: /* 0x76 */ 9423/* File: mips64/alt_stub.S */ 9424/* 9425 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9426 * any interesting requests and then jump to the real instruction 9427 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9428 */ 9429 .extern MterpCheckBefore 9430 REFRESH_IBASE 9431 dla ra, artMterpAsmInstructionStart 9432 dla t9, MterpCheckBefore 9433 move a0, rSELF 9434 daddu a1, rFP, OFF_FP_SHADOWFRAME 9435 move a2, rPC 9436 daddu ra, ra, (118 * 128) # Addr of primary handler. 9437 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 9438 9439/* ------------------------------ */ 9440 .balign 128 9441.L_ALT_op_invoke_static_range: /* 0x77 */ 9442/* File: mips64/alt_stub.S */ 9443/* 9444 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9445 * any interesting requests and then jump to the real instruction 9446 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9447 */ 9448 .extern MterpCheckBefore 9449 REFRESH_IBASE 9450 dla ra, artMterpAsmInstructionStart 9451 dla t9, MterpCheckBefore 9452 move a0, rSELF 9453 daddu a1, rFP, OFF_FP_SHADOWFRAME 9454 move a2, rPC 9455 daddu ra, ra, (119 * 128) # Addr of primary handler. 9456 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 9457 9458/* ------------------------------ */ 9459 .balign 128 9460.L_ALT_op_invoke_interface_range: /* 0x78 */ 9461/* File: mips64/alt_stub.S */ 9462/* 9463 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9464 * any interesting requests and then jump to the real instruction 9465 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9466 */ 9467 .extern MterpCheckBefore 9468 REFRESH_IBASE 9469 dla ra, artMterpAsmInstructionStart 9470 dla t9, MterpCheckBefore 9471 move a0, rSELF 9472 daddu a1, rFP, OFF_FP_SHADOWFRAME 9473 move a2, rPC 9474 daddu ra, ra, (120 * 128) # Addr of primary handler. 9475 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 9476 9477/* ------------------------------ */ 9478 .balign 128 9479.L_ALT_op_unused_79: /* 0x79 */ 9480/* File: mips64/alt_stub.S */ 9481/* 9482 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9483 * any interesting requests and then jump to the real instruction 9484 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9485 */ 9486 .extern MterpCheckBefore 9487 REFRESH_IBASE 9488 dla ra, artMterpAsmInstructionStart 9489 dla t9, MterpCheckBefore 9490 move a0, rSELF 9491 daddu a1, rFP, OFF_FP_SHADOWFRAME 9492 move a2, rPC 9493 daddu ra, ra, (121 * 128) # Addr of primary handler. 9494 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 9495 9496/* ------------------------------ */ 9497 .balign 128 9498.L_ALT_op_unused_7a: /* 0x7a */ 9499/* File: mips64/alt_stub.S */ 9500/* 9501 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9502 * any interesting requests and then jump to the real instruction 9503 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9504 */ 9505 .extern MterpCheckBefore 9506 REFRESH_IBASE 9507 dla ra, artMterpAsmInstructionStart 9508 dla t9, MterpCheckBefore 9509 move a0, rSELF 9510 daddu a1, rFP, OFF_FP_SHADOWFRAME 9511 move a2, rPC 9512 daddu ra, ra, (122 * 128) # Addr of primary handler. 9513 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 9514 9515/* ------------------------------ */ 9516 .balign 128 9517.L_ALT_op_neg_int: /* 0x7b */ 9518/* File: mips64/alt_stub.S */ 9519/* 9520 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9521 * any interesting requests and then jump to the real instruction 9522 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9523 */ 9524 .extern MterpCheckBefore 9525 REFRESH_IBASE 9526 dla ra, artMterpAsmInstructionStart 9527 dla t9, MterpCheckBefore 9528 move a0, rSELF 9529 daddu a1, rFP, OFF_FP_SHADOWFRAME 9530 move a2, rPC 9531 daddu ra, ra, (123 * 128) # Addr of primary handler. 9532 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 9533 9534/* ------------------------------ */ 9535 .balign 128 9536.L_ALT_op_not_int: /* 0x7c */ 9537/* File: mips64/alt_stub.S */ 9538/* 9539 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9540 * any interesting requests and then jump to the real instruction 9541 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9542 */ 9543 .extern MterpCheckBefore 9544 REFRESH_IBASE 9545 dla ra, artMterpAsmInstructionStart 9546 dla t9, MterpCheckBefore 9547 move a0, rSELF 9548 daddu a1, rFP, OFF_FP_SHADOWFRAME 9549 move a2, rPC 9550 daddu ra, ra, (124 * 128) # Addr of primary handler. 9551 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 9552 9553/* ------------------------------ */ 9554 .balign 128 9555.L_ALT_op_neg_long: /* 0x7d */ 9556/* File: mips64/alt_stub.S */ 9557/* 9558 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9559 * any interesting requests and then jump to the real instruction 9560 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9561 */ 9562 .extern MterpCheckBefore 9563 REFRESH_IBASE 9564 dla ra, artMterpAsmInstructionStart 9565 dla t9, MterpCheckBefore 9566 move a0, rSELF 9567 daddu a1, rFP, OFF_FP_SHADOWFRAME 9568 move a2, rPC 9569 daddu ra, ra, (125 * 128) # Addr of primary handler. 9570 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 9571 9572/* ------------------------------ */ 9573 .balign 128 9574.L_ALT_op_not_long: /* 0x7e */ 9575/* File: mips64/alt_stub.S */ 9576/* 9577 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9578 * any interesting requests and then jump to the real instruction 9579 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9580 */ 9581 .extern MterpCheckBefore 9582 REFRESH_IBASE 9583 dla ra, artMterpAsmInstructionStart 9584 dla t9, MterpCheckBefore 9585 move a0, rSELF 9586 daddu a1, rFP, OFF_FP_SHADOWFRAME 9587 move a2, rPC 9588 daddu ra, ra, (126 * 128) # Addr of primary handler. 9589 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 9590 9591/* ------------------------------ */ 9592 .balign 128 9593.L_ALT_op_neg_float: /* 0x7f */ 9594/* File: mips64/alt_stub.S */ 9595/* 9596 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9597 * any interesting requests and then jump to the real instruction 9598 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9599 */ 9600 .extern MterpCheckBefore 9601 REFRESH_IBASE 9602 dla ra, artMterpAsmInstructionStart 9603 dla t9, MterpCheckBefore 9604 move a0, rSELF 9605 daddu a1, rFP, OFF_FP_SHADOWFRAME 9606 move a2, rPC 9607 daddu ra, ra, (127 * 128) # Addr of primary handler. 9608 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 9609 9610/* ------------------------------ */ 9611 .balign 128 9612.L_ALT_op_neg_double: /* 0x80 */ 9613/* File: mips64/alt_stub.S */ 9614/* 9615 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9616 * any interesting requests and then jump to the real instruction 9617 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9618 */ 9619 .extern MterpCheckBefore 9620 REFRESH_IBASE 9621 dla ra, artMterpAsmInstructionStart 9622 dla t9, MterpCheckBefore 9623 move a0, rSELF 9624 daddu a1, rFP, OFF_FP_SHADOWFRAME 9625 move a2, rPC 9626 daddu ra, ra, (128 * 128) # Addr of primary handler. 9627 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 9628 9629/* ------------------------------ */ 9630 .balign 128 9631.L_ALT_op_int_to_long: /* 0x81 */ 9632/* File: mips64/alt_stub.S */ 9633/* 9634 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9635 * any interesting requests and then jump to the real instruction 9636 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9637 */ 9638 .extern MterpCheckBefore 9639 REFRESH_IBASE 9640 dla ra, artMterpAsmInstructionStart 9641 dla t9, MterpCheckBefore 9642 move a0, rSELF 9643 daddu a1, rFP, OFF_FP_SHADOWFRAME 9644 move a2, rPC 9645 daddu ra, ra, (129 * 128) # Addr of primary handler. 9646 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 9647 9648/* ------------------------------ */ 9649 .balign 128 9650.L_ALT_op_int_to_float: /* 0x82 */ 9651/* File: mips64/alt_stub.S */ 9652/* 9653 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9654 * any interesting requests and then jump to the real instruction 9655 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9656 */ 9657 .extern MterpCheckBefore 9658 REFRESH_IBASE 9659 dla ra, artMterpAsmInstructionStart 9660 dla t9, MterpCheckBefore 9661 move a0, rSELF 9662 daddu a1, rFP, OFF_FP_SHADOWFRAME 9663 move a2, rPC 9664 daddu ra, ra, (130 * 128) # Addr of primary handler. 9665 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 9666 9667/* ------------------------------ */ 9668 .balign 128 9669.L_ALT_op_int_to_double: /* 0x83 */ 9670/* File: mips64/alt_stub.S */ 9671/* 9672 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9673 * any interesting requests and then jump to the real instruction 9674 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9675 */ 9676 .extern MterpCheckBefore 9677 REFRESH_IBASE 9678 dla ra, artMterpAsmInstructionStart 9679 dla t9, MterpCheckBefore 9680 move a0, rSELF 9681 daddu a1, rFP, OFF_FP_SHADOWFRAME 9682 move a2, rPC 9683 daddu ra, ra, (131 * 128) # Addr of primary handler. 9684 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 9685 9686/* ------------------------------ */ 9687 .balign 128 9688.L_ALT_op_long_to_int: /* 0x84 */ 9689/* File: mips64/alt_stub.S */ 9690/* 9691 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9692 * any interesting requests and then jump to the real instruction 9693 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9694 */ 9695 .extern MterpCheckBefore 9696 REFRESH_IBASE 9697 dla ra, artMterpAsmInstructionStart 9698 dla t9, MterpCheckBefore 9699 move a0, rSELF 9700 daddu a1, rFP, OFF_FP_SHADOWFRAME 9701 move a2, rPC 9702 daddu ra, ra, (132 * 128) # Addr of primary handler. 9703 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 9704 9705/* ------------------------------ */ 9706 .balign 128 9707.L_ALT_op_long_to_float: /* 0x85 */ 9708/* File: mips64/alt_stub.S */ 9709/* 9710 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9711 * any interesting requests and then jump to the real instruction 9712 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9713 */ 9714 .extern MterpCheckBefore 9715 REFRESH_IBASE 9716 dla ra, artMterpAsmInstructionStart 9717 dla t9, MterpCheckBefore 9718 move a0, rSELF 9719 daddu a1, rFP, OFF_FP_SHADOWFRAME 9720 move a2, rPC 9721 daddu ra, ra, (133 * 128) # Addr of primary handler. 9722 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 9723 9724/* ------------------------------ */ 9725 .balign 128 9726.L_ALT_op_long_to_double: /* 0x86 */ 9727/* File: mips64/alt_stub.S */ 9728/* 9729 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9730 * any interesting requests and then jump to the real instruction 9731 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9732 */ 9733 .extern MterpCheckBefore 9734 REFRESH_IBASE 9735 dla ra, artMterpAsmInstructionStart 9736 dla t9, MterpCheckBefore 9737 move a0, rSELF 9738 daddu a1, rFP, OFF_FP_SHADOWFRAME 9739 move a2, rPC 9740 daddu ra, ra, (134 * 128) # Addr of primary handler. 9741 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 9742 9743/* ------------------------------ */ 9744 .balign 128 9745.L_ALT_op_float_to_int: /* 0x87 */ 9746/* File: mips64/alt_stub.S */ 9747/* 9748 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9749 * any interesting requests and then jump to the real instruction 9750 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9751 */ 9752 .extern MterpCheckBefore 9753 REFRESH_IBASE 9754 dla ra, artMterpAsmInstructionStart 9755 dla t9, MterpCheckBefore 9756 move a0, rSELF 9757 daddu a1, rFP, OFF_FP_SHADOWFRAME 9758 move a2, rPC 9759 daddu ra, ra, (135 * 128) # Addr of primary handler. 9760 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 9761 9762/* ------------------------------ */ 9763 .balign 128 9764.L_ALT_op_float_to_long: /* 0x88 */ 9765/* File: mips64/alt_stub.S */ 9766/* 9767 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9768 * any interesting requests and then jump to the real instruction 9769 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9770 */ 9771 .extern MterpCheckBefore 9772 REFRESH_IBASE 9773 dla ra, artMterpAsmInstructionStart 9774 dla t9, MterpCheckBefore 9775 move a0, rSELF 9776 daddu a1, rFP, OFF_FP_SHADOWFRAME 9777 move a2, rPC 9778 daddu ra, ra, (136 * 128) # Addr of primary handler. 9779 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 9780 9781/* ------------------------------ */ 9782 .balign 128 9783.L_ALT_op_float_to_double: /* 0x89 */ 9784/* File: mips64/alt_stub.S */ 9785/* 9786 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9787 * any interesting requests and then jump to the real instruction 9788 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9789 */ 9790 .extern MterpCheckBefore 9791 REFRESH_IBASE 9792 dla ra, artMterpAsmInstructionStart 9793 dla t9, MterpCheckBefore 9794 move a0, rSELF 9795 daddu a1, rFP, OFF_FP_SHADOWFRAME 9796 move a2, rPC 9797 daddu ra, ra, (137 * 128) # Addr of primary handler. 9798 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 9799 9800/* ------------------------------ */ 9801 .balign 128 9802.L_ALT_op_double_to_int: /* 0x8a */ 9803/* File: mips64/alt_stub.S */ 9804/* 9805 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9806 * any interesting requests and then jump to the real instruction 9807 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9808 */ 9809 .extern MterpCheckBefore 9810 REFRESH_IBASE 9811 dla ra, artMterpAsmInstructionStart 9812 dla t9, MterpCheckBefore 9813 move a0, rSELF 9814 daddu a1, rFP, OFF_FP_SHADOWFRAME 9815 move a2, rPC 9816 daddu ra, ra, (138 * 128) # Addr of primary handler. 9817 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 9818 9819/* ------------------------------ */ 9820 .balign 128 9821.L_ALT_op_double_to_long: /* 0x8b */ 9822/* File: mips64/alt_stub.S */ 9823/* 9824 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9825 * any interesting requests and then jump to the real instruction 9826 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9827 */ 9828 .extern MterpCheckBefore 9829 REFRESH_IBASE 9830 dla ra, artMterpAsmInstructionStart 9831 dla t9, MterpCheckBefore 9832 move a0, rSELF 9833 daddu a1, rFP, OFF_FP_SHADOWFRAME 9834 move a2, rPC 9835 daddu ra, ra, (139 * 128) # Addr of primary handler. 9836 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 9837 9838/* ------------------------------ */ 9839 .balign 128 9840.L_ALT_op_double_to_float: /* 0x8c */ 9841/* File: mips64/alt_stub.S */ 9842/* 9843 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9844 * any interesting requests and then jump to the real instruction 9845 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9846 */ 9847 .extern MterpCheckBefore 9848 REFRESH_IBASE 9849 dla ra, artMterpAsmInstructionStart 9850 dla t9, MterpCheckBefore 9851 move a0, rSELF 9852 daddu a1, rFP, OFF_FP_SHADOWFRAME 9853 move a2, rPC 9854 daddu ra, ra, (140 * 128) # Addr of primary handler. 9855 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 9856 9857/* ------------------------------ */ 9858 .balign 128 9859.L_ALT_op_int_to_byte: /* 0x8d */ 9860/* File: mips64/alt_stub.S */ 9861/* 9862 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9863 * any interesting requests and then jump to the real instruction 9864 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9865 */ 9866 .extern MterpCheckBefore 9867 REFRESH_IBASE 9868 dla ra, artMterpAsmInstructionStart 9869 dla t9, MterpCheckBefore 9870 move a0, rSELF 9871 daddu a1, rFP, OFF_FP_SHADOWFRAME 9872 move a2, rPC 9873 daddu ra, ra, (141 * 128) # Addr of primary handler. 9874 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 9875 9876/* ------------------------------ */ 9877 .balign 128 9878.L_ALT_op_int_to_char: /* 0x8e */ 9879/* File: mips64/alt_stub.S */ 9880/* 9881 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9882 * any interesting requests and then jump to the real instruction 9883 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9884 */ 9885 .extern MterpCheckBefore 9886 REFRESH_IBASE 9887 dla ra, artMterpAsmInstructionStart 9888 dla t9, MterpCheckBefore 9889 move a0, rSELF 9890 daddu a1, rFP, OFF_FP_SHADOWFRAME 9891 move a2, rPC 9892 daddu ra, ra, (142 * 128) # Addr of primary handler. 9893 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 9894 9895/* ------------------------------ */ 9896 .balign 128 9897.L_ALT_op_int_to_short: /* 0x8f */ 9898/* File: mips64/alt_stub.S */ 9899/* 9900 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9901 * any interesting requests and then jump to the real instruction 9902 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9903 */ 9904 .extern MterpCheckBefore 9905 REFRESH_IBASE 9906 dla ra, artMterpAsmInstructionStart 9907 dla t9, MterpCheckBefore 9908 move a0, rSELF 9909 daddu a1, rFP, OFF_FP_SHADOWFRAME 9910 move a2, rPC 9911 daddu ra, ra, (143 * 128) # Addr of primary handler. 9912 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 9913 9914/* ------------------------------ */ 9915 .balign 128 9916.L_ALT_op_add_int: /* 0x90 */ 9917/* File: mips64/alt_stub.S */ 9918/* 9919 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9920 * any interesting requests and then jump to the real instruction 9921 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9922 */ 9923 .extern MterpCheckBefore 9924 REFRESH_IBASE 9925 dla ra, artMterpAsmInstructionStart 9926 dla t9, MterpCheckBefore 9927 move a0, rSELF 9928 daddu a1, rFP, OFF_FP_SHADOWFRAME 9929 move a2, rPC 9930 daddu ra, ra, (144 * 128) # Addr of primary handler. 9931 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 9932 9933/* ------------------------------ */ 9934 .balign 128 9935.L_ALT_op_sub_int: /* 0x91 */ 9936/* File: mips64/alt_stub.S */ 9937/* 9938 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9939 * any interesting requests and then jump to the real instruction 9940 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9941 */ 9942 .extern MterpCheckBefore 9943 REFRESH_IBASE 9944 dla ra, artMterpAsmInstructionStart 9945 dla t9, MterpCheckBefore 9946 move a0, rSELF 9947 daddu a1, rFP, OFF_FP_SHADOWFRAME 9948 move a2, rPC 9949 daddu ra, ra, (145 * 128) # Addr of primary handler. 9950 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 9951 9952/* ------------------------------ */ 9953 .balign 128 9954.L_ALT_op_mul_int: /* 0x92 */ 9955/* File: mips64/alt_stub.S */ 9956/* 9957 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9958 * any interesting requests and then jump to the real instruction 9959 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9960 */ 9961 .extern MterpCheckBefore 9962 REFRESH_IBASE 9963 dla ra, artMterpAsmInstructionStart 9964 dla t9, MterpCheckBefore 9965 move a0, rSELF 9966 daddu a1, rFP, OFF_FP_SHADOWFRAME 9967 move a2, rPC 9968 daddu ra, ra, (146 * 128) # Addr of primary handler. 9969 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 9970 9971/* ------------------------------ */ 9972 .balign 128 9973.L_ALT_op_div_int: /* 0x93 */ 9974/* File: mips64/alt_stub.S */ 9975/* 9976 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9977 * any interesting requests and then jump to the real instruction 9978 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9979 */ 9980 .extern MterpCheckBefore 9981 REFRESH_IBASE 9982 dla ra, artMterpAsmInstructionStart 9983 dla t9, MterpCheckBefore 9984 move a0, rSELF 9985 daddu a1, rFP, OFF_FP_SHADOWFRAME 9986 move a2, rPC 9987 daddu ra, ra, (147 * 128) # Addr of primary handler. 9988 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 9989 9990/* ------------------------------ */ 9991 .balign 128 9992.L_ALT_op_rem_int: /* 0x94 */ 9993/* File: mips64/alt_stub.S */ 9994/* 9995 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9996 * any interesting requests and then jump to the real instruction 9997 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9998 */ 9999 .extern MterpCheckBefore 10000 REFRESH_IBASE 10001 dla ra, artMterpAsmInstructionStart 10002 dla t9, MterpCheckBefore 10003 move a0, rSELF 10004 daddu a1, rFP, OFF_FP_SHADOWFRAME 10005 move a2, rPC 10006 daddu ra, ra, (148 * 128) # Addr of primary handler. 10007 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 10008 10009/* ------------------------------ */ 10010 .balign 128 10011.L_ALT_op_and_int: /* 0x95 */ 10012/* File: mips64/alt_stub.S */ 10013/* 10014 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10015 * any interesting requests and then jump to the real instruction 10016 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10017 */ 10018 .extern MterpCheckBefore 10019 REFRESH_IBASE 10020 dla ra, artMterpAsmInstructionStart 10021 dla t9, MterpCheckBefore 10022 move a0, rSELF 10023 daddu a1, rFP, OFF_FP_SHADOWFRAME 10024 move a2, rPC 10025 daddu ra, ra, (149 * 128) # Addr of primary handler. 10026 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 10027 10028/* ------------------------------ */ 10029 .balign 128 10030.L_ALT_op_or_int: /* 0x96 */ 10031/* File: mips64/alt_stub.S */ 10032/* 10033 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10034 * any interesting requests and then jump to the real instruction 10035 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10036 */ 10037 .extern MterpCheckBefore 10038 REFRESH_IBASE 10039 dla ra, artMterpAsmInstructionStart 10040 dla t9, MterpCheckBefore 10041 move a0, rSELF 10042 daddu a1, rFP, OFF_FP_SHADOWFRAME 10043 move a2, rPC 10044 daddu ra, ra, (150 * 128) # Addr of primary handler. 10045 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 10046 10047/* ------------------------------ */ 10048 .balign 128 10049.L_ALT_op_xor_int: /* 0x97 */ 10050/* File: mips64/alt_stub.S */ 10051/* 10052 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10053 * any interesting requests and then jump to the real instruction 10054 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10055 */ 10056 .extern MterpCheckBefore 10057 REFRESH_IBASE 10058 dla ra, artMterpAsmInstructionStart 10059 dla t9, MterpCheckBefore 10060 move a0, rSELF 10061 daddu a1, rFP, OFF_FP_SHADOWFRAME 10062 move a2, rPC 10063 daddu ra, ra, (151 * 128) # Addr of primary handler. 10064 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 10065 10066/* ------------------------------ */ 10067 .balign 128 10068.L_ALT_op_shl_int: /* 0x98 */ 10069/* File: mips64/alt_stub.S */ 10070/* 10071 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10072 * any interesting requests and then jump to the real instruction 10073 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10074 */ 10075 .extern MterpCheckBefore 10076 REFRESH_IBASE 10077 dla ra, artMterpAsmInstructionStart 10078 dla t9, MterpCheckBefore 10079 move a0, rSELF 10080 daddu a1, rFP, OFF_FP_SHADOWFRAME 10081 move a2, rPC 10082 daddu ra, ra, (152 * 128) # Addr of primary handler. 10083 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 10084 10085/* ------------------------------ */ 10086 .balign 128 10087.L_ALT_op_shr_int: /* 0x99 */ 10088/* File: mips64/alt_stub.S */ 10089/* 10090 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10091 * any interesting requests and then jump to the real instruction 10092 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10093 */ 10094 .extern MterpCheckBefore 10095 REFRESH_IBASE 10096 dla ra, artMterpAsmInstructionStart 10097 dla t9, MterpCheckBefore 10098 move a0, rSELF 10099 daddu a1, rFP, OFF_FP_SHADOWFRAME 10100 move a2, rPC 10101 daddu ra, ra, (153 * 128) # Addr of primary handler. 10102 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 10103 10104/* ------------------------------ */ 10105 .balign 128 10106.L_ALT_op_ushr_int: /* 0x9a */ 10107/* File: mips64/alt_stub.S */ 10108/* 10109 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10110 * any interesting requests and then jump to the real instruction 10111 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10112 */ 10113 .extern MterpCheckBefore 10114 REFRESH_IBASE 10115 dla ra, artMterpAsmInstructionStart 10116 dla t9, MterpCheckBefore 10117 move a0, rSELF 10118 daddu a1, rFP, OFF_FP_SHADOWFRAME 10119 move a2, rPC 10120 daddu ra, ra, (154 * 128) # Addr of primary handler. 10121 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 10122 10123/* ------------------------------ */ 10124 .balign 128 10125.L_ALT_op_add_long: /* 0x9b */ 10126/* File: mips64/alt_stub.S */ 10127/* 10128 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10129 * any interesting requests and then jump to the real instruction 10130 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10131 */ 10132 .extern MterpCheckBefore 10133 REFRESH_IBASE 10134 dla ra, artMterpAsmInstructionStart 10135 dla t9, MterpCheckBefore 10136 move a0, rSELF 10137 daddu a1, rFP, OFF_FP_SHADOWFRAME 10138 move a2, rPC 10139 daddu ra, ra, (155 * 128) # Addr of primary handler. 10140 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 10141 10142/* ------------------------------ */ 10143 .balign 128 10144.L_ALT_op_sub_long: /* 0x9c */ 10145/* File: mips64/alt_stub.S */ 10146/* 10147 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10148 * any interesting requests and then jump to the real instruction 10149 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10150 */ 10151 .extern MterpCheckBefore 10152 REFRESH_IBASE 10153 dla ra, artMterpAsmInstructionStart 10154 dla t9, MterpCheckBefore 10155 move a0, rSELF 10156 daddu a1, rFP, OFF_FP_SHADOWFRAME 10157 move a2, rPC 10158 daddu ra, ra, (156 * 128) # Addr of primary handler. 10159 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 10160 10161/* ------------------------------ */ 10162 .balign 128 10163.L_ALT_op_mul_long: /* 0x9d */ 10164/* File: mips64/alt_stub.S */ 10165/* 10166 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10167 * any interesting requests and then jump to the real instruction 10168 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10169 */ 10170 .extern MterpCheckBefore 10171 REFRESH_IBASE 10172 dla ra, artMterpAsmInstructionStart 10173 dla t9, MterpCheckBefore 10174 move a0, rSELF 10175 daddu a1, rFP, OFF_FP_SHADOWFRAME 10176 move a2, rPC 10177 daddu ra, ra, (157 * 128) # Addr of primary handler. 10178 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 10179 10180/* ------------------------------ */ 10181 .balign 128 10182.L_ALT_op_div_long: /* 0x9e */ 10183/* File: mips64/alt_stub.S */ 10184/* 10185 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10186 * any interesting requests and then jump to the real instruction 10187 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10188 */ 10189 .extern MterpCheckBefore 10190 REFRESH_IBASE 10191 dla ra, artMterpAsmInstructionStart 10192 dla t9, MterpCheckBefore 10193 move a0, rSELF 10194 daddu a1, rFP, OFF_FP_SHADOWFRAME 10195 move a2, rPC 10196 daddu ra, ra, (158 * 128) # Addr of primary handler. 10197 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 10198 10199/* ------------------------------ */ 10200 .balign 128 10201.L_ALT_op_rem_long: /* 0x9f */ 10202/* File: mips64/alt_stub.S */ 10203/* 10204 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10205 * any interesting requests and then jump to the real instruction 10206 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10207 */ 10208 .extern MterpCheckBefore 10209 REFRESH_IBASE 10210 dla ra, artMterpAsmInstructionStart 10211 dla t9, MterpCheckBefore 10212 move a0, rSELF 10213 daddu a1, rFP, OFF_FP_SHADOWFRAME 10214 move a2, rPC 10215 daddu ra, ra, (159 * 128) # Addr of primary handler. 10216 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 10217 10218/* ------------------------------ */ 10219 .balign 128 10220.L_ALT_op_and_long: /* 0xa0 */ 10221/* File: mips64/alt_stub.S */ 10222/* 10223 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10224 * any interesting requests and then jump to the real instruction 10225 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10226 */ 10227 .extern MterpCheckBefore 10228 REFRESH_IBASE 10229 dla ra, artMterpAsmInstructionStart 10230 dla t9, MterpCheckBefore 10231 move a0, rSELF 10232 daddu a1, rFP, OFF_FP_SHADOWFRAME 10233 move a2, rPC 10234 daddu ra, ra, (160 * 128) # Addr of primary handler. 10235 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 10236 10237/* ------------------------------ */ 10238 .balign 128 10239.L_ALT_op_or_long: /* 0xa1 */ 10240/* File: mips64/alt_stub.S */ 10241/* 10242 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10243 * any interesting requests and then jump to the real instruction 10244 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10245 */ 10246 .extern MterpCheckBefore 10247 REFRESH_IBASE 10248 dla ra, artMterpAsmInstructionStart 10249 dla t9, MterpCheckBefore 10250 move a0, rSELF 10251 daddu a1, rFP, OFF_FP_SHADOWFRAME 10252 move a2, rPC 10253 daddu ra, ra, (161 * 128) # Addr of primary handler. 10254 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 10255 10256/* ------------------------------ */ 10257 .balign 128 10258.L_ALT_op_xor_long: /* 0xa2 */ 10259/* File: mips64/alt_stub.S */ 10260/* 10261 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10262 * any interesting requests and then jump to the real instruction 10263 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10264 */ 10265 .extern MterpCheckBefore 10266 REFRESH_IBASE 10267 dla ra, artMterpAsmInstructionStart 10268 dla t9, MterpCheckBefore 10269 move a0, rSELF 10270 daddu a1, rFP, OFF_FP_SHADOWFRAME 10271 move a2, rPC 10272 daddu ra, ra, (162 * 128) # Addr of primary handler. 10273 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 10274 10275/* ------------------------------ */ 10276 .balign 128 10277.L_ALT_op_shl_long: /* 0xa3 */ 10278/* File: mips64/alt_stub.S */ 10279/* 10280 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10281 * any interesting requests and then jump to the real instruction 10282 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10283 */ 10284 .extern MterpCheckBefore 10285 REFRESH_IBASE 10286 dla ra, artMterpAsmInstructionStart 10287 dla t9, MterpCheckBefore 10288 move a0, rSELF 10289 daddu a1, rFP, OFF_FP_SHADOWFRAME 10290 move a2, rPC 10291 daddu ra, ra, (163 * 128) # Addr of primary handler. 10292 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 10293 10294/* ------------------------------ */ 10295 .balign 128 10296.L_ALT_op_shr_long: /* 0xa4 */ 10297/* File: mips64/alt_stub.S */ 10298/* 10299 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10300 * any interesting requests and then jump to the real instruction 10301 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10302 */ 10303 .extern MterpCheckBefore 10304 REFRESH_IBASE 10305 dla ra, artMterpAsmInstructionStart 10306 dla t9, MterpCheckBefore 10307 move a0, rSELF 10308 daddu a1, rFP, OFF_FP_SHADOWFRAME 10309 move a2, rPC 10310 daddu ra, ra, (164 * 128) # Addr of primary handler. 10311 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 10312 10313/* ------------------------------ */ 10314 .balign 128 10315.L_ALT_op_ushr_long: /* 0xa5 */ 10316/* File: mips64/alt_stub.S */ 10317/* 10318 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10319 * any interesting requests and then jump to the real instruction 10320 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10321 */ 10322 .extern MterpCheckBefore 10323 REFRESH_IBASE 10324 dla ra, artMterpAsmInstructionStart 10325 dla t9, MterpCheckBefore 10326 move a0, rSELF 10327 daddu a1, rFP, OFF_FP_SHADOWFRAME 10328 move a2, rPC 10329 daddu ra, ra, (165 * 128) # Addr of primary handler. 10330 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 10331 10332/* ------------------------------ */ 10333 .balign 128 10334.L_ALT_op_add_float: /* 0xa6 */ 10335/* File: mips64/alt_stub.S */ 10336/* 10337 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10338 * any interesting requests and then jump to the real instruction 10339 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10340 */ 10341 .extern MterpCheckBefore 10342 REFRESH_IBASE 10343 dla ra, artMterpAsmInstructionStart 10344 dla t9, MterpCheckBefore 10345 move a0, rSELF 10346 daddu a1, rFP, OFF_FP_SHADOWFRAME 10347 move a2, rPC 10348 daddu ra, ra, (166 * 128) # Addr of primary handler. 10349 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 10350 10351/* ------------------------------ */ 10352 .balign 128 10353.L_ALT_op_sub_float: /* 0xa7 */ 10354/* File: mips64/alt_stub.S */ 10355/* 10356 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10357 * any interesting requests and then jump to the real instruction 10358 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10359 */ 10360 .extern MterpCheckBefore 10361 REFRESH_IBASE 10362 dla ra, artMterpAsmInstructionStart 10363 dla t9, MterpCheckBefore 10364 move a0, rSELF 10365 daddu a1, rFP, OFF_FP_SHADOWFRAME 10366 move a2, rPC 10367 daddu ra, ra, (167 * 128) # Addr of primary handler. 10368 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 10369 10370/* ------------------------------ */ 10371 .balign 128 10372.L_ALT_op_mul_float: /* 0xa8 */ 10373/* File: mips64/alt_stub.S */ 10374/* 10375 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10376 * any interesting requests and then jump to the real instruction 10377 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10378 */ 10379 .extern MterpCheckBefore 10380 REFRESH_IBASE 10381 dla ra, artMterpAsmInstructionStart 10382 dla t9, MterpCheckBefore 10383 move a0, rSELF 10384 daddu a1, rFP, OFF_FP_SHADOWFRAME 10385 move a2, rPC 10386 daddu ra, ra, (168 * 128) # Addr of primary handler. 10387 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 10388 10389/* ------------------------------ */ 10390 .balign 128 10391.L_ALT_op_div_float: /* 0xa9 */ 10392/* File: mips64/alt_stub.S */ 10393/* 10394 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10395 * any interesting requests and then jump to the real instruction 10396 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10397 */ 10398 .extern MterpCheckBefore 10399 REFRESH_IBASE 10400 dla ra, artMterpAsmInstructionStart 10401 dla t9, MterpCheckBefore 10402 move a0, rSELF 10403 daddu a1, rFP, OFF_FP_SHADOWFRAME 10404 move a2, rPC 10405 daddu ra, ra, (169 * 128) # Addr of primary handler. 10406 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 10407 10408/* ------------------------------ */ 10409 .balign 128 10410.L_ALT_op_rem_float: /* 0xaa */ 10411/* File: mips64/alt_stub.S */ 10412/* 10413 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10414 * any interesting requests and then jump to the real instruction 10415 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10416 */ 10417 .extern MterpCheckBefore 10418 REFRESH_IBASE 10419 dla ra, artMterpAsmInstructionStart 10420 dla t9, MterpCheckBefore 10421 move a0, rSELF 10422 daddu a1, rFP, OFF_FP_SHADOWFRAME 10423 move a2, rPC 10424 daddu ra, ra, (170 * 128) # Addr of primary handler. 10425 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 10426 10427/* ------------------------------ */ 10428 .balign 128 10429.L_ALT_op_add_double: /* 0xab */ 10430/* File: mips64/alt_stub.S */ 10431/* 10432 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10433 * any interesting requests and then jump to the real instruction 10434 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10435 */ 10436 .extern MterpCheckBefore 10437 REFRESH_IBASE 10438 dla ra, artMterpAsmInstructionStart 10439 dla t9, MterpCheckBefore 10440 move a0, rSELF 10441 daddu a1, rFP, OFF_FP_SHADOWFRAME 10442 move a2, rPC 10443 daddu ra, ra, (171 * 128) # Addr of primary handler. 10444 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 10445 10446/* ------------------------------ */ 10447 .balign 128 10448.L_ALT_op_sub_double: /* 0xac */ 10449/* File: mips64/alt_stub.S */ 10450/* 10451 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10452 * any interesting requests and then jump to the real instruction 10453 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10454 */ 10455 .extern MterpCheckBefore 10456 REFRESH_IBASE 10457 dla ra, artMterpAsmInstructionStart 10458 dla t9, MterpCheckBefore 10459 move a0, rSELF 10460 daddu a1, rFP, OFF_FP_SHADOWFRAME 10461 move a2, rPC 10462 daddu ra, ra, (172 * 128) # Addr of primary handler. 10463 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 10464 10465/* ------------------------------ */ 10466 .balign 128 10467.L_ALT_op_mul_double: /* 0xad */ 10468/* File: mips64/alt_stub.S */ 10469/* 10470 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10471 * any interesting requests and then jump to the real instruction 10472 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10473 */ 10474 .extern MterpCheckBefore 10475 REFRESH_IBASE 10476 dla ra, artMterpAsmInstructionStart 10477 dla t9, MterpCheckBefore 10478 move a0, rSELF 10479 daddu a1, rFP, OFF_FP_SHADOWFRAME 10480 move a2, rPC 10481 daddu ra, ra, (173 * 128) # Addr of primary handler. 10482 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 10483 10484/* ------------------------------ */ 10485 .balign 128 10486.L_ALT_op_div_double: /* 0xae */ 10487/* File: mips64/alt_stub.S */ 10488/* 10489 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10490 * any interesting requests and then jump to the real instruction 10491 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10492 */ 10493 .extern MterpCheckBefore 10494 REFRESH_IBASE 10495 dla ra, artMterpAsmInstructionStart 10496 dla t9, MterpCheckBefore 10497 move a0, rSELF 10498 daddu a1, rFP, OFF_FP_SHADOWFRAME 10499 move a2, rPC 10500 daddu ra, ra, (174 * 128) # Addr of primary handler. 10501 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 10502 10503/* ------------------------------ */ 10504 .balign 128 10505.L_ALT_op_rem_double: /* 0xaf */ 10506/* File: mips64/alt_stub.S */ 10507/* 10508 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10509 * any interesting requests and then jump to the real instruction 10510 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10511 */ 10512 .extern MterpCheckBefore 10513 REFRESH_IBASE 10514 dla ra, artMterpAsmInstructionStart 10515 dla t9, MterpCheckBefore 10516 move a0, rSELF 10517 daddu a1, rFP, OFF_FP_SHADOWFRAME 10518 move a2, rPC 10519 daddu ra, ra, (175 * 128) # Addr of primary handler. 10520 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 10521 10522/* ------------------------------ */ 10523 .balign 128 10524.L_ALT_op_add_int_2addr: /* 0xb0 */ 10525/* File: mips64/alt_stub.S */ 10526/* 10527 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10528 * any interesting requests and then jump to the real instruction 10529 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10530 */ 10531 .extern MterpCheckBefore 10532 REFRESH_IBASE 10533 dla ra, artMterpAsmInstructionStart 10534 dla t9, MterpCheckBefore 10535 move a0, rSELF 10536 daddu a1, rFP, OFF_FP_SHADOWFRAME 10537 move a2, rPC 10538 daddu ra, ra, (176 * 128) # Addr of primary handler. 10539 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 10540 10541/* ------------------------------ */ 10542 .balign 128 10543.L_ALT_op_sub_int_2addr: /* 0xb1 */ 10544/* File: mips64/alt_stub.S */ 10545/* 10546 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10547 * any interesting requests and then jump to the real instruction 10548 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10549 */ 10550 .extern MterpCheckBefore 10551 REFRESH_IBASE 10552 dla ra, artMterpAsmInstructionStart 10553 dla t9, MterpCheckBefore 10554 move a0, rSELF 10555 daddu a1, rFP, OFF_FP_SHADOWFRAME 10556 move a2, rPC 10557 daddu ra, ra, (177 * 128) # Addr of primary handler. 10558 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 10559 10560/* ------------------------------ */ 10561 .balign 128 10562.L_ALT_op_mul_int_2addr: /* 0xb2 */ 10563/* File: mips64/alt_stub.S */ 10564/* 10565 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10566 * any interesting requests and then jump to the real instruction 10567 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10568 */ 10569 .extern MterpCheckBefore 10570 REFRESH_IBASE 10571 dla ra, artMterpAsmInstructionStart 10572 dla t9, MterpCheckBefore 10573 move a0, rSELF 10574 daddu a1, rFP, OFF_FP_SHADOWFRAME 10575 move a2, rPC 10576 daddu ra, ra, (178 * 128) # Addr of primary handler. 10577 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 10578 10579/* ------------------------------ */ 10580 .balign 128 10581.L_ALT_op_div_int_2addr: /* 0xb3 */ 10582/* File: mips64/alt_stub.S */ 10583/* 10584 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10585 * any interesting requests and then jump to the real instruction 10586 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10587 */ 10588 .extern MterpCheckBefore 10589 REFRESH_IBASE 10590 dla ra, artMterpAsmInstructionStart 10591 dla t9, MterpCheckBefore 10592 move a0, rSELF 10593 daddu a1, rFP, OFF_FP_SHADOWFRAME 10594 move a2, rPC 10595 daddu ra, ra, (179 * 128) # Addr of primary handler. 10596 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 10597 10598/* ------------------------------ */ 10599 .balign 128 10600.L_ALT_op_rem_int_2addr: /* 0xb4 */ 10601/* File: mips64/alt_stub.S */ 10602/* 10603 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10604 * any interesting requests and then jump to the real instruction 10605 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10606 */ 10607 .extern MterpCheckBefore 10608 REFRESH_IBASE 10609 dla ra, artMterpAsmInstructionStart 10610 dla t9, MterpCheckBefore 10611 move a0, rSELF 10612 daddu a1, rFP, OFF_FP_SHADOWFRAME 10613 move a2, rPC 10614 daddu ra, ra, (180 * 128) # Addr of primary handler. 10615 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 10616 10617/* ------------------------------ */ 10618 .balign 128 10619.L_ALT_op_and_int_2addr: /* 0xb5 */ 10620/* File: mips64/alt_stub.S */ 10621/* 10622 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10623 * any interesting requests and then jump to the real instruction 10624 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10625 */ 10626 .extern MterpCheckBefore 10627 REFRESH_IBASE 10628 dla ra, artMterpAsmInstructionStart 10629 dla t9, MterpCheckBefore 10630 move a0, rSELF 10631 daddu a1, rFP, OFF_FP_SHADOWFRAME 10632 move a2, rPC 10633 daddu ra, ra, (181 * 128) # Addr of primary handler. 10634 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 10635 10636/* ------------------------------ */ 10637 .balign 128 10638.L_ALT_op_or_int_2addr: /* 0xb6 */ 10639/* File: mips64/alt_stub.S */ 10640/* 10641 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10642 * any interesting requests and then jump to the real instruction 10643 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10644 */ 10645 .extern MterpCheckBefore 10646 REFRESH_IBASE 10647 dla ra, artMterpAsmInstructionStart 10648 dla t9, MterpCheckBefore 10649 move a0, rSELF 10650 daddu a1, rFP, OFF_FP_SHADOWFRAME 10651 move a2, rPC 10652 daddu ra, ra, (182 * 128) # Addr of primary handler. 10653 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 10654 10655/* ------------------------------ */ 10656 .balign 128 10657.L_ALT_op_xor_int_2addr: /* 0xb7 */ 10658/* File: mips64/alt_stub.S */ 10659/* 10660 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10661 * any interesting requests and then jump to the real instruction 10662 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10663 */ 10664 .extern MterpCheckBefore 10665 REFRESH_IBASE 10666 dla ra, artMterpAsmInstructionStart 10667 dla t9, MterpCheckBefore 10668 move a0, rSELF 10669 daddu a1, rFP, OFF_FP_SHADOWFRAME 10670 move a2, rPC 10671 daddu ra, ra, (183 * 128) # Addr of primary handler. 10672 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 10673 10674/* ------------------------------ */ 10675 .balign 128 10676.L_ALT_op_shl_int_2addr: /* 0xb8 */ 10677/* File: mips64/alt_stub.S */ 10678/* 10679 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10680 * any interesting requests and then jump to the real instruction 10681 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10682 */ 10683 .extern MterpCheckBefore 10684 REFRESH_IBASE 10685 dla ra, artMterpAsmInstructionStart 10686 dla t9, MterpCheckBefore 10687 move a0, rSELF 10688 daddu a1, rFP, OFF_FP_SHADOWFRAME 10689 move a2, rPC 10690 daddu ra, ra, (184 * 128) # Addr of primary handler. 10691 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 10692 10693/* ------------------------------ */ 10694 .balign 128 10695.L_ALT_op_shr_int_2addr: /* 0xb9 */ 10696/* File: mips64/alt_stub.S */ 10697/* 10698 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10699 * any interesting requests and then jump to the real instruction 10700 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10701 */ 10702 .extern MterpCheckBefore 10703 REFRESH_IBASE 10704 dla ra, artMterpAsmInstructionStart 10705 dla t9, MterpCheckBefore 10706 move a0, rSELF 10707 daddu a1, rFP, OFF_FP_SHADOWFRAME 10708 move a2, rPC 10709 daddu ra, ra, (185 * 128) # Addr of primary handler. 10710 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 10711 10712/* ------------------------------ */ 10713 .balign 128 10714.L_ALT_op_ushr_int_2addr: /* 0xba */ 10715/* File: mips64/alt_stub.S */ 10716/* 10717 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10718 * any interesting requests and then jump to the real instruction 10719 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10720 */ 10721 .extern MterpCheckBefore 10722 REFRESH_IBASE 10723 dla ra, artMterpAsmInstructionStart 10724 dla t9, MterpCheckBefore 10725 move a0, rSELF 10726 daddu a1, rFP, OFF_FP_SHADOWFRAME 10727 move a2, rPC 10728 daddu ra, ra, (186 * 128) # Addr of primary handler. 10729 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 10730 10731/* ------------------------------ */ 10732 .balign 128 10733.L_ALT_op_add_long_2addr: /* 0xbb */ 10734/* File: mips64/alt_stub.S */ 10735/* 10736 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10737 * any interesting requests and then jump to the real instruction 10738 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10739 */ 10740 .extern MterpCheckBefore 10741 REFRESH_IBASE 10742 dla ra, artMterpAsmInstructionStart 10743 dla t9, MterpCheckBefore 10744 move a0, rSELF 10745 daddu a1, rFP, OFF_FP_SHADOWFRAME 10746 move a2, rPC 10747 daddu ra, ra, (187 * 128) # Addr of primary handler. 10748 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 10749 10750/* ------------------------------ */ 10751 .balign 128 10752.L_ALT_op_sub_long_2addr: /* 0xbc */ 10753/* File: mips64/alt_stub.S */ 10754/* 10755 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10756 * any interesting requests and then jump to the real instruction 10757 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10758 */ 10759 .extern MterpCheckBefore 10760 REFRESH_IBASE 10761 dla ra, artMterpAsmInstructionStart 10762 dla t9, MterpCheckBefore 10763 move a0, rSELF 10764 daddu a1, rFP, OFF_FP_SHADOWFRAME 10765 move a2, rPC 10766 daddu ra, ra, (188 * 128) # Addr of primary handler. 10767 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 10768 10769/* ------------------------------ */ 10770 .balign 128 10771.L_ALT_op_mul_long_2addr: /* 0xbd */ 10772/* File: mips64/alt_stub.S */ 10773/* 10774 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10775 * any interesting requests and then jump to the real instruction 10776 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10777 */ 10778 .extern MterpCheckBefore 10779 REFRESH_IBASE 10780 dla ra, artMterpAsmInstructionStart 10781 dla t9, MterpCheckBefore 10782 move a0, rSELF 10783 daddu a1, rFP, OFF_FP_SHADOWFRAME 10784 move a2, rPC 10785 daddu ra, ra, (189 * 128) # Addr of primary handler. 10786 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 10787 10788/* ------------------------------ */ 10789 .balign 128 10790.L_ALT_op_div_long_2addr: /* 0xbe */ 10791/* File: mips64/alt_stub.S */ 10792/* 10793 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10794 * any interesting requests and then jump to the real instruction 10795 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10796 */ 10797 .extern MterpCheckBefore 10798 REFRESH_IBASE 10799 dla ra, artMterpAsmInstructionStart 10800 dla t9, MterpCheckBefore 10801 move a0, rSELF 10802 daddu a1, rFP, OFF_FP_SHADOWFRAME 10803 move a2, rPC 10804 daddu ra, ra, (190 * 128) # Addr of primary handler. 10805 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 10806 10807/* ------------------------------ */ 10808 .balign 128 10809.L_ALT_op_rem_long_2addr: /* 0xbf */ 10810/* File: mips64/alt_stub.S */ 10811/* 10812 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10813 * any interesting requests and then jump to the real instruction 10814 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10815 */ 10816 .extern MterpCheckBefore 10817 REFRESH_IBASE 10818 dla ra, artMterpAsmInstructionStart 10819 dla t9, MterpCheckBefore 10820 move a0, rSELF 10821 daddu a1, rFP, OFF_FP_SHADOWFRAME 10822 move a2, rPC 10823 daddu ra, ra, (191 * 128) # Addr of primary handler. 10824 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 10825 10826/* ------------------------------ */ 10827 .balign 128 10828.L_ALT_op_and_long_2addr: /* 0xc0 */ 10829/* File: mips64/alt_stub.S */ 10830/* 10831 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10832 * any interesting requests and then jump to the real instruction 10833 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10834 */ 10835 .extern MterpCheckBefore 10836 REFRESH_IBASE 10837 dla ra, artMterpAsmInstructionStart 10838 dla t9, MterpCheckBefore 10839 move a0, rSELF 10840 daddu a1, rFP, OFF_FP_SHADOWFRAME 10841 move a2, rPC 10842 daddu ra, ra, (192 * 128) # Addr of primary handler. 10843 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 10844 10845/* ------------------------------ */ 10846 .balign 128 10847.L_ALT_op_or_long_2addr: /* 0xc1 */ 10848/* File: mips64/alt_stub.S */ 10849/* 10850 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10851 * any interesting requests and then jump to the real instruction 10852 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10853 */ 10854 .extern MterpCheckBefore 10855 REFRESH_IBASE 10856 dla ra, artMterpAsmInstructionStart 10857 dla t9, MterpCheckBefore 10858 move a0, rSELF 10859 daddu a1, rFP, OFF_FP_SHADOWFRAME 10860 move a2, rPC 10861 daddu ra, ra, (193 * 128) # Addr of primary handler. 10862 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 10863 10864/* ------------------------------ */ 10865 .balign 128 10866.L_ALT_op_xor_long_2addr: /* 0xc2 */ 10867/* File: mips64/alt_stub.S */ 10868/* 10869 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10870 * any interesting requests and then jump to the real instruction 10871 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10872 */ 10873 .extern MterpCheckBefore 10874 REFRESH_IBASE 10875 dla ra, artMterpAsmInstructionStart 10876 dla t9, MterpCheckBefore 10877 move a0, rSELF 10878 daddu a1, rFP, OFF_FP_SHADOWFRAME 10879 move a2, rPC 10880 daddu ra, ra, (194 * 128) # Addr of primary handler. 10881 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 10882 10883/* ------------------------------ */ 10884 .balign 128 10885.L_ALT_op_shl_long_2addr: /* 0xc3 */ 10886/* File: mips64/alt_stub.S */ 10887/* 10888 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10889 * any interesting requests and then jump to the real instruction 10890 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10891 */ 10892 .extern MterpCheckBefore 10893 REFRESH_IBASE 10894 dla ra, artMterpAsmInstructionStart 10895 dla t9, MterpCheckBefore 10896 move a0, rSELF 10897 daddu a1, rFP, OFF_FP_SHADOWFRAME 10898 move a2, rPC 10899 daddu ra, ra, (195 * 128) # Addr of primary handler. 10900 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 10901 10902/* ------------------------------ */ 10903 .balign 128 10904.L_ALT_op_shr_long_2addr: /* 0xc4 */ 10905/* File: mips64/alt_stub.S */ 10906/* 10907 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10908 * any interesting requests and then jump to the real instruction 10909 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10910 */ 10911 .extern MterpCheckBefore 10912 REFRESH_IBASE 10913 dla ra, artMterpAsmInstructionStart 10914 dla t9, MterpCheckBefore 10915 move a0, rSELF 10916 daddu a1, rFP, OFF_FP_SHADOWFRAME 10917 move a2, rPC 10918 daddu ra, ra, (196 * 128) # Addr of primary handler. 10919 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 10920 10921/* ------------------------------ */ 10922 .balign 128 10923.L_ALT_op_ushr_long_2addr: /* 0xc5 */ 10924/* File: mips64/alt_stub.S */ 10925/* 10926 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10927 * any interesting requests and then jump to the real instruction 10928 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10929 */ 10930 .extern MterpCheckBefore 10931 REFRESH_IBASE 10932 dla ra, artMterpAsmInstructionStart 10933 dla t9, MterpCheckBefore 10934 move a0, rSELF 10935 daddu a1, rFP, OFF_FP_SHADOWFRAME 10936 move a2, rPC 10937 daddu ra, ra, (197 * 128) # Addr of primary handler. 10938 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 10939 10940/* ------------------------------ */ 10941 .balign 128 10942.L_ALT_op_add_float_2addr: /* 0xc6 */ 10943/* File: mips64/alt_stub.S */ 10944/* 10945 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10946 * any interesting requests and then jump to the real instruction 10947 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10948 */ 10949 .extern MterpCheckBefore 10950 REFRESH_IBASE 10951 dla ra, artMterpAsmInstructionStart 10952 dla t9, MterpCheckBefore 10953 move a0, rSELF 10954 daddu a1, rFP, OFF_FP_SHADOWFRAME 10955 move a2, rPC 10956 daddu ra, ra, (198 * 128) # Addr of primary handler. 10957 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 10958 10959/* ------------------------------ */ 10960 .balign 128 10961.L_ALT_op_sub_float_2addr: /* 0xc7 */ 10962/* File: mips64/alt_stub.S */ 10963/* 10964 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10965 * any interesting requests and then jump to the real instruction 10966 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10967 */ 10968 .extern MterpCheckBefore 10969 REFRESH_IBASE 10970 dla ra, artMterpAsmInstructionStart 10971 dla t9, MterpCheckBefore 10972 move a0, rSELF 10973 daddu a1, rFP, OFF_FP_SHADOWFRAME 10974 move a2, rPC 10975 daddu ra, ra, (199 * 128) # Addr of primary handler. 10976 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 10977 10978/* ------------------------------ */ 10979 .balign 128 10980.L_ALT_op_mul_float_2addr: /* 0xc8 */ 10981/* File: mips64/alt_stub.S */ 10982/* 10983 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10984 * any interesting requests and then jump to the real instruction 10985 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10986 */ 10987 .extern MterpCheckBefore 10988 REFRESH_IBASE 10989 dla ra, artMterpAsmInstructionStart 10990 dla t9, MterpCheckBefore 10991 move a0, rSELF 10992 daddu a1, rFP, OFF_FP_SHADOWFRAME 10993 move a2, rPC 10994 daddu ra, ra, (200 * 128) # Addr of primary handler. 10995 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 10996 10997/* ------------------------------ */ 10998 .balign 128 10999.L_ALT_op_div_float_2addr: /* 0xc9 */ 11000/* File: mips64/alt_stub.S */ 11001/* 11002 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11003 * any interesting requests and then jump to the real instruction 11004 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11005 */ 11006 .extern MterpCheckBefore 11007 REFRESH_IBASE 11008 dla ra, artMterpAsmInstructionStart 11009 dla t9, MterpCheckBefore 11010 move a0, rSELF 11011 daddu a1, rFP, OFF_FP_SHADOWFRAME 11012 move a2, rPC 11013 daddu ra, ra, (201 * 128) # Addr of primary handler. 11014 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 11015 11016/* ------------------------------ */ 11017 .balign 128 11018.L_ALT_op_rem_float_2addr: /* 0xca */ 11019/* File: mips64/alt_stub.S */ 11020/* 11021 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11022 * any interesting requests and then jump to the real instruction 11023 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11024 */ 11025 .extern MterpCheckBefore 11026 REFRESH_IBASE 11027 dla ra, artMterpAsmInstructionStart 11028 dla t9, MterpCheckBefore 11029 move a0, rSELF 11030 daddu a1, rFP, OFF_FP_SHADOWFRAME 11031 move a2, rPC 11032 daddu ra, ra, (202 * 128) # Addr of primary handler. 11033 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 11034 11035/* ------------------------------ */ 11036 .balign 128 11037.L_ALT_op_add_double_2addr: /* 0xcb */ 11038/* File: mips64/alt_stub.S */ 11039/* 11040 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11041 * any interesting requests and then jump to the real instruction 11042 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11043 */ 11044 .extern MterpCheckBefore 11045 REFRESH_IBASE 11046 dla ra, artMterpAsmInstructionStart 11047 dla t9, MterpCheckBefore 11048 move a0, rSELF 11049 daddu a1, rFP, OFF_FP_SHADOWFRAME 11050 move a2, rPC 11051 daddu ra, ra, (203 * 128) # Addr of primary handler. 11052 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 11053 11054/* ------------------------------ */ 11055 .balign 128 11056.L_ALT_op_sub_double_2addr: /* 0xcc */ 11057/* File: mips64/alt_stub.S */ 11058/* 11059 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11060 * any interesting requests and then jump to the real instruction 11061 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11062 */ 11063 .extern MterpCheckBefore 11064 REFRESH_IBASE 11065 dla ra, artMterpAsmInstructionStart 11066 dla t9, MterpCheckBefore 11067 move a0, rSELF 11068 daddu a1, rFP, OFF_FP_SHADOWFRAME 11069 move a2, rPC 11070 daddu ra, ra, (204 * 128) # Addr of primary handler. 11071 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 11072 11073/* ------------------------------ */ 11074 .balign 128 11075.L_ALT_op_mul_double_2addr: /* 0xcd */ 11076/* File: mips64/alt_stub.S */ 11077/* 11078 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11079 * any interesting requests and then jump to the real instruction 11080 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11081 */ 11082 .extern MterpCheckBefore 11083 REFRESH_IBASE 11084 dla ra, artMterpAsmInstructionStart 11085 dla t9, MterpCheckBefore 11086 move a0, rSELF 11087 daddu a1, rFP, OFF_FP_SHADOWFRAME 11088 move a2, rPC 11089 daddu ra, ra, (205 * 128) # Addr of primary handler. 11090 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 11091 11092/* ------------------------------ */ 11093 .balign 128 11094.L_ALT_op_div_double_2addr: /* 0xce */ 11095/* File: mips64/alt_stub.S */ 11096/* 11097 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11098 * any interesting requests and then jump to the real instruction 11099 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11100 */ 11101 .extern MterpCheckBefore 11102 REFRESH_IBASE 11103 dla ra, artMterpAsmInstructionStart 11104 dla t9, MterpCheckBefore 11105 move a0, rSELF 11106 daddu a1, rFP, OFF_FP_SHADOWFRAME 11107 move a2, rPC 11108 daddu ra, ra, (206 * 128) # Addr of primary handler. 11109 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 11110 11111/* ------------------------------ */ 11112 .balign 128 11113.L_ALT_op_rem_double_2addr: /* 0xcf */ 11114/* File: mips64/alt_stub.S */ 11115/* 11116 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11117 * any interesting requests and then jump to the real instruction 11118 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11119 */ 11120 .extern MterpCheckBefore 11121 REFRESH_IBASE 11122 dla ra, artMterpAsmInstructionStart 11123 dla t9, MterpCheckBefore 11124 move a0, rSELF 11125 daddu a1, rFP, OFF_FP_SHADOWFRAME 11126 move a2, rPC 11127 daddu ra, ra, (207 * 128) # Addr of primary handler. 11128 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 11129 11130/* ------------------------------ */ 11131 .balign 128 11132.L_ALT_op_add_int_lit16: /* 0xd0 */ 11133/* File: mips64/alt_stub.S */ 11134/* 11135 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11136 * any interesting requests and then jump to the real instruction 11137 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11138 */ 11139 .extern MterpCheckBefore 11140 REFRESH_IBASE 11141 dla ra, artMterpAsmInstructionStart 11142 dla t9, MterpCheckBefore 11143 move a0, rSELF 11144 daddu a1, rFP, OFF_FP_SHADOWFRAME 11145 move a2, rPC 11146 daddu ra, ra, (208 * 128) # Addr of primary handler. 11147 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 11148 11149/* ------------------------------ */ 11150 .balign 128 11151.L_ALT_op_rsub_int: /* 0xd1 */ 11152/* File: mips64/alt_stub.S */ 11153/* 11154 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11155 * any interesting requests and then jump to the real instruction 11156 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11157 */ 11158 .extern MterpCheckBefore 11159 REFRESH_IBASE 11160 dla ra, artMterpAsmInstructionStart 11161 dla t9, MterpCheckBefore 11162 move a0, rSELF 11163 daddu a1, rFP, OFF_FP_SHADOWFRAME 11164 move a2, rPC 11165 daddu ra, ra, (209 * 128) # Addr of primary handler. 11166 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 11167 11168/* ------------------------------ */ 11169 .balign 128 11170.L_ALT_op_mul_int_lit16: /* 0xd2 */ 11171/* File: mips64/alt_stub.S */ 11172/* 11173 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11174 * any interesting requests and then jump to the real instruction 11175 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11176 */ 11177 .extern MterpCheckBefore 11178 REFRESH_IBASE 11179 dla ra, artMterpAsmInstructionStart 11180 dla t9, MterpCheckBefore 11181 move a0, rSELF 11182 daddu a1, rFP, OFF_FP_SHADOWFRAME 11183 move a2, rPC 11184 daddu ra, ra, (210 * 128) # Addr of primary handler. 11185 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 11186 11187/* ------------------------------ */ 11188 .balign 128 11189.L_ALT_op_div_int_lit16: /* 0xd3 */ 11190/* File: mips64/alt_stub.S */ 11191/* 11192 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11193 * any interesting requests and then jump to the real instruction 11194 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11195 */ 11196 .extern MterpCheckBefore 11197 REFRESH_IBASE 11198 dla ra, artMterpAsmInstructionStart 11199 dla t9, MterpCheckBefore 11200 move a0, rSELF 11201 daddu a1, rFP, OFF_FP_SHADOWFRAME 11202 move a2, rPC 11203 daddu ra, ra, (211 * 128) # Addr of primary handler. 11204 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 11205 11206/* ------------------------------ */ 11207 .balign 128 11208.L_ALT_op_rem_int_lit16: /* 0xd4 */ 11209/* File: mips64/alt_stub.S */ 11210/* 11211 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11212 * any interesting requests and then jump to the real instruction 11213 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11214 */ 11215 .extern MterpCheckBefore 11216 REFRESH_IBASE 11217 dla ra, artMterpAsmInstructionStart 11218 dla t9, MterpCheckBefore 11219 move a0, rSELF 11220 daddu a1, rFP, OFF_FP_SHADOWFRAME 11221 move a2, rPC 11222 daddu ra, ra, (212 * 128) # Addr of primary handler. 11223 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 11224 11225/* ------------------------------ */ 11226 .balign 128 11227.L_ALT_op_and_int_lit16: /* 0xd5 */ 11228/* File: mips64/alt_stub.S */ 11229/* 11230 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11231 * any interesting requests and then jump to the real instruction 11232 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11233 */ 11234 .extern MterpCheckBefore 11235 REFRESH_IBASE 11236 dla ra, artMterpAsmInstructionStart 11237 dla t9, MterpCheckBefore 11238 move a0, rSELF 11239 daddu a1, rFP, OFF_FP_SHADOWFRAME 11240 move a2, rPC 11241 daddu ra, ra, (213 * 128) # Addr of primary handler. 11242 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 11243 11244/* ------------------------------ */ 11245 .balign 128 11246.L_ALT_op_or_int_lit16: /* 0xd6 */ 11247/* File: mips64/alt_stub.S */ 11248/* 11249 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11250 * any interesting requests and then jump to the real instruction 11251 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11252 */ 11253 .extern MterpCheckBefore 11254 REFRESH_IBASE 11255 dla ra, artMterpAsmInstructionStart 11256 dla t9, MterpCheckBefore 11257 move a0, rSELF 11258 daddu a1, rFP, OFF_FP_SHADOWFRAME 11259 move a2, rPC 11260 daddu ra, ra, (214 * 128) # Addr of primary handler. 11261 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 11262 11263/* ------------------------------ */ 11264 .balign 128 11265.L_ALT_op_xor_int_lit16: /* 0xd7 */ 11266/* File: mips64/alt_stub.S */ 11267/* 11268 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11269 * any interesting requests and then jump to the real instruction 11270 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11271 */ 11272 .extern MterpCheckBefore 11273 REFRESH_IBASE 11274 dla ra, artMterpAsmInstructionStart 11275 dla t9, MterpCheckBefore 11276 move a0, rSELF 11277 daddu a1, rFP, OFF_FP_SHADOWFRAME 11278 move a2, rPC 11279 daddu ra, ra, (215 * 128) # Addr of primary handler. 11280 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 11281 11282/* ------------------------------ */ 11283 .balign 128 11284.L_ALT_op_add_int_lit8: /* 0xd8 */ 11285/* File: mips64/alt_stub.S */ 11286/* 11287 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11288 * any interesting requests and then jump to the real instruction 11289 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11290 */ 11291 .extern MterpCheckBefore 11292 REFRESH_IBASE 11293 dla ra, artMterpAsmInstructionStart 11294 dla t9, MterpCheckBefore 11295 move a0, rSELF 11296 daddu a1, rFP, OFF_FP_SHADOWFRAME 11297 move a2, rPC 11298 daddu ra, ra, (216 * 128) # Addr of primary handler. 11299 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 11300 11301/* ------------------------------ */ 11302 .balign 128 11303.L_ALT_op_rsub_int_lit8: /* 0xd9 */ 11304/* File: mips64/alt_stub.S */ 11305/* 11306 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11307 * any interesting requests and then jump to the real instruction 11308 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11309 */ 11310 .extern MterpCheckBefore 11311 REFRESH_IBASE 11312 dla ra, artMterpAsmInstructionStart 11313 dla t9, MterpCheckBefore 11314 move a0, rSELF 11315 daddu a1, rFP, OFF_FP_SHADOWFRAME 11316 move a2, rPC 11317 daddu ra, ra, (217 * 128) # Addr of primary handler. 11318 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 11319 11320/* ------------------------------ */ 11321 .balign 128 11322.L_ALT_op_mul_int_lit8: /* 0xda */ 11323/* File: mips64/alt_stub.S */ 11324/* 11325 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11326 * any interesting requests and then jump to the real instruction 11327 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11328 */ 11329 .extern MterpCheckBefore 11330 REFRESH_IBASE 11331 dla ra, artMterpAsmInstructionStart 11332 dla t9, MterpCheckBefore 11333 move a0, rSELF 11334 daddu a1, rFP, OFF_FP_SHADOWFRAME 11335 move a2, rPC 11336 daddu ra, ra, (218 * 128) # Addr of primary handler. 11337 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 11338 11339/* ------------------------------ */ 11340 .balign 128 11341.L_ALT_op_div_int_lit8: /* 0xdb */ 11342/* File: mips64/alt_stub.S */ 11343/* 11344 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11345 * any interesting requests and then jump to the real instruction 11346 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11347 */ 11348 .extern MterpCheckBefore 11349 REFRESH_IBASE 11350 dla ra, artMterpAsmInstructionStart 11351 dla t9, MterpCheckBefore 11352 move a0, rSELF 11353 daddu a1, rFP, OFF_FP_SHADOWFRAME 11354 move a2, rPC 11355 daddu ra, ra, (219 * 128) # Addr of primary handler. 11356 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 11357 11358/* ------------------------------ */ 11359 .balign 128 11360.L_ALT_op_rem_int_lit8: /* 0xdc */ 11361/* File: mips64/alt_stub.S */ 11362/* 11363 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11364 * any interesting requests and then jump to the real instruction 11365 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11366 */ 11367 .extern MterpCheckBefore 11368 REFRESH_IBASE 11369 dla ra, artMterpAsmInstructionStart 11370 dla t9, MterpCheckBefore 11371 move a0, rSELF 11372 daddu a1, rFP, OFF_FP_SHADOWFRAME 11373 move a2, rPC 11374 daddu ra, ra, (220 * 128) # Addr of primary handler. 11375 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 11376 11377/* ------------------------------ */ 11378 .balign 128 11379.L_ALT_op_and_int_lit8: /* 0xdd */ 11380/* File: mips64/alt_stub.S */ 11381/* 11382 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11383 * any interesting requests and then jump to the real instruction 11384 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11385 */ 11386 .extern MterpCheckBefore 11387 REFRESH_IBASE 11388 dla ra, artMterpAsmInstructionStart 11389 dla t9, MterpCheckBefore 11390 move a0, rSELF 11391 daddu a1, rFP, OFF_FP_SHADOWFRAME 11392 move a2, rPC 11393 daddu ra, ra, (221 * 128) # Addr of primary handler. 11394 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 11395 11396/* ------------------------------ */ 11397 .balign 128 11398.L_ALT_op_or_int_lit8: /* 0xde */ 11399/* File: mips64/alt_stub.S */ 11400/* 11401 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11402 * any interesting requests and then jump to the real instruction 11403 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11404 */ 11405 .extern MterpCheckBefore 11406 REFRESH_IBASE 11407 dla ra, artMterpAsmInstructionStart 11408 dla t9, MterpCheckBefore 11409 move a0, rSELF 11410 daddu a1, rFP, OFF_FP_SHADOWFRAME 11411 move a2, rPC 11412 daddu ra, ra, (222 * 128) # Addr of primary handler. 11413 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 11414 11415/* ------------------------------ */ 11416 .balign 128 11417.L_ALT_op_xor_int_lit8: /* 0xdf */ 11418/* File: mips64/alt_stub.S */ 11419/* 11420 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11421 * any interesting requests and then jump to the real instruction 11422 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11423 */ 11424 .extern MterpCheckBefore 11425 REFRESH_IBASE 11426 dla ra, artMterpAsmInstructionStart 11427 dla t9, MterpCheckBefore 11428 move a0, rSELF 11429 daddu a1, rFP, OFF_FP_SHADOWFRAME 11430 move a2, rPC 11431 daddu ra, ra, (223 * 128) # Addr of primary handler. 11432 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 11433 11434/* ------------------------------ */ 11435 .balign 128 11436.L_ALT_op_shl_int_lit8: /* 0xe0 */ 11437/* File: mips64/alt_stub.S */ 11438/* 11439 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11440 * any interesting requests and then jump to the real instruction 11441 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11442 */ 11443 .extern MterpCheckBefore 11444 REFRESH_IBASE 11445 dla ra, artMterpAsmInstructionStart 11446 dla t9, MterpCheckBefore 11447 move a0, rSELF 11448 daddu a1, rFP, OFF_FP_SHADOWFRAME 11449 move a2, rPC 11450 daddu ra, ra, (224 * 128) # Addr of primary handler. 11451 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 11452 11453/* ------------------------------ */ 11454 .balign 128 11455.L_ALT_op_shr_int_lit8: /* 0xe1 */ 11456/* File: mips64/alt_stub.S */ 11457/* 11458 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11459 * any interesting requests and then jump to the real instruction 11460 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11461 */ 11462 .extern MterpCheckBefore 11463 REFRESH_IBASE 11464 dla ra, artMterpAsmInstructionStart 11465 dla t9, MterpCheckBefore 11466 move a0, rSELF 11467 daddu a1, rFP, OFF_FP_SHADOWFRAME 11468 move a2, rPC 11469 daddu ra, ra, (225 * 128) # Addr of primary handler. 11470 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 11471 11472/* ------------------------------ */ 11473 .balign 128 11474.L_ALT_op_ushr_int_lit8: /* 0xe2 */ 11475/* File: mips64/alt_stub.S */ 11476/* 11477 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11478 * any interesting requests and then jump to the real instruction 11479 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11480 */ 11481 .extern MterpCheckBefore 11482 REFRESH_IBASE 11483 dla ra, artMterpAsmInstructionStart 11484 dla t9, MterpCheckBefore 11485 move a0, rSELF 11486 daddu a1, rFP, OFF_FP_SHADOWFRAME 11487 move a2, rPC 11488 daddu ra, ra, (226 * 128) # Addr of primary handler. 11489 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 11490 11491/* ------------------------------ */ 11492 .balign 128 11493.L_ALT_op_iget_quick: /* 0xe3 */ 11494/* File: mips64/alt_stub.S */ 11495/* 11496 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11497 * any interesting requests and then jump to the real instruction 11498 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11499 */ 11500 .extern MterpCheckBefore 11501 REFRESH_IBASE 11502 dla ra, artMterpAsmInstructionStart 11503 dla t9, MterpCheckBefore 11504 move a0, rSELF 11505 daddu a1, rFP, OFF_FP_SHADOWFRAME 11506 move a2, rPC 11507 daddu ra, ra, (227 * 128) # Addr of primary handler. 11508 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 11509 11510/* ------------------------------ */ 11511 .balign 128 11512.L_ALT_op_iget_wide_quick: /* 0xe4 */ 11513/* File: mips64/alt_stub.S */ 11514/* 11515 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11516 * any interesting requests and then jump to the real instruction 11517 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11518 */ 11519 .extern MterpCheckBefore 11520 REFRESH_IBASE 11521 dla ra, artMterpAsmInstructionStart 11522 dla t9, MterpCheckBefore 11523 move a0, rSELF 11524 daddu a1, rFP, OFF_FP_SHADOWFRAME 11525 move a2, rPC 11526 daddu ra, ra, (228 * 128) # Addr of primary handler. 11527 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 11528 11529/* ------------------------------ */ 11530 .balign 128 11531.L_ALT_op_iget_object_quick: /* 0xe5 */ 11532/* File: mips64/alt_stub.S */ 11533/* 11534 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11535 * any interesting requests and then jump to the real instruction 11536 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11537 */ 11538 .extern MterpCheckBefore 11539 REFRESH_IBASE 11540 dla ra, artMterpAsmInstructionStart 11541 dla t9, MterpCheckBefore 11542 move a0, rSELF 11543 daddu a1, rFP, OFF_FP_SHADOWFRAME 11544 move a2, rPC 11545 daddu ra, ra, (229 * 128) # Addr of primary handler. 11546 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 11547 11548/* ------------------------------ */ 11549 .balign 128 11550.L_ALT_op_iput_quick: /* 0xe6 */ 11551/* File: mips64/alt_stub.S */ 11552/* 11553 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11554 * any interesting requests and then jump to the real instruction 11555 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11556 */ 11557 .extern MterpCheckBefore 11558 REFRESH_IBASE 11559 dla ra, artMterpAsmInstructionStart 11560 dla t9, MterpCheckBefore 11561 move a0, rSELF 11562 daddu a1, rFP, OFF_FP_SHADOWFRAME 11563 move a2, rPC 11564 daddu ra, ra, (230 * 128) # Addr of primary handler. 11565 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 11566 11567/* ------------------------------ */ 11568 .balign 128 11569.L_ALT_op_iput_wide_quick: /* 0xe7 */ 11570/* File: mips64/alt_stub.S */ 11571/* 11572 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11573 * any interesting requests and then jump to the real instruction 11574 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11575 */ 11576 .extern MterpCheckBefore 11577 REFRESH_IBASE 11578 dla ra, artMterpAsmInstructionStart 11579 dla t9, MterpCheckBefore 11580 move a0, rSELF 11581 daddu a1, rFP, OFF_FP_SHADOWFRAME 11582 move a2, rPC 11583 daddu ra, ra, (231 * 128) # Addr of primary handler. 11584 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 11585 11586/* ------------------------------ */ 11587 .balign 128 11588.L_ALT_op_iput_object_quick: /* 0xe8 */ 11589/* File: mips64/alt_stub.S */ 11590/* 11591 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11592 * any interesting requests and then jump to the real instruction 11593 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11594 */ 11595 .extern MterpCheckBefore 11596 REFRESH_IBASE 11597 dla ra, artMterpAsmInstructionStart 11598 dla t9, MterpCheckBefore 11599 move a0, rSELF 11600 daddu a1, rFP, OFF_FP_SHADOWFRAME 11601 move a2, rPC 11602 daddu ra, ra, (232 * 128) # Addr of primary handler. 11603 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 11604 11605/* ------------------------------ */ 11606 .balign 128 11607.L_ALT_op_invoke_virtual_quick: /* 0xe9 */ 11608/* File: mips64/alt_stub.S */ 11609/* 11610 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11611 * any interesting requests and then jump to the real instruction 11612 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11613 */ 11614 .extern MterpCheckBefore 11615 REFRESH_IBASE 11616 dla ra, artMterpAsmInstructionStart 11617 dla t9, MterpCheckBefore 11618 move a0, rSELF 11619 daddu a1, rFP, OFF_FP_SHADOWFRAME 11620 move a2, rPC 11621 daddu ra, ra, (233 * 128) # Addr of primary handler. 11622 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 11623 11624/* ------------------------------ */ 11625 .balign 128 11626.L_ALT_op_invoke_virtual_range_quick: /* 0xea */ 11627/* File: mips64/alt_stub.S */ 11628/* 11629 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11630 * any interesting requests and then jump to the real instruction 11631 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11632 */ 11633 .extern MterpCheckBefore 11634 REFRESH_IBASE 11635 dla ra, artMterpAsmInstructionStart 11636 dla t9, MterpCheckBefore 11637 move a0, rSELF 11638 daddu a1, rFP, OFF_FP_SHADOWFRAME 11639 move a2, rPC 11640 daddu ra, ra, (234 * 128) # Addr of primary handler. 11641 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 11642 11643/* ------------------------------ */ 11644 .balign 128 11645.L_ALT_op_iput_boolean_quick: /* 0xeb */ 11646/* File: mips64/alt_stub.S */ 11647/* 11648 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11649 * any interesting requests and then jump to the real instruction 11650 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11651 */ 11652 .extern MterpCheckBefore 11653 REFRESH_IBASE 11654 dla ra, artMterpAsmInstructionStart 11655 dla t9, MterpCheckBefore 11656 move a0, rSELF 11657 daddu a1, rFP, OFF_FP_SHADOWFRAME 11658 move a2, rPC 11659 daddu ra, ra, (235 * 128) # Addr of primary handler. 11660 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 11661 11662/* ------------------------------ */ 11663 .balign 128 11664.L_ALT_op_iput_byte_quick: /* 0xec */ 11665/* File: mips64/alt_stub.S */ 11666/* 11667 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11668 * any interesting requests and then jump to the real instruction 11669 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11670 */ 11671 .extern MterpCheckBefore 11672 REFRESH_IBASE 11673 dla ra, artMterpAsmInstructionStart 11674 dla t9, MterpCheckBefore 11675 move a0, rSELF 11676 daddu a1, rFP, OFF_FP_SHADOWFRAME 11677 move a2, rPC 11678 daddu ra, ra, (236 * 128) # Addr of primary handler. 11679 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 11680 11681/* ------------------------------ */ 11682 .balign 128 11683.L_ALT_op_iput_char_quick: /* 0xed */ 11684/* File: mips64/alt_stub.S */ 11685/* 11686 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11687 * any interesting requests and then jump to the real instruction 11688 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11689 */ 11690 .extern MterpCheckBefore 11691 REFRESH_IBASE 11692 dla ra, artMterpAsmInstructionStart 11693 dla t9, MterpCheckBefore 11694 move a0, rSELF 11695 daddu a1, rFP, OFF_FP_SHADOWFRAME 11696 move a2, rPC 11697 daddu ra, ra, (237 * 128) # Addr of primary handler. 11698 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 11699 11700/* ------------------------------ */ 11701 .balign 128 11702.L_ALT_op_iput_short_quick: /* 0xee */ 11703/* File: mips64/alt_stub.S */ 11704/* 11705 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11706 * any interesting requests and then jump to the real instruction 11707 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11708 */ 11709 .extern MterpCheckBefore 11710 REFRESH_IBASE 11711 dla ra, artMterpAsmInstructionStart 11712 dla t9, MterpCheckBefore 11713 move a0, rSELF 11714 daddu a1, rFP, OFF_FP_SHADOWFRAME 11715 move a2, rPC 11716 daddu ra, ra, (238 * 128) # Addr of primary handler. 11717 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 11718 11719/* ------------------------------ */ 11720 .balign 128 11721.L_ALT_op_iget_boolean_quick: /* 0xef */ 11722/* File: mips64/alt_stub.S */ 11723/* 11724 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11725 * any interesting requests and then jump to the real instruction 11726 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11727 */ 11728 .extern MterpCheckBefore 11729 REFRESH_IBASE 11730 dla ra, artMterpAsmInstructionStart 11731 dla t9, MterpCheckBefore 11732 move a0, rSELF 11733 daddu a1, rFP, OFF_FP_SHADOWFRAME 11734 move a2, rPC 11735 daddu ra, ra, (239 * 128) # Addr of primary handler. 11736 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 11737 11738/* ------------------------------ */ 11739 .balign 128 11740.L_ALT_op_iget_byte_quick: /* 0xf0 */ 11741/* File: mips64/alt_stub.S */ 11742/* 11743 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11744 * any interesting requests and then jump to the real instruction 11745 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11746 */ 11747 .extern MterpCheckBefore 11748 REFRESH_IBASE 11749 dla ra, artMterpAsmInstructionStart 11750 dla t9, MterpCheckBefore 11751 move a0, rSELF 11752 daddu a1, rFP, OFF_FP_SHADOWFRAME 11753 move a2, rPC 11754 daddu ra, ra, (240 * 128) # Addr of primary handler. 11755 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 11756 11757/* ------------------------------ */ 11758 .balign 128 11759.L_ALT_op_iget_char_quick: /* 0xf1 */ 11760/* File: mips64/alt_stub.S */ 11761/* 11762 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11763 * any interesting requests and then jump to the real instruction 11764 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11765 */ 11766 .extern MterpCheckBefore 11767 REFRESH_IBASE 11768 dla ra, artMterpAsmInstructionStart 11769 dla t9, MterpCheckBefore 11770 move a0, rSELF 11771 daddu a1, rFP, OFF_FP_SHADOWFRAME 11772 move a2, rPC 11773 daddu ra, ra, (241 * 128) # Addr of primary handler. 11774 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 11775 11776/* ------------------------------ */ 11777 .balign 128 11778.L_ALT_op_iget_short_quick: /* 0xf2 */ 11779/* File: mips64/alt_stub.S */ 11780/* 11781 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11782 * any interesting requests and then jump to the real instruction 11783 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11784 */ 11785 .extern MterpCheckBefore 11786 REFRESH_IBASE 11787 dla ra, artMterpAsmInstructionStart 11788 dla t9, MterpCheckBefore 11789 move a0, rSELF 11790 daddu a1, rFP, OFF_FP_SHADOWFRAME 11791 move a2, rPC 11792 daddu ra, ra, (242 * 128) # Addr of primary handler. 11793 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 11794 11795/* ------------------------------ */ 11796 .balign 128 11797.L_ALT_op_unused_f3: /* 0xf3 */ 11798/* File: mips64/alt_stub.S */ 11799/* 11800 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11801 * any interesting requests and then jump to the real instruction 11802 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11803 */ 11804 .extern MterpCheckBefore 11805 REFRESH_IBASE 11806 dla ra, artMterpAsmInstructionStart 11807 dla t9, MterpCheckBefore 11808 move a0, rSELF 11809 daddu a1, rFP, OFF_FP_SHADOWFRAME 11810 move a2, rPC 11811 daddu ra, ra, (243 * 128) # Addr of primary handler. 11812 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 11813 11814/* ------------------------------ */ 11815 .balign 128 11816.L_ALT_op_unused_f4: /* 0xf4 */ 11817/* File: mips64/alt_stub.S */ 11818/* 11819 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11820 * any interesting requests and then jump to the real instruction 11821 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11822 */ 11823 .extern MterpCheckBefore 11824 REFRESH_IBASE 11825 dla ra, artMterpAsmInstructionStart 11826 dla t9, MterpCheckBefore 11827 move a0, rSELF 11828 daddu a1, rFP, OFF_FP_SHADOWFRAME 11829 move a2, rPC 11830 daddu ra, ra, (244 * 128) # Addr of primary handler. 11831 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 11832 11833/* ------------------------------ */ 11834 .balign 128 11835.L_ALT_op_unused_f5: /* 0xf5 */ 11836/* File: mips64/alt_stub.S */ 11837/* 11838 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11839 * any interesting requests and then jump to the real instruction 11840 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11841 */ 11842 .extern MterpCheckBefore 11843 REFRESH_IBASE 11844 dla ra, artMterpAsmInstructionStart 11845 dla t9, MterpCheckBefore 11846 move a0, rSELF 11847 daddu a1, rFP, OFF_FP_SHADOWFRAME 11848 move a2, rPC 11849 daddu ra, ra, (245 * 128) # Addr of primary handler. 11850 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 11851 11852/* ------------------------------ */ 11853 .balign 128 11854.L_ALT_op_unused_f6: /* 0xf6 */ 11855/* File: mips64/alt_stub.S */ 11856/* 11857 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11858 * any interesting requests and then jump to the real instruction 11859 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11860 */ 11861 .extern MterpCheckBefore 11862 REFRESH_IBASE 11863 dla ra, artMterpAsmInstructionStart 11864 dla t9, MterpCheckBefore 11865 move a0, rSELF 11866 daddu a1, rFP, OFF_FP_SHADOWFRAME 11867 move a2, rPC 11868 daddu ra, ra, (246 * 128) # Addr of primary handler. 11869 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 11870 11871/* ------------------------------ */ 11872 .balign 128 11873.L_ALT_op_unused_f7: /* 0xf7 */ 11874/* File: mips64/alt_stub.S */ 11875/* 11876 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11877 * any interesting requests and then jump to the real instruction 11878 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11879 */ 11880 .extern MterpCheckBefore 11881 REFRESH_IBASE 11882 dla ra, artMterpAsmInstructionStart 11883 dla t9, MterpCheckBefore 11884 move a0, rSELF 11885 daddu a1, rFP, OFF_FP_SHADOWFRAME 11886 move a2, rPC 11887 daddu ra, ra, (247 * 128) # Addr of primary handler. 11888 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 11889 11890/* ------------------------------ */ 11891 .balign 128 11892.L_ALT_op_unused_f8: /* 0xf8 */ 11893/* File: mips64/alt_stub.S */ 11894/* 11895 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11896 * any interesting requests and then jump to the real instruction 11897 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11898 */ 11899 .extern MterpCheckBefore 11900 REFRESH_IBASE 11901 dla ra, artMterpAsmInstructionStart 11902 dla t9, MterpCheckBefore 11903 move a0, rSELF 11904 daddu a1, rFP, OFF_FP_SHADOWFRAME 11905 move a2, rPC 11906 daddu ra, ra, (248 * 128) # Addr of primary handler. 11907 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 11908 11909/* ------------------------------ */ 11910 .balign 128 11911.L_ALT_op_unused_f9: /* 0xf9 */ 11912/* File: mips64/alt_stub.S */ 11913/* 11914 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11915 * any interesting requests and then jump to the real instruction 11916 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11917 */ 11918 .extern MterpCheckBefore 11919 REFRESH_IBASE 11920 dla ra, artMterpAsmInstructionStart 11921 dla t9, MterpCheckBefore 11922 move a0, rSELF 11923 daddu a1, rFP, OFF_FP_SHADOWFRAME 11924 move a2, rPC 11925 daddu ra, ra, (249 * 128) # Addr of primary handler. 11926 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 11927 11928/* ------------------------------ */ 11929 .balign 128 11930.L_ALT_op_invoke_polymorphic: /* 0xfa */ 11931/* File: mips64/alt_stub.S */ 11932/* 11933 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11934 * any interesting requests and then jump to the real instruction 11935 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11936 */ 11937 .extern MterpCheckBefore 11938 REFRESH_IBASE 11939 dla ra, artMterpAsmInstructionStart 11940 dla t9, MterpCheckBefore 11941 move a0, rSELF 11942 daddu a1, rFP, OFF_FP_SHADOWFRAME 11943 move a2, rPC 11944 daddu ra, ra, (250 * 128) # Addr of primary handler. 11945 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 11946 11947/* ------------------------------ */ 11948 .balign 128 11949.L_ALT_op_invoke_polymorphic_range: /* 0xfb */ 11950/* File: mips64/alt_stub.S */ 11951/* 11952 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11953 * any interesting requests and then jump to the real instruction 11954 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11955 */ 11956 .extern MterpCheckBefore 11957 REFRESH_IBASE 11958 dla ra, artMterpAsmInstructionStart 11959 dla t9, MterpCheckBefore 11960 move a0, rSELF 11961 daddu a1, rFP, OFF_FP_SHADOWFRAME 11962 move a2, rPC 11963 daddu ra, ra, (251 * 128) # Addr of primary handler. 11964 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 11965 11966/* ------------------------------ */ 11967 .balign 128 11968.L_ALT_op_invoke_custom: /* 0xfc */ 11969/* File: mips64/alt_stub.S */ 11970/* 11971 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11972 * any interesting requests and then jump to the real instruction 11973 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11974 */ 11975 .extern MterpCheckBefore 11976 REFRESH_IBASE 11977 dla ra, artMterpAsmInstructionStart 11978 dla t9, MterpCheckBefore 11979 move a0, rSELF 11980 daddu a1, rFP, OFF_FP_SHADOWFRAME 11981 move a2, rPC 11982 daddu ra, ra, (252 * 128) # Addr of primary handler. 11983 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 11984 11985/* ------------------------------ */ 11986 .balign 128 11987.L_ALT_op_invoke_custom_range: /* 0xfd */ 11988/* File: mips64/alt_stub.S */ 11989/* 11990 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11991 * any interesting requests and then jump to the real instruction 11992 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11993 */ 11994 .extern MterpCheckBefore 11995 REFRESH_IBASE 11996 dla ra, artMterpAsmInstructionStart 11997 dla t9, MterpCheckBefore 11998 move a0, rSELF 11999 daddu a1, rFP, OFF_FP_SHADOWFRAME 12000 move a2, rPC 12001 daddu ra, ra, (253 * 128) # Addr of primary handler. 12002 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 12003 12004/* ------------------------------ */ 12005 .balign 128 12006.L_ALT_op_unused_fe: /* 0xfe */ 12007/* File: mips64/alt_stub.S */ 12008/* 12009 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 12010 * any interesting requests and then jump to the real instruction 12011 * handler. Note that the call to MterpCheckBefore is done as a tail call. 12012 */ 12013 .extern MterpCheckBefore 12014 REFRESH_IBASE 12015 dla ra, artMterpAsmInstructionStart 12016 dla t9, MterpCheckBefore 12017 move a0, rSELF 12018 daddu a1, rFP, OFF_FP_SHADOWFRAME 12019 move a2, rPC 12020 daddu ra, ra, (254 * 128) # Addr of primary handler. 12021 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 12022 12023/* ------------------------------ */ 12024 .balign 128 12025.L_ALT_op_unused_ff: /* 0xff */ 12026/* File: mips64/alt_stub.S */ 12027/* 12028 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 12029 * any interesting requests and then jump to the real instruction 12030 * handler. Note that the call to MterpCheckBefore is done as a tail call. 12031 */ 12032 .extern MterpCheckBefore 12033 REFRESH_IBASE 12034 dla ra, artMterpAsmInstructionStart 12035 dla t9, MterpCheckBefore 12036 move a0, rSELF 12037 daddu a1, rFP, OFF_FP_SHADOWFRAME 12038 move a2, rPC 12039 daddu ra, ra, (255 * 128) # Addr of primary handler. 12040 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 12041 12042 .balign 128 12043 .size artMterpAsmAltInstructionStart, .-artMterpAsmAltInstructionStart 12044 .global artMterpAsmAltInstructionEnd 12045artMterpAsmAltInstructionEnd: 12046/* File: mips64/footer.S */ 12047/* 12048 * We've detected a condition that will result in an exception, but the exception 12049 * has not yet been thrown. Just bail out to the reference interpreter to deal with it. 12050 * TUNING: for consistency, we may want to just go ahead and handle these here. 12051 */ 12052 12053 .extern MterpLogDivideByZeroException 12054common_errDivideByZero: 12055 EXPORT_PC 12056#if MTERP_LOGGING 12057 move a0, rSELF 12058 daddu a1, rFP, OFF_FP_SHADOWFRAME 12059 jal MterpLogDivideByZeroException 12060#endif 12061 b MterpCommonFallback 12062 12063 .extern MterpLogArrayIndexException 12064common_errArrayIndex: 12065 EXPORT_PC 12066#if MTERP_LOGGING 12067 move a0, rSELF 12068 daddu a1, rFP, OFF_FP_SHADOWFRAME 12069 jal MterpLogArrayIndexException 12070#endif 12071 b MterpCommonFallback 12072 12073 .extern MterpLogNullObjectException 12074common_errNullObject: 12075 EXPORT_PC 12076#if MTERP_LOGGING 12077 move a0, rSELF 12078 daddu a1, rFP, OFF_FP_SHADOWFRAME 12079 jal MterpLogNullObjectException 12080#endif 12081 b MterpCommonFallback 12082 12083/* 12084 * If we're here, something is out of the ordinary. If there is a pending 12085 * exception, handle it. Otherwise, roll back and retry with the reference 12086 * interpreter. 12087 */ 12088MterpPossibleException: 12089 ld a0, THREAD_EXCEPTION_OFFSET(rSELF) 12090 beqzc a0, MterpFallback # If not, fall back to reference interpreter. 12091 /* intentional fallthrough - handle pending exception. */ 12092/* 12093 * On return from a runtime helper routine, we've found a pending exception. 12094 * Can we handle it here - or need to bail out to caller? 12095 * 12096 */ 12097 .extern MterpHandleException 12098 .extern MterpShouldSwitchInterpreters 12099MterpException: 12100 move a0, rSELF 12101 daddu a1, rFP, OFF_FP_SHADOWFRAME 12102 jal MterpHandleException # (self, shadow_frame) 12103 beqzc v0, MterpExceptionReturn # no local catch, back to caller. 12104 ld a0, OFF_FP_CODE_ITEM(rFP) 12105 lwu a1, OFF_FP_DEX_PC(rFP) 12106 REFRESH_IBASE 12107 daddu rPC, a0, CODEITEM_INSNS_OFFSET 12108 dlsa rPC, a1, rPC, 1 # generate new dex_pc_ptr 12109 /* Do we need to switch interpreters? */ 12110 jal MterpShouldSwitchInterpreters 12111 bnezc v0, MterpFallback 12112 /* resume execution at catch block */ 12113 EXPORT_PC 12114 FETCH_INST 12115 GET_INST_OPCODE v0 12116 GOTO_OPCODE v0 12117 /* NOTE: no fallthrough */ 12118 12119/* 12120 * Common handling for branches with support for Jit profiling. 12121 * On entry: 12122 * rINST <= signed offset 12123 * rPROFILE <= signed hotness countdown (expanded to 64 bits) 12124 * 12125 * We have quite a few different cases for branch profiling, OSR detection and 12126 * suspend check support here. 12127 * 12128 * Taken backward branches: 12129 * If profiling active, do hotness countdown and report if we hit zero. 12130 * If in osr check mode, see if our target is a compiled loop header entry and do OSR if so. 12131 * Is there a pending suspend request? If so, suspend. 12132 * 12133 * Taken forward branches and not-taken backward branches: 12134 * If in osr check mode, see if our target is a compiled loop header entry and do OSR if so. 12135 * 12136 * Our most common case is expected to be a taken backward branch with active jit profiling, 12137 * but no full OSR check and no pending suspend request. 12138 * Next most common case is not-taken branch with no full OSR check. 12139 * 12140 */ 12141MterpCommonTakenBranchNoFlags: 12142 bgtzc rINST, .L_forward_branch # don't add forward branches to hotness 12143/* 12144 * We need to subtract 1 from positive values and we should not see 0 here, 12145 * so we may use the result of the comparison with -1. 12146 */ 12147 li v0, JIT_CHECK_OSR 12148 beqc rPROFILE, v0, .L_osr_check 12149 bltc rPROFILE, v0, .L_resume_backward_branch 12150 dsubu rPROFILE, 1 12151 beqzc rPROFILE, .L_add_batch # counted down to zero - report 12152.L_resume_backward_branch: 12153 lw ra, THREAD_FLAGS_OFFSET(rSELF) 12154 REFRESH_IBASE 12155 daddu a2, rINST, rINST # a2<- byte offset 12156 FETCH_ADVANCE_INST_RB a2 # update rPC, load rINST 12157 and ra, THREAD_SUSPEND_OR_CHECKPOINT_REQUEST 12158 bnezc ra, .L_suspend_request_pending 12159 GET_INST_OPCODE v0 # extract opcode from rINST 12160 GOTO_OPCODE v0 # jump to next instruction 12161 12162.L_suspend_request_pending: 12163 EXPORT_PC 12164 move a0, rSELF 12165 jal MterpSuspendCheck # (self) 12166 bnezc v0, MterpFallback 12167 REFRESH_IBASE # might have changed during suspend 12168 GET_INST_OPCODE v0 # extract opcode from rINST 12169 GOTO_OPCODE v0 # jump to next instruction 12170 12171.L_no_count_backwards: 12172 li v0, JIT_CHECK_OSR # check for possible OSR re-entry 12173 bnec rPROFILE, v0, .L_resume_backward_branch 12174.L_osr_check: 12175 move a0, rSELF 12176 daddu a1, rFP, OFF_FP_SHADOWFRAME 12177 move a2, rINST 12178 EXPORT_PC 12179 jal MterpMaybeDoOnStackReplacement # (self, shadow_frame, offset) 12180 bnezc v0, MterpOnStackReplacement 12181 b .L_resume_backward_branch 12182 12183.L_forward_branch: 12184 li v0, JIT_CHECK_OSR # check for possible OSR re-entry 12185 beqc rPROFILE, v0, .L_check_osr_forward 12186.L_resume_forward_branch: 12187 daddu a2, rINST, rINST # a2<- byte offset 12188 FETCH_ADVANCE_INST_RB a2 # update rPC, load rINST 12189 GET_INST_OPCODE v0 # extract opcode from rINST 12190 GOTO_OPCODE v0 # jump to next instruction 12191 12192.L_check_osr_forward: 12193 move a0, rSELF 12194 daddu a1, rFP, OFF_FP_SHADOWFRAME 12195 move a2, rINST 12196 EXPORT_PC 12197 jal MterpMaybeDoOnStackReplacement # (self, shadow_frame, offset) 12198 bnezc v0, MterpOnStackReplacement 12199 b .L_resume_forward_branch 12200 12201.L_add_batch: 12202 daddu a1, rFP, OFF_FP_SHADOWFRAME 12203 sh rPROFILE, SHADOWFRAME_HOTNESS_COUNTDOWN_OFFSET(a1) 12204 ld a0, OFF_FP_METHOD(rFP) 12205 move a2, rSELF 12206 jal MterpAddHotnessBatch # (method, shadow_frame, self) 12207 move rPROFILE, v0 # restore new hotness countdown to rPROFILE 12208 b .L_no_count_backwards 12209 12210/* 12211 * Entered from the conditional branch handlers when OSR check request active on 12212 * not-taken path. All Dalvik not-taken conditional branch offsets are 2. 12213 */ 12214.L_check_not_taken_osr: 12215 move a0, rSELF 12216 daddu a1, rFP, OFF_FP_SHADOWFRAME 12217 li a2, 2 12218 EXPORT_PC 12219 jal MterpMaybeDoOnStackReplacement # (self, shadow_frame, offset) 12220 bnezc v0, MterpOnStackReplacement 12221 FETCH_ADVANCE_INST 2 12222 GET_INST_OPCODE v0 # extract opcode from rINST 12223 GOTO_OPCODE v0 # jump to next instruction 12224 12225/* 12226 * On-stack replacement has happened, and now we've returned from the compiled method. 12227 */ 12228MterpOnStackReplacement: 12229#if MTERP_LOGGING 12230 move a0, rSELF 12231 daddu a1, rFP, OFF_FP_SHADOWFRAME 12232 move a2, rINST # rINST contains offset 12233 jal MterpLogOSR 12234#endif 12235 li v0, 1 # Signal normal return 12236 b MterpDone 12237 12238/* 12239 * Bail out to reference interpreter. 12240 */ 12241 .extern MterpLogFallback 12242MterpFallback: 12243 EXPORT_PC 12244#if MTERP_LOGGING 12245 move a0, rSELF 12246 daddu a1, rFP, OFF_FP_SHADOWFRAME 12247 jal MterpLogFallback 12248#endif 12249MterpCommonFallback: 12250 li v0, 0 # signal retry with reference interpreter. 12251 b MterpDone 12252 12253/* 12254 * We pushed some registers on the stack in ExecuteMterpImpl, then saved 12255 * SP and RA. Here we restore SP, restore the registers, and then restore 12256 * RA to PC. 12257 * 12258 * On entry: 12259 * uint32_t* rFP (should still be live, pointer to base of vregs) 12260 */ 12261MterpExceptionReturn: 12262 li v0, 1 # signal return to caller. 12263 b MterpDone 12264/* 12265 * Returned value is expected in a0 and if it's not 64-bit, the 32 most 12266 * significant bits of a0 must be zero-extended or sign-extended 12267 * depending on the return type. 12268 */ 12269MterpReturn: 12270 ld a2, OFF_FP_RESULT_REGISTER(rFP) 12271 sd a0, 0(a2) 12272 li v0, 1 # signal return to caller. 12273MterpDone: 12274/* 12275 * At this point, we expect rPROFILE to be non-zero. If negative, hotness is disabled or we're 12276 * checking for OSR. If greater than zero, we might have unreported hotness to register 12277 * (the difference between the ending rPROFILE and the cached hotness counter). rPROFILE 12278 * should only reach zero immediately after a hotness decrement, and is then reset to either 12279 * a negative special state or the new non-zero countdown value. 12280 */ 12281 blez rPROFILE, .L_pop_and_return # if > 0, we may have some counts to report. 12282 12283MterpProfileActive: 12284 move rINST, v0 # stash return value 12285 /* Report cached hotness counts */ 12286 ld a0, OFF_FP_METHOD(rFP) 12287 daddu a1, rFP, OFF_FP_SHADOWFRAME 12288 move a2, rSELF 12289 sh rPROFILE, SHADOWFRAME_HOTNESS_COUNTDOWN_OFFSET(a1) 12290 jal MterpAddHotnessBatch # (method, shadow_frame, self) 12291 move v0, rINST # restore return value 12292 12293.L_pop_and_return: 12294 ld s6, STACK_OFFSET_S6(sp) 12295 .cfi_restore 22 12296 ld s5, STACK_OFFSET_S5(sp) 12297 .cfi_restore 21 12298 ld s4, STACK_OFFSET_S4(sp) 12299 .cfi_restore 20 12300 ld s3, STACK_OFFSET_S3(sp) 12301 .cfi_restore 19 12302 ld s2, STACK_OFFSET_S2(sp) 12303 .cfi_restore 18 12304 ld s1, STACK_OFFSET_S1(sp) 12305 .cfi_restore 17 12306 ld s0, STACK_OFFSET_S0(sp) 12307 .cfi_restore 16 12308 12309 ld ra, STACK_OFFSET_RA(sp) 12310 .cfi_restore 31 12311 12312 ld t8, STACK_OFFSET_GP(sp) 12313 .cpreturn 12314 .cfi_restore 28 12315 12316 .set noreorder 12317 jr ra 12318 daddu sp, sp, STACK_SIZE 12319 .cfi_adjust_cfa_offset -STACK_SIZE 12320 12321 .cfi_endproc 12322 .set reorder 12323 .size ExecuteMterpImpl, .-ExecuteMterpImpl 12324 12325