1 /**************************************************************************** 2 **************************************************************************** 3 *** 4 *** This header was automatically generated from a Linux kernel header 5 *** of the same name, to make information necessary for userspace to 6 *** call into the kernel available to libc. It contains only constants, 7 *** structures, and macros generated from the original header, and thus, 8 *** contains no copyrightable information. 9 *** 10 *** To edit the content of this header, modify the corresponding 11 *** source file (e.g. under external/kernel-headers/original/) then 12 *** run bionic/libc/kernel/tools/update_all.py 13 *** 14 *** Any manual change here will be lost the next time this script will 15 *** be run. You've been warned! 16 *** 17 **************************************************************************** 18 ****************************************************************************/ 19 #ifndef __AMDGPU_DRM_H__ 20 #define __AMDGPU_DRM_H__ 21 #include "drm.h" 22 #ifdef __cplusplus 23 #endif 24 #define DRM_AMDGPU_GEM_CREATE 0x00 25 #define DRM_AMDGPU_GEM_MMAP 0x01 26 #define DRM_AMDGPU_CTX 0x02 27 #define DRM_AMDGPU_BO_LIST 0x03 28 #define DRM_AMDGPU_CS 0x04 29 #define DRM_AMDGPU_INFO 0x05 30 #define DRM_AMDGPU_GEM_METADATA 0x06 31 #define DRM_AMDGPU_GEM_WAIT_IDLE 0x07 32 #define DRM_AMDGPU_GEM_VA 0x08 33 #define DRM_AMDGPU_WAIT_CS 0x09 34 #define DRM_AMDGPU_GEM_OP 0x10 35 #define DRM_AMDGPU_GEM_USERPTR 0x11 36 #define DRM_AMDGPU_WAIT_FENCES 0x12 37 #define DRM_IOCTL_AMDGPU_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_CREATE, union drm_amdgpu_gem_create) 38 #define DRM_IOCTL_AMDGPU_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_MMAP, union drm_amdgpu_gem_mmap) 39 #define DRM_IOCTL_AMDGPU_CTX DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_CTX, union drm_amdgpu_ctx) 40 #define DRM_IOCTL_AMDGPU_BO_LIST DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_BO_LIST, union drm_amdgpu_bo_list) 41 #define DRM_IOCTL_AMDGPU_CS DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_CS, union drm_amdgpu_cs) 42 #define DRM_IOCTL_AMDGPU_INFO DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_INFO, struct drm_amdgpu_info) 43 #define DRM_IOCTL_AMDGPU_GEM_METADATA DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_METADATA, struct drm_amdgpu_gem_metadata) 44 #define DRM_IOCTL_AMDGPU_GEM_WAIT_IDLE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_WAIT_IDLE, union drm_amdgpu_gem_wait_idle) 45 #define DRM_IOCTL_AMDGPU_GEM_VA DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_VA, struct drm_amdgpu_gem_va) 46 #define DRM_IOCTL_AMDGPU_WAIT_CS DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_WAIT_CS, union drm_amdgpu_wait_cs) 47 #define DRM_IOCTL_AMDGPU_GEM_OP DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_OP, struct drm_amdgpu_gem_op) 48 #define DRM_IOCTL_AMDGPU_GEM_USERPTR DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_USERPTR, struct drm_amdgpu_gem_userptr) 49 #define DRM_IOCTL_AMDGPU_WAIT_FENCES DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_WAIT_FENCES, union drm_amdgpu_wait_fences) 50 #define AMDGPU_GEM_DOMAIN_CPU 0x1 51 #define AMDGPU_GEM_DOMAIN_GTT 0x2 52 #define AMDGPU_GEM_DOMAIN_VRAM 0x4 53 #define AMDGPU_GEM_DOMAIN_GDS 0x8 54 #define AMDGPU_GEM_DOMAIN_GWS 0x10 55 #define AMDGPU_GEM_DOMAIN_OA 0x20 56 #define AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED (1 << 0) 57 #define AMDGPU_GEM_CREATE_NO_CPU_ACCESS (1 << 1) 58 #define AMDGPU_GEM_CREATE_CPU_GTT_USWC (1 << 2) 59 #define AMDGPU_GEM_CREATE_VRAM_CLEARED (1 << 3) 60 #define AMDGPU_GEM_CREATE_SHADOW (1 << 4) 61 #define AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS (1 << 5) 62 struct drm_amdgpu_gem_create_in { 63 __u64 bo_size; 64 __u64 alignment; 65 __u64 domains; 66 __u64 domain_flags; 67 }; 68 struct drm_amdgpu_gem_create_out { 69 __u32 handle; 70 __u32 _pad; 71 }; 72 union drm_amdgpu_gem_create { 73 struct drm_amdgpu_gem_create_in in; 74 struct drm_amdgpu_gem_create_out out; 75 }; 76 #define AMDGPU_BO_LIST_OP_CREATE 0 77 #define AMDGPU_BO_LIST_OP_DESTROY 1 78 #define AMDGPU_BO_LIST_OP_UPDATE 2 79 struct drm_amdgpu_bo_list_in { 80 __u32 operation; 81 __u32 list_handle; 82 __u32 bo_number; 83 __u32 bo_info_size; 84 __u64 bo_info_ptr; 85 }; 86 struct drm_amdgpu_bo_list_entry { 87 __u32 bo_handle; 88 __u32 bo_priority; 89 }; 90 struct drm_amdgpu_bo_list_out { 91 __u32 list_handle; 92 __u32 _pad; 93 }; 94 union drm_amdgpu_bo_list { 95 struct drm_amdgpu_bo_list_in in; 96 struct drm_amdgpu_bo_list_out out; 97 }; 98 #define AMDGPU_CTX_OP_ALLOC_CTX 1 99 #define AMDGPU_CTX_OP_FREE_CTX 2 100 #define AMDGPU_CTX_OP_QUERY_STATE 3 101 #define AMDGPU_CTX_NO_RESET 0 102 #define AMDGPU_CTX_GUILTY_RESET 1 103 #define AMDGPU_CTX_INNOCENT_RESET 2 104 #define AMDGPU_CTX_UNKNOWN_RESET 3 105 struct drm_amdgpu_ctx_in { 106 __u32 op; 107 __u32 flags; 108 __u32 ctx_id; 109 __u32 _pad; 110 }; 111 union drm_amdgpu_ctx_out { 112 struct { 113 __u32 ctx_id; 114 __u32 _pad; 115 } alloc; 116 struct { 117 __u64 flags; 118 __u32 hangs; 119 __u32 reset_status; 120 } state; 121 }; 122 union drm_amdgpu_ctx { 123 struct drm_amdgpu_ctx_in in; 124 union drm_amdgpu_ctx_out out; 125 }; 126 #define AMDGPU_GEM_USERPTR_READONLY (1 << 0) 127 #define AMDGPU_GEM_USERPTR_ANONONLY (1 << 1) 128 #define AMDGPU_GEM_USERPTR_VALIDATE (1 << 2) 129 #define AMDGPU_GEM_USERPTR_REGISTER (1 << 3) 130 struct drm_amdgpu_gem_userptr { 131 __u64 addr; 132 __u64 size; 133 __u32 flags; 134 __u32 handle; 135 }; 136 #define AMDGPU_TILING_ARRAY_MODE_SHIFT 0 137 #define AMDGPU_TILING_ARRAY_MODE_MASK 0xf 138 #define AMDGPU_TILING_PIPE_CONFIG_SHIFT 4 139 #define AMDGPU_TILING_PIPE_CONFIG_MASK 0x1f 140 #define AMDGPU_TILING_TILE_SPLIT_SHIFT 9 141 #define AMDGPU_TILING_TILE_SPLIT_MASK 0x7 142 #define AMDGPU_TILING_MICRO_TILE_MODE_SHIFT 12 143 #define AMDGPU_TILING_MICRO_TILE_MODE_MASK 0x7 144 #define AMDGPU_TILING_BANK_WIDTH_SHIFT 15 145 #define AMDGPU_TILING_BANK_WIDTH_MASK 0x3 146 #define AMDGPU_TILING_BANK_HEIGHT_SHIFT 17 147 #define AMDGPU_TILING_BANK_HEIGHT_MASK 0x3 148 #define AMDGPU_TILING_MACRO_TILE_ASPECT_SHIFT 19 149 #define AMDGPU_TILING_MACRO_TILE_ASPECT_MASK 0x3 150 #define AMDGPU_TILING_NUM_BANKS_SHIFT 21 151 #define AMDGPU_TILING_NUM_BANKS_MASK 0x3 152 #define AMDGPU_TILING_SET(field,value) (((value) & AMDGPU_TILING_ ##field ##_MASK) << AMDGPU_TILING_ ##field ##_SHIFT) 153 #define AMDGPU_TILING_GET(value,field) (((value) >> AMDGPU_TILING_ ##field ##_SHIFT) & AMDGPU_TILING_ ##field ##_MASK) 154 #define AMDGPU_GEM_METADATA_OP_SET_METADATA 1 155 #define AMDGPU_GEM_METADATA_OP_GET_METADATA 2 156 struct drm_amdgpu_gem_metadata { 157 __u32 handle; 158 __u32 op; 159 struct { 160 __u64 flags; 161 __u64 tiling_info; 162 __u32 data_size_bytes; 163 __u32 data[64]; 164 } data; 165 }; 166 struct drm_amdgpu_gem_mmap_in { 167 __u32 handle; 168 __u32 _pad; 169 }; 170 struct drm_amdgpu_gem_mmap_out { 171 __u64 addr_ptr; 172 }; 173 union drm_amdgpu_gem_mmap { 174 struct drm_amdgpu_gem_mmap_in in; 175 struct drm_amdgpu_gem_mmap_out out; 176 }; 177 struct drm_amdgpu_gem_wait_idle_in { 178 __u32 handle; 179 __u32 flags; 180 __u64 timeout; 181 }; 182 struct drm_amdgpu_gem_wait_idle_out { 183 __u32 status; 184 __u32 domain; 185 }; 186 union drm_amdgpu_gem_wait_idle { 187 struct drm_amdgpu_gem_wait_idle_in in; 188 struct drm_amdgpu_gem_wait_idle_out out; 189 }; 190 struct drm_amdgpu_wait_cs_in { 191 __u64 handle; 192 __u64 timeout; 193 __u32 ip_type; 194 __u32 ip_instance; 195 __u32 ring; 196 __u32 ctx_id; 197 }; 198 struct drm_amdgpu_wait_cs_out { 199 __u64 status; 200 }; 201 union drm_amdgpu_wait_cs { 202 struct drm_amdgpu_wait_cs_in in; 203 struct drm_amdgpu_wait_cs_out out; 204 }; 205 struct drm_amdgpu_fence { 206 __u32 ctx_id; 207 __u32 ip_type; 208 __u32 ip_instance; 209 __u32 ring; 210 __u64 seq_no; 211 }; 212 struct drm_amdgpu_wait_fences_in { 213 __u64 fences; 214 __u32 fence_count; 215 __u32 wait_all; 216 __u64 timeout_ns; 217 }; 218 struct drm_amdgpu_wait_fences_out { 219 __u32 status; 220 __u32 first_signaled; 221 }; 222 union drm_amdgpu_wait_fences { 223 struct drm_amdgpu_wait_fences_in in; 224 struct drm_amdgpu_wait_fences_out out; 225 }; 226 #define AMDGPU_GEM_OP_GET_GEM_CREATE_INFO 0 227 #define AMDGPU_GEM_OP_SET_PLACEMENT 1 228 struct drm_amdgpu_gem_op { 229 __u32 handle; 230 __u32 op; 231 __u64 value; 232 }; 233 #define AMDGPU_VA_OP_MAP 1 234 #define AMDGPU_VA_OP_UNMAP 2 235 #define AMDGPU_VM_DELAY_UPDATE (1 << 0) 236 #define AMDGPU_VM_PAGE_READABLE (1 << 1) 237 #define AMDGPU_VM_PAGE_WRITEABLE (1 << 2) 238 #define AMDGPU_VM_PAGE_EXECUTABLE (1 << 3) 239 struct drm_amdgpu_gem_va { 240 __u32 handle; 241 __u32 _pad; 242 __u32 operation; 243 __u32 flags; 244 __u64 va_address; 245 __u64 offset_in_bo; 246 __u64 map_size; 247 }; 248 #define AMDGPU_HW_IP_GFX 0 249 #define AMDGPU_HW_IP_COMPUTE 1 250 #define AMDGPU_HW_IP_DMA 2 251 #define AMDGPU_HW_IP_UVD 3 252 #define AMDGPU_HW_IP_VCE 4 253 #define AMDGPU_HW_IP_NUM 5 254 #define AMDGPU_HW_IP_INSTANCE_MAX_COUNT 1 255 #define AMDGPU_CHUNK_ID_IB 0x01 256 #define AMDGPU_CHUNK_ID_FENCE 0x02 257 #define AMDGPU_CHUNK_ID_DEPENDENCIES 0x03 258 struct drm_amdgpu_cs_chunk { 259 __u32 chunk_id; 260 __u32 length_dw; 261 __u64 chunk_data; 262 }; 263 struct drm_amdgpu_cs_in { 264 __u32 ctx_id; 265 __u32 bo_list_handle; 266 __u32 num_chunks; 267 __u32 _pad; 268 __u64 chunks; 269 }; 270 struct drm_amdgpu_cs_out { 271 __u64 handle; 272 }; 273 union drm_amdgpu_cs { 274 struct drm_amdgpu_cs_in in; 275 struct drm_amdgpu_cs_out out; 276 }; 277 #define AMDGPU_IB_FLAG_CE (1 << 0) 278 #define AMDGPU_IB_FLAG_PREAMBLE (1 << 1) 279 struct drm_amdgpu_cs_chunk_ib { 280 __u32 _pad; 281 __u32 flags; 282 __u64 va_start; 283 __u32 ib_bytes; 284 __u32 ip_type; 285 __u32 ip_instance; 286 __u32 ring; 287 }; 288 struct drm_amdgpu_cs_chunk_dep { 289 __u32 ip_type; 290 __u32 ip_instance; 291 __u32 ring; 292 __u32 ctx_id; 293 __u64 handle; 294 }; 295 struct drm_amdgpu_cs_chunk_fence { 296 __u32 handle; 297 __u32 offset; 298 }; 299 struct drm_amdgpu_cs_chunk_data { 300 union { 301 struct drm_amdgpu_cs_chunk_ib ib_data; 302 struct drm_amdgpu_cs_chunk_fence fence_data; 303 }; 304 }; 305 #define AMDGPU_IDS_FLAGS_FUSION 0x1 306 #define AMDGPU_IDS_FLAGS_PREEMPTION 0x2 307 #define AMDGPU_INFO_ACCEL_WORKING 0x00 308 #define AMDGPU_INFO_CRTC_FROM_ID 0x01 309 #define AMDGPU_INFO_HW_IP_INFO 0x02 310 #define AMDGPU_INFO_HW_IP_COUNT 0x03 311 #define AMDGPU_INFO_TIMESTAMP 0x05 312 #define AMDGPU_INFO_FW_VERSION 0x0e 313 #define AMDGPU_INFO_FW_VCE 0x1 314 #define AMDGPU_INFO_FW_UVD 0x2 315 #define AMDGPU_INFO_FW_GMC 0x03 316 #define AMDGPU_INFO_FW_GFX_ME 0x04 317 #define AMDGPU_INFO_FW_GFX_PFP 0x05 318 #define AMDGPU_INFO_FW_GFX_CE 0x06 319 #define AMDGPU_INFO_FW_GFX_RLC 0x07 320 #define AMDGPU_INFO_FW_GFX_MEC 0x08 321 #define AMDGPU_INFO_FW_SMC 0x0a 322 #define AMDGPU_INFO_FW_SDMA 0x0b 323 #define AMDGPU_INFO_NUM_BYTES_MOVED 0x0f 324 #define AMDGPU_INFO_VRAM_USAGE 0x10 325 #define AMDGPU_INFO_GTT_USAGE 0x11 326 #define AMDGPU_INFO_GDS_CONFIG 0x13 327 #define AMDGPU_INFO_VRAM_GTT 0x14 328 #define AMDGPU_INFO_READ_MMR_REG 0x15 329 #define AMDGPU_INFO_DEV_INFO 0x16 330 #define AMDGPU_INFO_VIS_VRAM_USAGE 0x17 331 #define AMDGPU_INFO_NUM_EVICTIONS 0x18 332 #define AMDGPU_INFO_MEMORY 0x19 333 #define AMDGPU_INFO_VCE_CLOCK_TABLE 0x1A 334 #define AMDGPU_INFO_VBIOS 0x1B 335 #define AMDGPU_INFO_VBIOS_SIZE 0x1 336 #define AMDGPU_INFO_VBIOS_IMAGE 0x2 337 #define AMDGPU_INFO_MMR_SE_INDEX_SHIFT 0 338 #define AMDGPU_INFO_MMR_SE_INDEX_MASK 0xff 339 #define AMDGPU_INFO_MMR_SH_INDEX_SHIFT 8 340 #define AMDGPU_INFO_MMR_SH_INDEX_MASK 0xff 341 struct drm_amdgpu_query_fw { 342 __u32 fw_type; 343 __u32 ip_instance; 344 __u32 index; 345 __u32 _pad; 346 }; 347 struct drm_amdgpu_info { 348 __u64 return_pointer; 349 __u32 return_size; 350 __u32 query; 351 union { 352 struct { 353 __u32 id; 354 __u32 _pad; 355 } mode_crtc; 356 struct { 357 __u32 type; 358 __u32 ip_instance; 359 } query_hw_ip; 360 struct { 361 __u32 dword_offset; 362 __u32 count; 363 __u32 instance; 364 __u32 flags; 365 } read_mmr_reg; 366 struct drm_amdgpu_query_fw query_fw; 367 struct { 368 __u32 type; 369 __u32 offset; 370 } vbios_info; 371 }; 372 }; 373 struct drm_amdgpu_info_gds { 374 __u32 gds_gfx_partition_size; 375 __u32 compute_partition_size; 376 __u32 gds_total_size; 377 __u32 gws_per_gfx_partition; 378 __u32 gws_per_compute_partition; 379 __u32 oa_per_gfx_partition; 380 __u32 oa_per_compute_partition; 381 __u32 _pad; 382 }; 383 struct drm_amdgpu_info_vram_gtt { 384 __u64 vram_size; 385 __u64 vram_cpu_accessible_size; 386 __u64 gtt_size; 387 }; 388 struct drm_amdgpu_heap_info { 389 __u64 total_heap_size; 390 __u64 usable_heap_size; 391 __u64 heap_usage; 392 __u64 max_allocation; 393 }; 394 struct drm_amdgpu_memory_info { 395 struct drm_amdgpu_heap_info vram; 396 struct drm_amdgpu_heap_info cpu_accessible_vram; 397 struct drm_amdgpu_heap_info gtt; 398 }; 399 struct drm_amdgpu_info_firmware { 400 __u32 ver; 401 __u32 feature; 402 }; 403 #define AMDGPU_VRAM_TYPE_UNKNOWN 0 404 #define AMDGPU_VRAM_TYPE_GDDR1 1 405 #define AMDGPU_VRAM_TYPE_DDR2 2 406 #define AMDGPU_VRAM_TYPE_GDDR3 3 407 #define AMDGPU_VRAM_TYPE_GDDR4 4 408 #define AMDGPU_VRAM_TYPE_GDDR5 5 409 #define AMDGPU_VRAM_TYPE_HBM 6 410 #define AMDGPU_VRAM_TYPE_DDR3 7 411 struct drm_amdgpu_info_device { 412 __u32 device_id; 413 __u32 chip_rev; 414 __u32 external_rev; 415 __u32 pci_rev; 416 __u32 family; 417 __u32 num_shader_engines; 418 __u32 num_shader_arrays_per_engine; 419 __u32 gpu_counter_freq; 420 __u64 max_engine_clock; 421 __u64 max_memory_clock; 422 __u32 cu_active_number; 423 __u32 cu_ao_mask; 424 __u32 cu_bitmap[4][4]; 425 __u32 enabled_rb_pipes_mask; 426 __u32 num_rb_pipes; 427 __u32 num_hw_gfx_contexts; 428 __u32 _pad; 429 __u64 ids_flags; 430 __u64 virtual_address_offset; 431 __u64 virtual_address_max; 432 __u32 virtual_address_alignment; 433 __u32 pte_fragment_size; 434 __u32 gart_page_size; 435 __u32 ce_ram_size; 436 __u32 vram_type; 437 __u32 vram_bit_width; 438 __u32 vce_harvest_config; 439 }; 440 struct drm_amdgpu_info_hw_ip { 441 __u32 hw_ip_version_major; 442 __u32 hw_ip_version_minor; 443 __u64 capabilities_flags; 444 __u32 ib_start_alignment; 445 __u32 ib_size_alignment; 446 __u32 available_rings; 447 __u32 _pad; 448 }; 449 #define AMDGPU_VCE_CLOCK_TABLE_ENTRIES 6 450 struct drm_amdgpu_info_vce_clock_table_entry { 451 __u32 sclk; 452 __u32 mclk; 453 __u32 eclk; 454 __u32 pad; 455 }; 456 struct drm_amdgpu_info_vce_clock_table { 457 struct drm_amdgpu_info_vce_clock_table_entry entries[AMDGPU_VCE_CLOCK_TABLE_ENTRIES]; 458 __u32 num_valid_entries; 459 __u32 pad; 460 }; 461 #define AMDGPU_FAMILY_UNKNOWN 0 462 #define AMDGPU_FAMILY_SI 110 463 #define AMDGPU_FAMILY_CI 120 464 #define AMDGPU_FAMILY_KV 125 465 #define AMDGPU_FAMILY_VI 130 466 #define AMDGPU_FAMILY_CZ 135 467 #ifdef __cplusplus 468 #endif 469 #endif 470