1 /**************************************************************************** 2 **************************************************************************** 3 *** 4 *** This header was automatically generated from a Linux kernel header 5 *** of the same name, to make information necessary for userspace to 6 *** call into the kernel available to libc. It contains only constants, 7 *** structures, and macros generated from the original header, and thus, 8 *** contains no copyrightable information. 9 *** 10 *** To edit the content of this header, modify the corresponding 11 *** source file (e.g. under external/kernel-headers/original/) then 12 *** run bionic/libc/kernel/tools/update_all.py 13 *** 14 *** Any manual change here will be lost the next time this script will 15 *** be run. You've been warned! 16 *** 17 **************************************************************************** 18 ****************************************************************************/ 19 #ifndef __ETNAVIV_DRM_H__ 20 #define __ETNAVIV_DRM_H__ 21 #include "drm.h" 22 #ifdef __cplusplus 23 #endif 24 struct drm_etnaviv_timespec { 25 __s64 tv_sec; 26 __s64 tv_nsec; 27 }; 28 #define ETNAVIV_PARAM_GPU_MODEL 0x01 29 #define ETNAVIV_PARAM_GPU_REVISION 0x02 30 #define ETNAVIV_PARAM_GPU_FEATURES_0 0x03 31 #define ETNAVIV_PARAM_GPU_FEATURES_1 0x04 32 #define ETNAVIV_PARAM_GPU_FEATURES_2 0x05 33 #define ETNAVIV_PARAM_GPU_FEATURES_3 0x06 34 #define ETNAVIV_PARAM_GPU_FEATURES_4 0x07 35 #define ETNAVIV_PARAM_GPU_FEATURES_5 0x08 36 #define ETNAVIV_PARAM_GPU_FEATURES_6 0x09 37 #define ETNAVIV_PARAM_GPU_STREAM_COUNT 0x10 38 #define ETNAVIV_PARAM_GPU_REGISTER_MAX 0x11 39 #define ETNAVIV_PARAM_GPU_THREAD_COUNT 0x12 40 #define ETNAVIV_PARAM_GPU_VERTEX_CACHE_SIZE 0x13 41 #define ETNAVIV_PARAM_GPU_SHADER_CORE_COUNT 0x14 42 #define ETNAVIV_PARAM_GPU_PIXEL_PIPES 0x15 43 #define ETNAVIV_PARAM_GPU_VERTEX_OUTPUT_BUFFER_SIZE 0x16 44 #define ETNAVIV_PARAM_GPU_BUFFER_SIZE 0x17 45 #define ETNAVIV_PARAM_GPU_INSTRUCTION_COUNT 0x18 46 #define ETNAVIV_PARAM_GPU_NUM_CONSTANTS 0x19 47 #define ETNAVIV_PARAM_GPU_NUM_VARYINGS 0x1a 48 #define ETNA_MAX_PIPES 4 49 struct drm_etnaviv_param { 50 __u32 pipe; 51 __u32 param; 52 __u64 value; 53 }; 54 #define ETNA_BO_CACHE_MASK 0x000f0000 55 #define ETNA_BO_CACHED 0x00010000 56 #define ETNA_BO_WC 0x00020000 57 #define ETNA_BO_UNCACHED 0x00040000 58 #define ETNA_BO_FORCE_MMU 0x00100000 59 struct drm_etnaviv_gem_new { 60 __u64 size; 61 __u32 flags; 62 __u32 handle; 63 }; 64 struct drm_etnaviv_gem_info { 65 __u32 handle; 66 __u32 pad; 67 __u64 offset; 68 }; 69 #define ETNA_PREP_READ 0x01 70 #define ETNA_PREP_WRITE 0x02 71 #define ETNA_PREP_NOSYNC 0x04 72 struct drm_etnaviv_gem_cpu_prep { 73 __u32 handle; 74 __u32 op; 75 struct drm_etnaviv_timespec timeout; 76 }; 77 struct drm_etnaviv_gem_cpu_fini { 78 __u32 handle; 79 __u32 flags; 80 }; 81 struct drm_etnaviv_gem_submit_reloc { 82 __u32 submit_offset; 83 __u32 reloc_idx; 84 __u64 reloc_offset; 85 __u32 flags; 86 }; 87 #define ETNA_SUBMIT_BO_READ 0x0001 88 #define ETNA_SUBMIT_BO_WRITE 0x0002 89 struct drm_etnaviv_gem_submit_bo { 90 __u32 flags; 91 __u32 handle; 92 __u64 presumed; 93 }; 94 #define ETNA_PIPE_3D 0x00 95 #define ETNA_PIPE_2D 0x01 96 #define ETNA_PIPE_VG 0x02 97 struct drm_etnaviv_gem_submit { 98 __u32 fence; 99 __u32 pipe; 100 __u32 exec_state; 101 __u32 nr_bos; 102 __u32 nr_relocs; 103 __u32 stream_size; 104 __u64 bos; 105 __u64 relocs; 106 __u64 stream; 107 }; 108 #define ETNA_WAIT_NONBLOCK 0x01 109 struct drm_etnaviv_wait_fence { 110 __u32 pipe; 111 __u32 fence; 112 __u32 flags; 113 __u32 pad; 114 struct drm_etnaviv_timespec timeout; 115 }; 116 #define ETNA_USERPTR_READ 0x01 117 #define ETNA_USERPTR_WRITE 0x02 118 struct drm_etnaviv_gem_userptr { 119 __u64 user_ptr; 120 __u64 user_size; 121 __u32 flags; 122 __u32 handle; 123 }; 124 struct drm_etnaviv_gem_wait { 125 __u32 pipe; 126 __u32 handle; 127 __u32 flags; 128 __u32 pad; 129 struct drm_etnaviv_timespec timeout; 130 }; 131 #define DRM_ETNAVIV_GET_PARAM 0x00 132 #define DRM_ETNAVIV_GEM_NEW 0x02 133 #define DRM_ETNAVIV_GEM_INFO 0x03 134 #define DRM_ETNAVIV_GEM_CPU_PREP 0x04 135 #define DRM_ETNAVIV_GEM_CPU_FINI 0x05 136 #define DRM_ETNAVIV_GEM_SUBMIT 0x06 137 #define DRM_ETNAVIV_WAIT_FENCE 0x07 138 #define DRM_ETNAVIV_GEM_USERPTR 0x08 139 #define DRM_ETNAVIV_GEM_WAIT 0x09 140 #define DRM_ETNAVIV_NUM_IOCTLS 0x0a 141 #define DRM_IOCTL_ETNAVIV_GET_PARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_ETNAVIV_GET_PARAM, struct drm_etnaviv_param) 142 #define DRM_IOCTL_ETNAVIV_GEM_NEW DRM_IOWR(DRM_COMMAND_BASE + DRM_ETNAVIV_GEM_NEW, struct drm_etnaviv_gem_new) 143 #define DRM_IOCTL_ETNAVIV_GEM_INFO DRM_IOWR(DRM_COMMAND_BASE + DRM_ETNAVIV_GEM_INFO, struct drm_etnaviv_gem_info) 144 #define DRM_IOCTL_ETNAVIV_GEM_CPU_PREP DRM_IOW(DRM_COMMAND_BASE + DRM_ETNAVIV_GEM_CPU_PREP, struct drm_etnaviv_gem_cpu_prep) 145 #define DRM_IOCTL_ETNAVIV_GEM_CPU_FINI DRM_IOW(DRM_COMMAND_BASE + DRM_ETNAVIV_GEM_CPU_FINI, struct drm_etnaviv_gem_cpu_fini) 146 #define DRM_IOCTL_ETNAVIV_GEM_SUBMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_ETNAVIV_GEM_SUBMIT, struct drm_etnaviv_gem_submit) 147 #define DRM_IOCTL_ETNAVIV_WAIT_FENCE DRM_IOW(DRM_COMMAND_BASE + DRM_ETNAVIV_WAIT_FENCE, struct drm_etnaviv_wait_fence) 148 #define DRM_IOCTL_ETNAVIV_GEM_USERPTR DRM_IOWR(DRM_COMMAND_BASE + DRM_ETNAVIV_GEM_USERPTR, struct drm_etnaviv_gem_userptr) 149 #define DRM_IOCTL_ETNAVIV_GEM_WAIT DRM_IOW(DRM_COMMAND_BASE + DRM_ETNAVIV_GEM_WAIT, struct drm_etnaviv_gem_wait) 150 #ifdef __cplusplus 151 #endif 152 #endif 153