• Home
  • Line#
  • Scopes#
  • Navigate#
  • Raw
  • Download
1 /****************************************************************************
2  ****************************************************************************
3  ***
4  ***   This header was automatically generated from a Linux kernel header
5  ***   of the same name, to make information necessary for userspace to
6  ***   call into the kernel available to libc.  It contains only constants,
7  ***   structures, and macros generated from the original header, and thus,
8  ***   contains no copyrightable information.
9  ***
10  ***   To edit the content of this header, modify the corresponding
11  ***   source file (e.g. under external/kernel-headers/original/) then
12  ***   run bionic/libc/kernel/tools/update_all.py
13  ***
14  ***   Any manual change here will be lost the next time this script will
15  ***   be run. You've been warned!
16  ***
17  ****************************************************************************
18  ****************************************************************************/
19 #ifndef __RADEON_DRM_H__
20 #define __RADEON_DRM_H__
21 #include "drm.h"
22 #ifdef __cplusplus
23 #endif
24 #ifndef __RADEON_SAREA_DEFINES__
25 #define __RADEON_SAREA_DEFINES__
26 #define RADEON_UPLOAD_CONTEXT 0x00000001
27 #define RADEON_UPLOAD_VERTFMT 0x00000002
28 #define RADEON_UPLOAD_LINE 0x00000004
29 #define RADEON_UPLOAD_BUMPMAP 0x00000008
30 #define RADEON_UPLOAD_MASKS 0x00000010
31 #define RADEON_UPLOAD_VIEWPORT 0x00000020
32 #define RADEON_UPLOAD_SETUP 0x00000040
33 #define RADEON_UPLOAD_TCL 0x00000080
34 #define RADEON_UPLOAD_MISC 0x00000100
35 #define RADEON_UPLOAD_TEX0 0x00000200
36 #define RADEON_UPLOAD_TEX1 0x00000400
37 #define RADEON_UPLOAD_TEX2 0x00000800
38 #define RADEON_UPLOAD_TEX0IMAGES 0x00001000
39 #define RADEON_UPLOAD_TEX1IMAGES 0x00002000
40 #define RADEON_UPLOAD_TEX2IMAGES 0x00004000
41 #define RADEON_UPLOAD_CLIPRECTS 0x00008000
42 #define RADEON_REQUIRE_QUIESCENCE 0x00010000
43 #define RADEON_UPLOAD_ZBIAS 0x00020000
44 #define RADEON_UPLOAD_ALL 0x003effff
45 #define RADEON_UPLOAD_CONTEXT_ALL 0x003e01ff
46 #define RADEON_EMIT_PP_MISC 0
47 #define RADEON_EMIT_PP_CNTL 1
48 #define RADEON_EMIT_RB3D_COLORPITCH 2
49 #define RADEON_EMIT_RE_LINE_PATTERN 3
50 #define RADEON_EMIT_SE_LINE_WIDTH 4
51 #define RADEON_EMIT_PP_LUM_MATRIX 5
52 #define RADEON_EMIT_PP_ROT_MATRIX_0 6
53 #define RADEON_EMIT_RB3D_STENCILREFMASK 7
54 #define RADEON_EMIT_SE_VPORT_XSCALE 8
55 #define RADEON_EMIT_SE_CNTL 9
56 #define RADEON_EMIT_SE_CNTL_STATUS 10
57 #define RADEON_EMIT_RE_MISC 11
58 #define RADEON_EMIT_PP_TXFILTER_0 12
59 #define RADEON_EMIT_PP_BORDER_COLOR_0 13
60 #define RADEON_EMIT_PP_TXFILTER_1 14
61 #define RADEON_EMIT_PP_BORDER_COLOR_1 15
62 #define RADEON_EMIT_PP_TXFILTER_2 16
63 #define RADEON_EMIT_PP_BORDER_COLOR_2 17
64 #define RADEON_EMIT_SE_ZBIAS_FACTOR 18
65 #define RADEON_EMIT_SE_TCL_OUTPUT_VTX_FMT 19
66 #define RADEON_EMIT_SE_TCL_MATERIAL_EMMISSIVE_RED 20
67 #define R200_EMIT_PP_TXCBLEND_0 21
68 #define R200_EMIT_PP_TXCBLEND_1 22
69 #define R200_EMIT_PP_TXCBLEND_2 23
70 #define R200_EMIT_PP_TXCBLEND_3 24
71 #define R200_EMIT_PP_TXCBLEND_4 25
72 #define R200_EMIT_PP_TXCBLEND_5 26
73 #define R200_EMIT_PP_TXCBLEND_6 27
74 #define R200_EMIT_PP_TXCBLEND_7 28
75 #define R200_EMIT_TCL_LIGHT_MODEL_CTL_0 29
76 #define R200_EMIT_TFACTOR_0 30
77 #define R200_EMIT_VTX_FMT_0 31
78 #define R200_EMIT_VAP_CTL 32
79 #define R200_EMIT_MATRIX_SELECT_0 33
80 #define R200_EMIT_TEX_PROC_CTL_2 34
81 #define R200_EMIT_TCL_UCP_VERT_BLEND_CTL 35
82 #define R200_EMIT_PP_TXFILTER_0 36
83 #define R200_EMIT_PP_TXFILTER_1 37
84 #define R200_EMIT_PP_TXFILTER_2 38
85 #define R200_EMIT_PP_TXFILTER_3 39
86 #define R200_EMIT_PP_TXFILTER_4 40
87 #define R200_EMIT_PP_TXFILTER_5 41
88 #define R200_EMIT_PP_TXOFFSET_0 42
89 #define R200_EMIT_PP_TXOFFSET_1 43
90 #define R200_EMIT_PP_TXOFFSET_2 44
91 #define R200_EMIT_PP_TXOFFSET_3 45
92 #define R200_EMIT_PP_TXOFFSET_4 46
93 #define R200_EMIT_PP_TXOFFSET_5 47
94 #define R200_EMIT_VTE_CNTL 48
95 #define R200_EMIT_OUTPUT_VTX_COMP_SEL 49
96 #define R200_EMIT_PP_TAM_DEBUG3 50
97 #define R200_EMIT_PP_CNTL_X 51
98 #define R200_EMIT_RB3D_DEPTHXY_OFFSET 52
99 #define R200_EMIT_RE_AUX_SCISSOR_CNTL 53
100 #define R200_EMIT_RE_SCISSOR_TL_0 54
101 #define R200_EMIT_RE_SCISSOR_TL_1 55
102 #define R200_EMIT_RE_SCISSOR_TL_2 56
103 #define R200_EMIT_SE_VAP_CNTL_STATUS 57
104 #define R200_EMIT_SE_VTX_STATE_CNTL 58
105 #define R200_EMIT_RE_POINTSIZE 59
106 #define R200_EMIT_TCL_INPUT_VTX_VECTOR_ADDR_0 60
107 #define R200_EMIT_PP_CUBIC_FACES_0 61
108 #define R200_EMIT_PP_CUBIC_OFFSETS_0 62
109 #define R200_EMIT_PP_CUBIC_FACES_1 63
110 #define R200_EMIT_PP_CUBIC_OFFSETS_1 64
111 #define R200_EMIT_PP_CUBIC_FACES_2 65
112 #define R200_EMIT_PP_CUBIC_OFFSETS_2 66
113 #define R200_EMIT_PP_CUBIC_FACES_3 67
114 #define R200_EMIT_PP_CUBIC_OFFSETS_3 68
115 #define R200_EMIT_PP_CUBIC_FACES_4 69
116 #define R200_EMIT_PP_CUBIC_OFFSETS_4 70
117 #define R200_EMIT_PP_CUBIC_FACES_5 71
118 #define R200_EMIT_PP_CUBIC_OFFSETS_5 72
119 #define RADEON_EMIT_PP_TEX_SIZE_0 73
120 #define RADEON_EMIT_PP_TEX_SIZE_1 74
121 #define RADEON_EMIT_PP_TEX_SIZE_2 75
122 #define R200_EMIT_RB3D_BLENDCOLOR 76
123 #define R200_EMIT_TCL_POINT_SPRITE_CNTL 77
124 #define RADEON_EMIT_PP_CUBIC_FACES_0 78
125 #define RADEON_EMIT_PP_CUBIC_OFFSETS_T0 79
126 #define RADEON_EMIT_PP_CUBIC_FACES_1 80
127 #define RADEON_EMIT_PP_CUBIC_OFFSETS_T1 81
128 #define RADEON_EMIT_PP_CUBIC_FACES_2 82
129 #define RADEON_EMIT_PP_CUBIC_OFFSETS_T2 83
130 #define R200_EMIT_PP_TRI_PERF_CNTL 84
131 #define R200_EMIT_PP_AFS_0 85
132 #define R200_EMIT_PP_AFS_1 86
133 #define R200_EMIT_ATF_TFACTOR 87
134 #define R200_EMIT_PP_TXCTLALL_0 88
135 #define R200_EMIT_PP_TXCTLALL_1 89
136 #define R200_EMIT_PP_TXCTLALL_2 90
137 #define R200_EMIT_PP_TXCTLALL_3 91
138 #define R200_EMIT_PP_TXCTLALL_4 92
139 #define R200_EMIT_PP_TXCTLALL_5 93
140 #define R200_EMIT_VAP_PVS_CNTL 94
141 #define RADEON_MAX_STATE_PACKETS 95
142 #define RADEON_CMD_PACKET 1
143 #define RADEON_CMD_SCALARS 2
144 #define RADEON_CMD_VECTORS 3
145 #define RADEON_CMD_DMA_DISCARD 4
146 #define RADEON_CMD_PACKET3 5
147 #define RADEON_CMD_PACKET3_CLIP 6
148 #define RADEON_CMD_SCALARS2 7
149 #define RADEON_CMD_WAIT 8
150 #define RADEON_CMD_VECLINEAR 9
151 typedef union {
152   int i;
153   struct {
154     unsigned char cmd_type, pad0, pad1, pad2;
155   } header;
156   struct {
157     unsigned char cmd_type, packet_id, pad0, pad1;
158   } packet;
159   struct {
160     unsigned char cmd_type, offset, stride, count;
161   } scalars;
162   struct {
163     unsigned char cmd_type, offset, stride, count;
164   } vectors;
165   struct {
166     unsigned char cmd_type, addr_lo, addr_hi, count;
167   } veclinear;
168   struct {
169     unsigned char cmd_type, buf_idx, pad0, pad1;
170   } dma;
171   struct {
172     unsigned char cmd_type, flags, pad0, pad1;
173   } wait;
174 } drm_radeon_cmd_header_t;
175 #define RADEON_WAIT_2D 0x1
176 #define RADEON_WAIT_3D 0x2
177 #define R300_CMD_PACKET3_CLEAR 0
178 #define R300_CMD_PACKET3_RAW 1
179 #define R300_CMD_PACKET0 1
180 #define R300_CMD_VPU 2
181 #define R300_CMD_PACKET3 3
182 #define R300_CMD_END3D 4
183 #define R300_CMD_CP_DELAY 5
184 #define R300_CMD_DMA_DISCARD 6
185 #define R300_CMD_WAIT 7
186 #define R300_WAIT_2D 0x1
187 #define R300_WAIT_3D 0x2
188 #define R300_WAIT_2D_CLEAN 0x3
189 #define R300_WAIT_3D_CLEAN 0x4
190 #define R300_NEW_WAIT_2D_3D 0x3
191 #define R300_NEW_WAIT_2D_2D_CLEAN 0x4
192 #define R300_NEW_WAIT_3D_3D_CLEAN 0x6
193 #define R300_NEW_WAIT_2D_2D_CLEAN_3D_3D_CLEAN 0x8
194 #define R300_CMD_SCRATCH 8
195 #define R300_CMD_R500FP 9
196 typedef union {
197   unsigned int u;
198   struct {
199     unsigned char cmd_type, pad0, pad1, pad2;
200   } header;
201   struct {
202     unsigned char cmd_type, count, reglo, reghi;
203   } packet0;
204   struct {
205     unsigned char cmd_type, count, adrlo, adrhi;
206   } vpu;
207   struct {
208     unsigned char cmd_type, packet, pad0, pad1;
209   } packet3;
210   struct {
211     unsigned char cmd_type, packet;
212     unsigned short count;
213   } delay;
214   struct {
215     unsigned char cmd_type, buf_idx, pad0, pad1;
216   } dma;
217   struct {
218     unsigned char cmd_type, flags, pad0, pad1;
219   } wait;
220   struct {
221     unsigned char cmd_type, reg, n_bufs, flags;
222   } scratch;
223   struct {
224     unsigned char cmd_type, count, adrlo, adrhi_flags;
225   } r500fp;
226 } drm_r300_cmd_header_t;
227 #define RADEON_FRONT 0x1
228 #define RADEON_BACK 0x2
229 #define RADEON_DEPTH 0x4
230 #define RADEON_STENCIL 0x8
231 #define RADEON_CLEAR_FASTZ 0x80000000
232 #define RADEON_USE_HIERZ 0x40000000
233 #define RADEON_USE_COMP_ZBUF 0x20000000
234 #define R500FP_CONSTANT_TYPE (1 << 1)
235 #define R500FP_CONSTANT_CLAMP (1 << 2)
236 #define RADEON_POINTS 0x1
237 #define RADEON_LINES 0x2
238 #define RADEON_LINE_STRIP 0x3
239 #define RADEON_TRIANGLES 0x4
240 #define RADEON_TRIANGLE_FAN 0x5
241 #define RADEON_TRIANGLE_STRIP 0x6
242 #define RADEON_BUFFER_SIZE 65536
243 #define RADEON_INDEX_PRIM_OFFSET 20
244 #define RADEON_SCRATCH_REG_OFFSET 32
245 #define R600_SCRATCH_REG_OFFSET 256
246 #define RADEON_NR_SAREA_CLIPRECTS 12
247 #define RADEON_LOCAL_TEX_HEAP 0
248 #define RADEON_GART_TEX_HEAP 1
249 #define RADEON_NR_TEX_HEAPS 2
250 #define RADEON_NR_TEX_REGIONS 64
251 #define RADEON_LOG_TEX_GRANULARITY 16
252 #define RADEON_MAX_TEXTURE_LEVELS 12
253 #define RADEON_MAX_TEXTURE_UNITS 3
254 #define RADEON_MAX_SURFACES 8
255 #define RADEON_OFFSET_SHIFT 10
256 #define RADEON_OFFSET_ALIGN (1 << RADEON_OFFSET_SHIFT)
257 #define RADEON_OFFSET_MASK (RADEON_OFFSET_ALIGN - 1)
258 #endif
259 typedef struct {
260   unsigned int red;
261   unsigned int green;
262   unsigned int blue;
263   unsigned int alpha;
264 } radeon_color_regs_t;
265 typedef struct {
266   unsigned int pp_misc;
267   unsigned int pp_fog_color;
268   unsigned int re_solid_color;
269   unsigned int rb3d_blendcntl;
270   unsigned int rb3d_depthoffset;
271   unsigned int rb3d_depthpitch;
272   unsigned int rb3d_zstencilcntl;
273   unsigned int pp_cntl;
274   unsigned int rb3d_cntl;
275   unsigned int rb3d_coloroffset;
276   unsigned int re_width_height;
277   unsigned int rb3d_colorpitch;
278   unsigned int se_cntl;
279   unsigned int se_coord_fmt;
280   unsigned int re_line_pattern;
281   unsigned int re_line_state;
282   unsigned int se_line_width;
283   unsigned int pp_lum_matrix;
284   unsigned int pp_rot_matrix_0;
285   unsigned int pp_rot_matrix_1;
286   unsigned int rb3d_stencilrefmask;
287   unsigned int rb3d_ropcntl;
288   unsigned int rb3d_planemask;
289   unsigned int se_vport_xscale;
290   unsigned int se_vport_xoffset;
291   unsigned int se_vport_yscale;
292   unsigned int se_vport_yoffset;
293   unsigned int se_vport_zscale;
294   unsigned int se_vport_zoffset;
295   unsigned int se_cntl_status;
296   unsigned int re_top_left;
297   unsigned int re_misc;
298 } drm_radeon_context_regs_t;
299 typedef struct {
300   unsigned int se_zbias_factor;
301   unsigned int se_zbias_constant;
302 } drm_radeon_context2_regs_t;
303 typedef struct {
304   unsigned int pp_txfilter;
305   unsigned int pp_txformat;
306   unsigned int pp_txoffset;
307   unsigned int pp_txcblend;
308   unsigned int pp_txablend;
309   unsigned int pp_tfactor;
310   unsigned int pp_border_color;
311 } drm_radeon_texture_regs_t;
312 typedef struct {
313   unsigned int start;
314   unsigned int finish;
315   unsigned int prim : 8;
316   unsigned int stateidx : 8;
317   unsigned int numverts : 16;
318   unsigned int vc_format;
319 } drm_radeon_prim_t;
320 typedef struct {
321   drm_radeon_context_regs_t context;
322   drm_radeon_texture_regs_t tex[RADEON_MAX_TEXTURE_UNITS];
323   drm_radeon_context2_regs_t context2;
324   unsigned int dirty;
325 } drm_radeon_state_t;
326 typedef struct {
327   drm_radeon_context_regs_t context_state;
328   drm_radeon_texture_regs_t tex_state[RADEON_MAX_TEXTURE_UNITS];
329   unsigned int dirty;
330   unsigned int vertsize;
331   unsigned int vc_format;
332   struct drm_clip_rect boxes[RADEON_NR_SAREA_CLIPRECTS];
333   unsigned int nbox;
334   unsigned int last_frame;
335   unsigned int last_dispatch;
336   unsigned int last_clear;
337   struct drm_tex_region tex_list[RADEON_NR_TEX_HEAPS][RADEON_NR_TEX_REGIONS + 1];
338   unsigned int tex_age[RADEON_NR_TEX_HEAPS];
339   int ctx_owner;
340   int pfState;
341   int pfCurrentPage;
342   int crtc2_base;
343   int tiling_enabled;
344 } drm_radeon_sarea_t;
345 #define DRM_RADEON_CP_INIT 0x00
346 #define DRM_RADEON_CP_START 0x01
347 #define DRM_RADEON_CP_STOP 0x02
348 #define DRM_RADEON_CP_RESET 0x03
349 #define DRM_RADEON_CP_IDLE 0x04
350 #define DRM_RADEON_RESET 0x05
351 #define DRM_RADEON_FULLSCREEN 0x06
352 #define DRM_RADEON_SWAP 0x07
353 #define DRM_RADEON_CLEAR 0x08
354 #define DRM_RADEON_VERTEX 0x09
355 #define DRM_RADEON_INDICES 0x0A
356 #define DRM_RADEON_NOT_USED
357 #define DRM_RADEON_STIPPLE 0x0C
358 #define DRM_RADEON_INDIRECT 0x0D
359 #define DRM_RADEON_TEXTURE 0x0E
360 #define DRM_RADEON_VERTEX2 0x0F
361 #define DRM_RADEON_CMDBUF 0x10
362 #define DRM_RADEON_GETPARAM 0x11
363 #define DRM_RADEON_FLIP 0x12
364 #define DRM_RADEON_ALLOC 0x13
365 #define DRM_RADEON_FREE 0x14
366 #define DRM_RADEON_INIT_HEAP 0x15
367 #define DRM_RADEON_IRQ_EMIT 0x16
368 #define DRM_RADEON_IRQ_WAIT 0x17
369 #define DRM_RADEON_CP_RESUME 0x18
370 #define DRM_RADEON_SETPARAM 0x19
371 #define DRM_RADEON_SURF_ALLOC 0x1a
372 #define DRM_RADEON_SURF_FREE 0x1b
373 #define DRM_RADEON_GEM_INFO 0x1c
374 #define DRM_RADEON_GEM_CREATE 0x1d
375 #define DRM_RADEON_GEM_MMAP 0x1e
376 #define DRM_RADEON_GEM_PREAD 0x21
377 #define DRM_RADEON_GEM_PWRITE 0x22
378 #define DRM_RADEON_GEM_SET_DOMAIN 0x23
379 #define DRM_RADEON_GEM_WAIT_IDLE 0x24
380 #define DRM_RADEON_CS 0x26
381 #define DRM_RADEON_INFO 0x27
382 #define DRM_RADEON_GEM_SET_TILING 0x28
383 #define DRM_RADEON_GEM_GET_TILING 0x29
384 #define DRM_RADEON_GEM_BUSY 0x2a
385 #define DRM_RADEON_GEM_VA 0x2b
386 #define DRM_RADEON_GEM_OP 0x2c
387 #define DRM_RADEON_GEM_USERPTR 0x2d
388 #define DRM_IOCTL_RADEON_CP_INIT DRM_IOW(DRM_COMMAND_BASE + DRM_RADEON_CP_INIT, drm_radeon_init_t)
389 #define DRM_IOCTL_RADEON_CP_START DRM_IO(DRM_COMMAND_BASE + DRM_RADEON_CP_START)
390 #define DRM_IOCTL_RADEON_CP_STOP DRM_IOW(DRM_COMMAND_BASE + DRM_RADEON_CP_STOP, drm_radeon_cp_stop_t)
391 #define DRM_IOCTL_RADEON_CP_RESET DRM_IO(DRM_COMMAND_BASE + DRM_RADEON_CP_RESET)
392 #define DRM_IOCTL_RADEON_CP_IDLE DRM_IO(DRM_COMMAND_BASE + DRM_RADEON_CP_IDLE)
393 #define DRM_IOCTL_RADEON_RESET DRM_IO(DRM_COMMAND_BASE + DRM_RADEON_RESET)
394 #define DRM_IOCTL_RADEON_FULLSCREEN DRM_IOW(DRM_COMMAND_BASE + DRM_RADEON_FULLSCREEN, drm_radeon_fullscreen_t)
395 #define DRM_IOCTL_RADEON_SWAP DRM_IO(DRM_COMMAND_BASE + DRM_RADEON_SWAP)
396 #define DRM_IOCTL_RADEON_CLEAR DRM_IOW(DRM_COMMAND_BASE + DRM_RADEON_CLEAR, drm_radeon_clear_t)
397 #define DRM_IOCTL_RADEON_VERTEX DRM_IOW(DRM_COMMAND_BASE + DRM_RADEON_VERTEX, drm_radeon_vertex_t)
398 #define DRM_IOCTL_RADEON_INDICES DRM_IOW(DRM_COMMAND_BASE + DRM_RADEON_INDICES, drm_radeon_indices_t)
399 #define DRM_IOCTL_RADEON_STIPPLE DRM_IOW(DRM_COMMAND_BASE + DRM_RADEON_STIPPLE, drm_radeon_stipple_t)
400 #define DRM_IOCTL_RADEON_INDIRECT DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_INDIRECT, drm_radeon_indirect_t)
401 #define DRM_IOCTL_RADEON_TEXTURE DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_TEXTURE, drm_radeon_texture_t)
402 #define DRM_IOCTL_RADEON_VERTEX2 DRM_IOW(DRM_COMMAND_BASE + DRM_RADEON_VERTEX2, drm_radeon_vertex2_t)
403 #define DRM_IOCTL_RADEON_CMDBUF DRM_IOW(DRM_COMMAND_BASE + DRM_RADEON_CMDBUF, drm_radeon_cmd_buffer_t)
404 #define DRM_IOCTL_RADEON_GETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GETPARAM, drm_radeon_getparam_t)
405 #define DRM_IOCTL_RADEON_FLIP DRM_IO(DRM_COMMAND_BASE + DRM_RADEON_FLIP)
406 #define DRM_IOCTL_RADEON_ALLOC DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_ALLOC, drm_radeon_mem_alloc_t)
407 #define DRM_IOCTL_RADEON_FREE DRM_IOW(DRM_COMMAND_BASE + DRM_RADEON_FREE, drm_radeon_mem_free_t)
408 #define DRM_IOCTL_RADEON_INIT_HEAP DRM_IOW(DRM_COMMAND_BASE + DRM_RADEON_INIT_HEAP, drm_radeon_mem_init_heap_t)
409 #define DRM_IOCTL_RADEON_IRQ_EMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_IRQ_EMIT, drm_radeon_irq_emit_t)
410 #define DRM_IOCTL_RADEON_IRQ_WAIT DRM_IOW(DRM_COMMAND_BASE + DRM_RADEON_IRQ_WAIT, drm_radeon_irq_wait_t)
411 #define DRM_IOCTL_RADEON_CP_RESUME DRM_IO(DRM_COMMAND_BASE + DRM_RADEON_CP_RESUME)
412 #define DRM_IOCTL_RADEON_SETPARAM DRM_IOW(DRM_COMMAND_BASE + DRM_RADEON_SETPARAM, drm_radeon_setparam_t)
413 #define DRM_IOCTL_RADEON_SURF_ALLOC DRM_IOW(DRM_COMMAND_BASE + DRM_RADEON_SURF_ALLOC, drm_radeon_surface_alloc_t)
414 #define DRM_IOCTL_RADEON_SURF_FREE DRM_IOW(DRM_COMMAND_BASE + DRM_RADEON_SURF_FREE, drm_radeon_surface_free_t)
415 #define DRM_IOCTL_RADEON_GEM_INFO DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_INFO, struct drm_radeon_gem_info)
416 #define DRM_IOCTL_RADEON_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_CREATE, struct drm_radeon_gem_create)
417 #define DRM_IOCTL_RADEON_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_MMAP, struct drm_radeon_gem_mmap)
418 #define DRM_IOCTL_RADEON_GEM_PREAD DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_PREAD, struct drm_radeon_gem_pread)
419 #define DRM_IOCTL_RADEON_GEM_PWRITE DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_PWRITE, struct drm_radeon_gem_pwrite)
420 #define DRM_IOCTL_RADEON_GEM_SET_DOMAIN DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_SET_DOMAIN, struct drm_radeon_gem_set_domain)
421 #define DRM_IOCTL_RADEON_GEM_WAIT_IDLE DRM_IOW(DRM_COMMAND_BASE + DRM_RADEON_GEM_WAIT_IDLE, struct drm_radeon_gem_wait_idle)
422 #define DRM_IOCTL_RADEON_CS DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_CS, struct drm_radeon_cs)
423 #define DRM_IOCTL_RADEON_INFO DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_INFO, struct drm_radeon_info)
424 #define DRM_IOCTL_RADEON_GEM_SET_TILING DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_SET_TILING, struct drm_radeon_gem_set_tiling)
425 #define DRM_IOCTL_RADEON_GEM_GET_TILING DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_GET_TILING, struct drm_radeon_gem_get_tiling)
426 #define DRM_IOCTL_RADEON_GEM_BUSY DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_BUSY, struct drm_radeon_gem_busy)
427 #define DRM_IOCTL_RADEON_GEM_VA DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_VA, struct drm_radeon_gem_va)
428 #define DRM_IOCTL_RADEON_GEM_OP DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_OP, struct drm_radeon_gem_op)
429 #define DRM_IOCTL_RADEON_GEM_USERPTR DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_USERPTR, struct drm_radeon_gem_userptr)
430 typedef struct drm_radeon_init {
431   enum {
432     RADEON_INIT_CP = 0x01,
433     RADEON_CLEANUP_CP = 0x02,
434     RADEON_INIT_R200_CP = 0x03,
435     RADEON_INIT_R300_CP = 0x04,
436     RADEON_INIT_R600_CP = 0x05
437   } func;
438   unsigned long sarea_priv_offset;
439   int is_pci;
440   int cp_mode;
441   int gart_size;
442   int ring_size;
443   int usec_timeout;
444   unsigned int fb_bpp;
445   unsigned int front_offset, front_pitch;
446   unsigned int back_offset, back_pitch;
447   unsigned int depth_bpp;
448   unsigned int depth_offset, depth_pitch;
449   unsigned long fb_offset;
450   unsigned long mmio_offset;
451   unsigned long ring_offset;
452   unsigned long ring_rptr_offset;
453   unsigned long buffers_offset;
454   unsigned long gart_textures_offset;
455 } drm_radeon_init_t;
456 typedef struct drm_radeon_cp_stop {
457   int flush;
458   int idle;
459 } drm_radeon_cp_stop_t;
460 typedef struct drm_radeon_fullscreen {
461   enum {
462     RADEON_INIT_FULLSCREEN = 0x01,
463     RADEON_CLEANUP_FULLSCREEN = 0x02
464   } func;
465 } drm_radeon_fullscreen_t;
466 #define CLEAR_X1 0
467 #define CLEAR_Y1 1
468 #define CLEAR_X2 2
469 #define CLEAR_Y2 3
470 #define CLEAR_DEPTH 4
471 typedef union drm_radeon_clear_rect {
472   float f[5];
473   unsigned int ui[5];
474 } drm_radeon_clear_rect_t;
475 typedef struct drm_radeon_clear {
476   unsigned int flags;
477   unsigned int clear_color;
478   unsigned int clear_depth;
479   unsigned int color_mask;
480   unsigned int depth_mask;
481   drm_radeon_clear_rect_t __user * depth_boxes;
482 } drm_radeon_clear_t;
483 typedef struct drm_radeon_vertex {
484   int prim;
485   int idx;
486   int count;
487   int discard;
488 } drm_radeon_vertex_t;
489 typedef struct drm_radeon_indices {
490   int prim;
491   int idx;
492   int start;
493   int end;
494   int discard;
495 } drm_radeon_indices_t;
496 typedef struct drm_radeon_vertex2 {
497   int idx;
498   int discard;
499   int nr_states;
500   drm_radeon_state_t __user * state;
501   int nr_prims;
502   drm_radeon_prim_t __user * prim;
503 } drm_radeon_vertex2_t;
504 typedef struct drm_radeon_cmd_buffer {
505   int bufsz;
506   char __user * buf;
507   int nbox;
508   struct drm_clip_rect __user * boxes;
509 } drm_radeon_cmd_buffer_t;
510 typedef struct drm_radeon_tex_image {
511   unsigned int x, y;
512   unsigned int width, height;
513   const void __user * data;
514 } drm_radeon_tex_image_t;
515 typedef struct drm_radeon_texture {
516   unsigned int offset;
517   int pitch;
518   int format;
519   int width;
520   int height;
521   drm_radeon_tex_image_t __user * image;
522 } drm_radeon_texture_t;
523 typedef struct drm_radeon_stipple {
524   unsigned int __user * mask;
525 } drm_radeon_stipple_t;
526 typedef struct drm_radeon_indirect {
527   int idx;
528   int start;
529   int end;
530   int discard;
531 } drm_radeon_indirect_t;
532 #define RADEON_CARD_PCI 0
533 #define RADEON_CARD_AGP 1
534 #define RADEON_CARD_PCIE 2
535 #define RADEON_PARAM_GART_BUFFER_OFFSET 1
536 #define RADEON_PARAM_LAST_FRAME 2
537 #define RADEON_PARAM_LAST_DISPATCH 3
538 #define RADEON_PARAM_LAST_CLEAR 4
539 #define RADEON_PARAM_IRQ_NR 5
540 #define RADEON_PARAM_GART_BASE 6
541 #define RADEON_PARAM_REGISTER_HANDLE 7
542 #define RADEON_PARAM_STATUS_HANDLE 8
543 #define RADEON_PARAM_SAREA_HANDLE 9
544 #define RADEON_PARAM_GART_TEX_HANDLE 10
545 #define RADEON_PARAM_SCRATCH_OFFSET 11
546 #define RADEON_PARAM_CARD_TYPE 12
547 #define RADEON_PARAM_VBLANK_CRTC 13
548 #define RADEON_PARAM_FB_LOCATION 14
549 #define RADEON_PARAM_NUM_GB_PIPES 15
550 #define RADEON_PARAM_DEVICE_ID 16
551 #define RADEON_PARAM_NUM_Z_PIPES 17
552 typedef struct drm_radeon_getparam {
553   int param;
554   void __user * value;
555 } drm_radeon_getparam_t;
556 #define RADEON_MEM_REGION_GART 1
557 #define RADEON_MEM_REGION_FB 2
558 typedef struct drm_radeon_mem_alloc {
559   int region;
560   int alignment;
561   int size;
562   int __user * region_offset;
563 } drm_radeon_mem_alloc_t;
564 typedef struct drm_radeon_mem_free {
565   int region;
566   int region_offset;
567 } drm_radeon_mem_free_t;
568 typedef struct drm_radeon_mem_init_heap {
569   int region;
570   int size;
571   int start;
572 } drm_radeon_mem_init_heap_t;
573 typedef struct drm_radeon_irq_emit {
574   int __user * irq_seq;
575 } drm_radeon_irq_emit_t;
576 typedef struct drm_radeon_irq_wait {
577   int irq_seq;
578 } drm_radeon_irq_wait_t;
579 typedef struct drm_radeon_setparam {
580   unsigned int param;
581   __s64 value;
582 } drm_radeon_setparam_t;
583 #define RADEON_SETPARAM_FB_LOCATION 1
584 #define RADEON_SETPARAM_SWITCH_TILING 2
585 #define RADEON_SETPARAM_PCIGART_LOCATION 3
586 #define RADEON_SETPARAM_NEW_MEMMAP 4
587 #define RADEON_SETPARAM_PCIGART_TABLE_SIZE 5
588 #define RADEON_SETPARAM_VBLANK_CRTC 6
589 typedef struct drm_radeon_surface_alloc {
590   unsigned int address;
591   unsigned int size;
592   unsigned int flags;
593 } drm_radeon_surface_alloc_t;
594 typedef struct drm_radeon_surface_free {
595   unsigned int address;
596 } drm_radeon_surface_free_t;
597 #define DRM_RADEON_VBLANK_CRTC1 1
598 #define DRM_RADEON_VBLANK_CRTC2 2
599 #define RADEON_GEM_DOMAIN_CPU 0x1
600 #define RADEON_GEM_DOMAIN_GTT 0x2
601 #define RADEON_GEM_DOMAIN_VRAM 0x4
602 struct drm_radeon_gem_info {
603   __u64 gart_size;
604   __u64 vram_size;
605   __u64 vram_visible;
606 };
607 #define RADEON_GEM_NO_BACKING_STORE (1 << 0)
608 #define RADEON_GEM_GTT_UC (1 << 1)
609 #define RADEON_GEM_GTT_WC (1 << 2)
610 #define RADEON_GEM_CPU_ACCESS (1 << 3)
611 #define RADEON_GEM_NO_CPU_ACCESS (1 << 4)
612 struct drm_radeon_gem_create {
613   __u64 size;
614   __u64 alignment;
615   __u32 handle;
616   __u32 initial_domain;
617   __u32 flags;
618 };
619 #define RADEON_GEM_USERPTR_READONLY (1 << 0)
620 #define RADEON_GEM_USERPTR_ANONONLY (1 << 1)
621 #define RADEON_GEM_USERPTR_VALIDATE (1 << 2)
622 #define RADEON_GEM_USERPTR_REGISTER (1 << 3)
623 struct drm_radeon_gem_userptr {
624   __u64 addr;
625   __u64 size;
626   __u32 flags;
627   __u32 handle;
628 };
629 #define RADEON_TILING_MACRO 0x1
630 #define RADEON_TILING_MICRO 0x2
631 #define RADEON_TILING_SWAP_16BIT 0x4
632 #define RADEON_TILING_SWAP_32BIT 0x8
633 #define RADEON_TILING_SURFACE 0x10
634 #define RADEON_TILING_MICRO_SQUARE 0x20
635 #define RADEON_TILING_EG_BANKW_SHIFT 8
636 #define RADEON_TILING_EG_BANKW_MASK 0xf
637 #define RADEON_TILING_EG_BANKH_SHIFT 12
638 #define RADEON_TILING_EG_BANKH_MASK 0xf
639 #define RADEON_TILING_EG_MACRO_TILE_ASPECT_SHIFT 16
640 #define RADEON_TILING_EG_MACRO_TILE_ASPECT_MASK 0xf
641 #define RADEON_TILING_EG_TILE_SPLIT_SHIFT 24
642 #define RADEON_TILING_EG_TILE_SPLIT_MASK 0xf
643 #define RADEON_TILING_EG_STENCIL_TILE_SPLIT_SHIFT 28
644 #define RADEON_TILING_EG_STENCIL_TILE_SPLIT_MASK 0xf
645 struct drm_radeon_gem_set_tiling {
646   __u32 handle;
647   __u32 tiling_flags;
648   __u32 pitch;
649 };
650 struct drm_radeon_gem_get_tiling {
651   __u32 handle;
652   __u32 tiling_flags;
653   __u32 pitch;
654 };
655 struct drm_radeon_gem_mmap {
656   __u32 handle;
657   __u32 pad;
658   __u64 offset;
659   __u64 size;
660   __u64 addr_ptr;
661 };
662 struct drm_radeon_gem_set_domain {
663   __u32 handle;
664   __u32 read_domains;
665   __u32 write_domain;
666 };
667 struct drm_radeon_gem_wait_idle {
668   __u32 handle;
669   __u32 pad;
670 };
671 struct drm_radeon_gem_busy {
672   __u32 handle;
673   __u32 domain;
674 };
675 struct drm_radeon_gem_pread {
676   __u32 handle;
677   __u32 pad;
678   __u64 offset;
679   __u64 size;
680   __u64 data_ptr;
681 };
682 struct drm_radeon_gem_pwrite {
683   __u32 handle;
684   __u32 pad;
685   __u64 offset;
686   __u64 size;
687   __u64 data_ptr;
688 };
689 struct drm_radeon_gem_op {
690   __u32 handle;
691   __u32 op;
692   __u64 value;
693 };
694 #define RADEON_GEM_OP_GET_INITIAL_DOMAIN 0
695 #define RADEON_GEM_OP_SET_INITIAL_DOMAIN 1
696 #define RADEON_VA_MAP 1
697 #define RADEON_VA_UNMAP 2
698 #define RADEON_VA_RESULT_OK 0
699 #define RADEON_VA_RESULT_ERROR 1
700 #define RADEON_VA_RESULT_VA_EXIST 2
701 #define RADEON_VM_PAGE_VALID (1 << 0)
702 #define RADEON_VM_PAGE_READABLE (1 << 1)
703 #define RADEON_VM_PAGE_WRITEABLE (1 << 2)
704 #define RADEON_VM_PAGE_SYSTEM (1 << 3)
705 #define RADEON_VM_PAGE_SNOOPED (1 << 4)
706 struct drm_radeon_gem_va {
707   __u32 handle;
708   __u32 operation;
709   __u32 vm_id;
710   __u32 flags;
711   __u64 offset;
712 };
713 #define RADEON_CHUNK_ID_RELOCS 0x01
714 #define RADEON_CHUNK_ID_IB 0x02
715 #define RADEON_CHUNK_ID_FLAGS 0x03
716 #define RADEON_CHUNK_ID_CONST_IB 0x04
717 #define RADEON_CS_KEEP_TILING_FLAGS 0x01
718 #define RADEON_CS_USE_VM 0x02
719 #define RADEON_CS_END_OF_FRAME 0x04
720 #define RADEON_CS_RING_GFX 0
721 #define RADEON_CS_RING_COMPUTE 1
722 #define RADEON_CS_RING_DMA 2
723 #define RADEON_CS_RING_UVD 3
724 #define RADEON_CS_RING_VCE 4
725 struct drm_radeon_cs_chunk {
726   __u32 chunk_id;
727   __u32 length_dw;
728   __u64 chunk_data;
729 };
730 #define RADEON_RELOC_PRIO_MASK (0xf << 0)
731 struct drm_radeon_cs_reloc {
732   __u32 handle;
733   __u32 read_domains;
734   __u32 write_domain;
735   __u32 flags;
736 };
737 struct drm_radeon_cs {
738   __u32 num_chunks;
739   __u32 cs_id;
740   __u64 chunks;
741   __u64 gart_limit;
742   __u64 vram_limit;
743 };
744 #define RADEON_INFO_DEVICE_ID 0x00
745 #define RADEON_INFO_NUM_GB_PIPES 0x01
746 #define RADEON_INFO_NUM_Z_PIPES 0x02
747 #define RADEON_INFO_ACCEL_WORKING 0x03
748 #define RADEON_INFO_CRTC_FROM_ID 0x04
749 #define RADEON_INFO_ACCEL_WORKING2 0x05
750 #define RADEON_INFO_TILING_CONFIG 0x06
751 #define RADEON_INFO_WANT_HYPERZ 0x07
752 #define RADEON_INFO_WANT_CMASK 0x08
753 #define RADEON_INFO_CLOCK_CRYSTAL_FREQ 0x09
754 #define RADEON_INFO_NUM_BACKENDS 0x0a
755 #define RADEON_INFO_NUM_TILE_PIPES 0x0b
756 #define RADEON_INFO_FUSION_GART_WORKING 0x0c
757 #define RADEON_INFO_BACKEND_MAP 0x0d
758 #define RADEON_INFO_VA_START 0x0e
759 #define RADEON_INFO_IB_VM_MAX_SIZE 0x0f
760 #define RADEON_INFO_MAX_PIPES 0x10
761 #define RADEON_INFO_TIMESTAMP 0x11
762 #define RADEON_INFO_MAX_SE 0x12
763 #define RADEON_INFO_MAX_SH_PER_SE 0x13
764 #define RADEON_INFO_FASTFB_WORKING 0x14
765 #define RADEON_INFO_RING_WORKING 0x15
766 #define RADEON_INFO_SI_TILE_MODE_ARRAY 0x16
767 #define RADEON_INFO_SI_CP_DMA_COMPUTE 0x17
768 #define RADEON_INFO_CIK_MACROTILE_MODE_ARRAY 0x18
769 #define RADEON_INFO_SI_BACKEND_ENABLED_MASK 0x19
770 #define RADEON_INFO_MAX_SCLK 0x1a
771 #define RADEON_INFO_VCE_FW_VERSION 0x1b
772 #define RADEON_INFO_VCE_FB_VERSION 0x1c
773 #define RADEON_INFO_NUM_BYTES_MOVED 0x1d
774 #define RADEON_INFO_VRAM_USAGE 0x1e
775 #define RADEON_INFO_GTT_USAGE 0x1f
776 #define RADEON_INFO_ACTIVE_CU_COUNT 0x20
777 #define RADEON_INFO_CURRENT_GPU_TEMP 0x21
778 #define RADEON_INFO_CURRENT_GPU_SCLK 0x22
779 #define RADEON_INFO_CURRENT_GPU_MCLK 0x23
780 #define RADEON_INFO_READ_REG 0x24
781 #define RADEON_INFO_VA_UNMAP_WORKING 0x25
782 #define RADEON_INFO_GPU_RESET_COUNTER 0x26
783 struct drm_radeon_info {
784   __u32 request;
785   __u32 pad;
786   __u64 value;
787 };
788 #define SI_TILE_MODE_COLOR_LINEAR_ALIGNED 8
789 #define SI_TILE_MODE_COLOR_1D 13
790 #define SI_TILE_MODE_COLOR_1D_SCANOUT 9
791 #define SI_TILE_MODE_COLOR_2D_8BPP 14
792 #define SI_TILE_MODE_COLOR_2D_16BPP 15
793 #define SI_TILE_MODE_COLOR_2D_32BPP 16
794 #define SI_TILE_MODE_COLOR_2D_64BPP 17
795 #define SI_TILE_MODE_COLOR_2D_SCANOUT_16BPP 11
796 #define SI_TILE_MODE_COLOR_2D_SCANOUT_32BPP 12
797 #define SI_TILE_MODE_DEPTH_STENCIL_1D 4
798 #define SI_TILE_MODE_DEPTH_STENCIL_2D 0
799 #define SI_TILE_MODE_DEPTH_STENCIL_2D_2AA 3
800 #define SI_TILE_MODE_DEPTH_STENCIL_2D_4AA 3
801 #define SI_TILE_MODE_DEPTH_STENCIL_2D_8AA 2
802 #define CIK_TILE_MODE_DEPTH_STENCIL_1D 5
803 #ifdef __cplusplus
804 #endif
805 #endif
806