1 /**************************************************************************** 2 **************************************************************************** 3 *** 4 *** This header was automatically generated from a Linux kernel header 5 *** of the same name, to make information necessary for userspace to 6 *** call into the kernel available to libc. It contains only constants, 7 *** structures, and macros generated from the original header, and thus, 8 *** contains no copyrightable information. 9 *** 10 *** To edit the content of this header, modify the corresponding 11 *** source file (e.g. under external/kernel-headers/original/) then 12 *** run bionic/libc/kernel/tools/update_all.py 13 *** 14 *** Any manual change here will be lost the next time this script will 15 *** be run. You've been warned! 16 *** 17 **************************************************************************** 18 ****************************************************************************/ 19 #ifndef _UAPI_VC4_DRM_H_ 20 #define _UAPI_VC4_DRM_H_ 21 #include "drm.h" 22 #ifdef __cplusplus 23 #endif 24 #define DRM_VC4_SUBMIT_CL 0x00 25 #define DRM_VC4_WAIT_SEQNO 0x01 26 #define DRM_VC4_WAIT_BO 0x02 27 #define DRM_VC4_CREATE_BO 0x03 28 #define DRM_VC4_MMAP_BO 0x04 29 #define DRM_VC4_CREATE_SHADER_BO 0x05 30 #define DRM_VC4_GET_HANG_STATE 0x06 31 #define DRM_VC4_GET_PARAM 0x07 32 #define DRM_IOCTL_VC4_SUBMIT_CL DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_SUBMIT_CL, struct drm_vc4_submit_cl) 33 #define DRM_IOCTL_VC4_WAIT_SEQNO DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_WAIT_SEQNO, struct drm_vc4_wait_seqno) 34 #define DRM_IOCTL_VC4_WAIT_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_WAIT_BO, struct drm_vc4_wait_bo) 35 #define DRM_IOCTL_VC4_CREATE_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_CREATE_BO, struct drm_vc4_create_bo) 36 #define DRM_IOCTL_VC4_MMAP_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_MMAP_BO, struct drm_vc4_mmap_bo) 37 #define DRM_IOCTL_VC4_CREATE_SHADER_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_CREATE_SHADER_BO, struct drm_vc4_create_shader_bo) 38 #define DRM_IOCTL_VC4_GET_HANG_STATE DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_GET_HANG_STATE, struct drm_vc4_get_hang_state) 39 #define DRM_IOCTL_VC4_GET_PARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_GET_PARAM, struct drm_vc4_get_param) 40 struct drm_vc4_submit_rcl_surface { 41 __u32 hindex; 42 __u32 offset; 43 __u16 bits; 44 #define VC4_SUBMIT_RCL_SURFACE_READ_IS_FULL_RES (1 << 0) 45 __u16 flags; 46 }; 47 struct drm_vc4_submit_cl { 48 __u64 bin_cl; 49 __u64 shader_rec; 50 __u64 uniforms; 51 __u64 bo_handles; 52 __u32 bin_cl_size; 53 __u32 shader_rec_size; 54 __u32 shader_rec_count; 55 __u32 uniforms_size; 56 __u32 bo_handle_count; 57 __u16 width; 58 __u16 height; 59 __u8 min_x_tile; 60 __u8 min_y_tile; 61 __u8 max_x_tile; 62 __u8 max_y_tile; 63 struct drm_vc4_submit_rcl_surface color_read; 64 struct drm_vc4_submit_rcl_surface color_write; 65 struct drm_vc4_submit_rcl_surface zs_read; 66 struct drm_vc4_submit_rcl_surface zs_write; 67 struct drm_vc4_submit_rcl_surface msaa_color_write; 68 struct drm_vc4_submit_rcl_surface msaa_zs_write; 69 __u32 clear_color[2]; 70 __u32 clear_z; 71 __u8 clear_s; 72 __u32 pad : 24; 73 #define VC4_SUBMIT_CL_USE_CLEAR_COLOR (1 << 0) 74 __u32 flags; 75 __u64 seqno; 76 }; 77 struct drm_vc4_wait_seqno { 78 __u64 seqno; 79 __u64 timeout_ns; 80 }; 81 struct drm_vc4_wait_bo { 82 __u32 handle; 83 __u32 pad; 84 __u64 timeout_ns; 85 }; 86 struct drm_vc4_create_bo { 87 __u32 size; 88 __u32 flags; 89 __u32 handle; 90 __u32 pad; 91 }; 92 struct drm_vc4_mmap_bo { 93 __u32 handle; 94 __u32 flags; 95 __u64 offset; 96 }; 97 struct drm_vc4_create_shader_bo { 98 __u32 size; 99 __u32 flags; 100 __u64 data; 101 __u32 handle; 102 __u32 pad; 103 }; 104 struct drm_vc4_get_hang_state_bo { 105 __u32 handle; 106 __u32 paddr; 107 __u32 size; 108 __u32 pad; 109 }; 110 struct drm_vc4_get_hang_state { 111 __u64 bo; 112 __u32 bo_count; 113 __u32 start_bin, start_render; 114 __u32 ct0ca, ct0ea; 115 __u32 ct1ca, ct1ea; 116 __u32 ct0cs, ct1cs; 117 __u32 ct0ra0, ct1ra0; 118 __u32 bpca, bpcs; 119 __u32 bpoa, bpos; 120 __u32 vpmbase; 121 __u32 dbge; 122 __u32 fdbgo; 123 __u32 fdbgb; 124 __u32 fdbgr; 125 __u32 fdbgs; 126 __u32 errstat; 127 __u32 pad[16]; 128 }; 129 #define DRM_VC4_PARAM_V3D_IDENT0 0 130 #define DRM_VC4_PARAM_V3D_IDENT1 1 131 #define DRM_VC4_PARAM_V3D_IDENT2 2 132 #define DRM_VC4_PARAM_SUPPORTS_BRANCHES 3 133 #define DRM_VC4_PARAM_SUPPORTS_ETC1 4 134 #define DRM_VC4_PARAM_SUPPORTS_THREADED_FS 5 135 struct drm_vc4_get_param { 136 __u32 param; 137 __u32 pad; 138 __u64 value; 139 }; 140 #ifdef __cplusplus 141 #endif 142 #endif 143