1 /**************************************************************************** 2 **************************************************************************** 3 *** 4 *** This header was automatically generated from a Linux kernel header 5 *** of the same name, to make information necessary for userspace to 6 *** call into the kernel available to libc. It contains only constants, 7 *** structures, and macros generated from the original header, and thus, 8 *** contains no copyrightable information. 9 *** 10 *** To edit the content of this header, modify the corresponding 11 *** source file (e.g. under external/kernel-headers/original/) then 12 *** run bionic/libc/kernel/tools/update_all.py 13 *** 14 *** Any manual change here will be lost the next time this script will 15 *** be run. You've been warned! 16 *** 17 **************************************************************************** 18 ****************************************************************************/ 19 #ifndef MLX5_ABI_USER_H 20 #define MLX5_ABI_USER_H 21 #include <linux/types.h> 22 enum { 23 MLX5_QP_FLAG_SIGNATURE = 1 << 0, 24 MLX5_QP_FLAG_SCATTER_CQE = 1 << 1, 25 }; 26 enum { 27 MLX5_SRQ_FLAG_SIGNATURE = 1 << 0, 28 }; 29 enum { 30 MLX5_WQ_FLAG_SIGNATURE = 1 << 0, 31 }; 32 #define MLX5_IB_UVERBS_ABI_VERSION 1 33 struct mlx5_ib_alloc_ucontext_req { 34 __u32 total_num_uuars; 35 __u32 num_low_latency_uuars; 36 }; 37 struct mlx5_ib_alloc_ucontext_req_v2 { 38 __u32 total_num_uuars; 39 __u32 num_low_latency_uuars; 40 __u32 flags; 41 __u32 comp_mask; 42 __u8 max_cqe_version; 43 __u8 reserved0; 44 __u16 reserved1; 45 __u32 reserved2; 46 }; 47 enum mlx5_ib_alloc_ucontext_resp_mask { 48 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_CORE_CLOCK_OFFSET = 1UL << 0, 49 }; 50 enum mlx5_user_cmds_supp_uhw { 51 MLX5_USER_CMDS_SUPP_UHW_QUERY_DEVICE = 1 << 0, 52 MLX5_USER_CMDS_SUPP_UHW_CREATE_AH = 1 << 1, 53 }; 54 struct mlx5_ib_alloc_ucontext_resp { 55 __u32 qp_tab_size; 56 __u32 bf_reg_size; 57 __u32 tot_uuars; 58 __u32 cache_line_size; 59 __u16 max_sq_desc_sz; 60 __u16 max_rq_desc_sz; 61 __u32 max_send_wqebb; 62 __u32 max_recv_wr; 63 __u32 max_srq_recv_wr; 64 __u16 num_ports; 65 __u16 reserved1; 66 __u32 comp_mask; 67 __u32 response_length; 68 __u8 cqe_version; 69 __u8 cmds_supp_uhw; 70 __u16 reserved2; 71 __u64 hca_core_clock_offset; 72 }; 73 struct mlx5_ib_alloc_pd_resp { 74 __u32 pdn; 75 }; 76 struct mlx5_ib_tso_caps { 77 __u32 max_tso; 78 __u32 supported_qpts; 79 }; 80 struct mlx5_ib_rss_caps { 81 __u64 rx_hash_fields_mask; 82 __u8 rx_hash_function; 83 __u8 reserved[7]; 84 }; 85 enum mlx5_ib_cqe_comp_res_format { 86 MLX5_IB_CQE_RES_FORMAT_HASH = 1 << 0, 87 MLX5_IB_CQE_RES_FORMAT_CSUM = 1 << 1, 88 MLX5_IB_CQE_RES_RESERVED = 1 << 2, 89 }; 90 struct mlx5_ib_cqe_comp_caps { 91 __u32 max_num; 92 __u32 supported_format; 93 }; 94 struct mlx5_packet_pacing_caps { 95 __u32 qp_rate_limit_min; 96 __u32 qp_rate_limit_max; 97 __u32 supported_qpts; 98 __u32 reserved; 99 }; 100 struct mlx5_ib_query_device_resp { 101 __u32 comp_mask; 102 __u32 response_length; 103 struct mlx5_ib_tso_caps tso_caps; 104 struct mlx5_ib_rss_caps rss_caps; 105 struct mlx5_ib_cqe_comp_caps cqe_comp_caps; 106 struct mlx5_packet_pacing_caps packet_pacing_caps; 107 __u32 mlx5_ib_support_multi_pkt_send_wqes; 108 __u32 reserved; 109 }; 110 struct mlx5_ib_create_cq { 111 __u64 buf_addr; 112 __u64 db_addr; 113 __u32 cqe_size; 114 __u8 cqe_comp_en; 115 __u8 cqe_comp_res_format; 116 __u16 reserved; 117 }; 118 struct mlx5_ib_create_cq_resp { 119 __u32 cqn; 120 __u32 reserved; 121 }; 122 struct mlx5_ib_resize_cq { 123 __u64 buf_addr; 124 __u16 cqe_size; 125 __u16 reserved0; 126 __u32 reserved1; 127 }; 128 struct mlx5_ib_create_srq { 129 __u64 buf_addr; 130 __u64 db_addr; 131 __u32 flags; 132 __u32 reserved0; 133 __u32 uidx; 134 __u32 reserved1; 135 }; 136 struct mlx5_ib_create_srq_resp { 137 __u32 srqn; 138 __u32 reserved; 139 }; 140 struct mlx5_ib_create_qp { 141 __u64 buf_addr; 142 __u64 db_addr; 143 __u32 sq_wqe_count; 144 __u32 rq_wqe_count; 145 __u32 rq_wqe_shift; 146 __u32 flags; 147 __u32 uidx; 148 __u32 reserved0; 149 __u64 sq_buf_addr; 150 }; 151 enum mlx5_rx_hash_function_flags { 152 MLX5_RX_HASH_FUNC_TOEPLITZ = 1 << 0, 153 }; 154 enum mlx5_rx_hash_fields { 155 MLX5_RX_HASH_SRC_IPV4 = 1 << 0, 156 MLX5_RX_HASH_DST_IPV4 = 1 << 1, 157 MLX5_RX_HASH_SRC_IPV6 = 1 << 2, 158 MLX5_RX_HASH_DST_IPV6 = 1 << 3, 159 MLX5_RX_HASH_SRC_PORT_TCP = 1 << 4, 160 MLX5_RX_HASH_DST_PORT_TCP = 1 << 5, 161 MLX5_RX_HASH_SRC_PORT_UDP = 1 << 6, 162 MLX5_RX_HASH_DST_PORT_UDP = 1 << 7 163 }; 164 struct mlx5_ib_create_qp_rss { 165 __u64 rx_hash_fields_mask; 166 __u8 rx_hash_function; 167 __u8 rx_key_len; 168 __u8 reserved[6]; 169 __u8 rx_hash_key[128]; 170 __u32 comp_mask; 171 __u32 reserved1; 172 }; 173 struct mlx5_ib_create_qp_resp { 174 __u32 uuar_index; 175 }; 176 struct mlx5_ib_alloc_mw { 177 __u32 comp_mask; 178 __u8 num_klms; 179 __u8 reserved1; 180 __u16 reserved2; 181 }; 182 struct mlx5_ib_create_wq { 183 __u64 buf_addr; 184 __u64 db_addr; 185 __u32 rq_wqe_count; 186 __u32 rq_wqe_shift; 187 __u32 user_index; 188 __u32 flags; 189 __u32 comp_mask; 190 __u32 reserved; 191 }; 192 struct mlx5_ib_create_ah_resp { 193 __u32 response_length; 194 __u8 dmac[ETH_ALEN]; 195 __u8 reserved[6]; 196 }; 197 struct mlx5_ib_create_wq_resp { 198 __u32 response_length; 199 __u32 reserved; 200 }; 201 struct mlx5_ib_create_rwq_ind_tbl_resp { 202 __u32 response_length; 203 __u32 reserved; 204 }; 205 struct mlx5_ib_modify_wq { 206 __u32 comp_mask; 207 __u32 reserved; 208 }; 209 #endif 210