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1/*
2 * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * Redistributions of source code must retain the above copyright notice, this
8 * list of conditions and the following disclaimer.
9 *
10 * Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
13 *
14 * Neither the name of ARM nor the names of its contributors may be used
15 * to endorse or promote products derived from this software without specific
16 * prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28 * POSSIBILITY OF SUCH DAMAGE.
29 */
30
31#include <arch.h>
32#include <asm_macros.S>
33#include <bl_common.h>
34#include <runtime_svc.h>
35
36	.globl	bl1_exceptions
37
38	.section	.vectors, "ax"; .align 11
39
40	/* -----------------------------------------------------
41	 * Very simple stackless exception handlers used by BL1.
42	 * -----------------------------------------------------
43	 */
44	.align	7
45bl1_exceptions:
46	/* -----------------------------------------------------
47	 * Current EL with SP0 : 0x0 - 0x200
48	 * -----------------------------------------------------
49	 */
50SynchronousExceptionSP0:
51	mov	x0, #SYNC_EXCEPTION_SP_EL0
52	bl	plat_report_exception
53	b	SynchronousExceptionSP0
54	check_vector_size SynchronousExceptionSP0
55
56	.align	7
57IrqSP0:
58	mov	x0, #IRQ_SP_EL0
59	bl	plat_report_exception
60	b	IrqSP0
61	check_vector_size IrqSP0
62
63	.align	7
64FiqSP0:
65	mov	x0, #FIQ_SP_EL0
66	bl	plat_report_exception
67	b	FiqSP0
68	check_vector_size FiqSP0
69
70	.align	7
71SErrorSP0:
72	mov	x0, #SERROR_SP_EL0
73	bl	plat_report_exception
74	b	SErrorSP0
75	check_vector_size SErrorSP0
76
77	/* -----------------------------------------------------
78	 * Current EL with SPx: 0x200 - 0x400
79	 * -----------------------------------------------------
80	 */
81	.align	7
82SynchronousExceptionSPx:
83	mov	x0, #SYNC_EXCEPTION_SP_ELX
84	bl	plat_report_exception
85	b	SynchronousExceptionSPx
86	check_vector_size SynchronousExceptionSPx
87
88	.align	7
89IrqSPx:
90	mov	x0, #IRQ_SP_ELX
91	bl	plat_report_exception
92	b	IrqSPx
93	check_vector_size IrqSPx
94
95	.align	7
96FiqSPx:
97	mov	x0, #FIQ_SP_ELX
98	bl	plat_report_exception
99	b	FiqSPx
100	check_vector_size FiqSPx
101
102	.align	7
103SErrorSPx:
104	mov	x0, #SERROR_SP_ELX
105	bl	plat_report_exception
106	b	SErrorSPx
107	check_vector_size SErrorSPx
108
109	/* -----------------------------------------------------
110	 * Lower EL using AArch64 : 0x400 - 0x600
111	 * -----------------------------------------------------
112	 */
113	.align	7
114SynchronousExceptionA64:
115	/* Enable the SError interrupt */
116	msr	daifclr, #DAIF_ABT_BIT
117
118	/* ------------------------------------------------
119	 * Only a single SMC exception from BL2 to ask
120	 * BL1 to pass EL3 control to BL31 is expected
121	 * here.
122	 * It expects X0 with RUN_IMAGE SMC function id
123	 * X1 with address of a entry_point_info_t structure
124	 * describing the BL3-1 entrypoint
125	 * ------------------------------------------------
126	 */
127	mov	x19, x0
128	mov	x20, x1
129
130	mrs	x0, esr_el3
131	ubfx	x1, x0, #ESR_EC_SHIFT, #ESR_EC_LENGTH
132	cmp	x1, #EC_AARCH64_SMC
133	b.ne	panic
134
135	mov	x0, #RUN_IMAGE
136	cmp	x19, x0
137	b.ne	panic
138
139	mov	x0, x20
140	bl	display_boot_progress
141
142	ldp	x0, x1, [x20, #ENTRY_POINT_INFO_PC_OFFSET]
143	msr	elr_el3, x0
144	msr	spsr_el3, x1
145	ubfx	x0, x1, #MODE_EL_SHIFT, #2
146	cmp	x0, #MODE_EL3
147	b.ne	panic
148
149	bl	disable_mmu_icache_el3
150	tlbi	alle3
151
152	ldp	x6, x7, [x20, #(ENTRY_POINT_INFO_ARGS_OFFSET + 0x30)]
153	ldp	x4, x5, [x20, #(ENTRY_POINT_INFO_ARGS_OFFSET + 0x20)]
154	ldp	x2, x3, [x20, #(ENTRY_POINT_INFO_ARGS_OFFSET + 0x10)]
155	ldp	x0, x1, [x20, #(ENTRY_POINT_INFO_ARGS_OFFSET + 0x0)]
156	eret
157panic:
158	mov	x0, #SYNC_EXCEPTION_AARCH64
159	bl	plat_report_exception
160
161	wfi
162	b	panic
163	check_vector_size SynchronousExceptionA64
164
165	.align	7
166IrqA64:
167	mov	x0, #IRQ_AARCH64
168	bl	plat_report_exception
169	b	IrqA64
170	check_vector_size IrqA64
171
172	.align	7
173FiqA64:
174	mov	x0, #FIQ_AARCH64
175	bl	plat_report_exception
176	b	FiqA64
177	check_vector_size FiqA64
178
179	.align	7
180SErrorA64:
181	mov	x0, #SERROR_AARCH64
182	bl	plat_report_exception
183	b   	SErrorA64
184	check_vector_size SErrorA64
185
186	/* -----------------------------------------------------
187	 * Lower EL using AArch32 : 0x600 - 0x800
188	 * -----------------------------------------------------
189	 */
190	.align	7
191SynchronousExceptionA32:
192	mov	x0, #SYNC_EXCEPTION_AARCH32
193	bl	plat_report_exception
194	b	SynchronousExceptionA32
195	check_vector_size SynchronousExceptionA32
196
197	.align	7
198IrqA32:
199	mov	x0, #IRQ_AARCH32
200	bl	plat_report_exception
201	b	IrqA32
202	check_vector_size IrqA32
203
204	.align	7
205FiqA32:
206	mov	x0, #FIQ_AARCH32
207	bl	plat_report_exception
208	b	FiqA32
209	check_vector_size FiqA32
210
211	.align	7
212SErrorA32:
213	mov	x0, #SERROR_AARCH32
214	bl	plat_report_exception
215	b	SErrorA32
216	check_vector_size SErrorA32
217