1# 2# Copyright (c) 2014, ARM Limited. All rights reserved. 3# 4# This program and the accompanying materials are licensed and made available 5# under the terms and conditions of the BSD License which accompanies this 6# distribution. The full text of the license may be found at 7# http://opensource.org/licenses/bsd-license.php 8# 9# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, 10# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. 11# 12# 13 14#include <AsmMacroIoLibV8.h> 15 16#if !defined(__clang__) 17 18// 19// Clang versions before v3.6 do not support the GNU extension that allows 20// system registers outside of the IMPLEMENTATION DEFINED range to be specified 21// using the generic notation below. However, clang knows these registers by 22// their architectural names, so it has no need for these aliases anyway. 23// 24#define ICC_SRE_EL1 S3_0_C12_C12_5 25#define ICC_SRE_EL2 S3_4_C12_C9_5 26#define ICC_SRE_EL3 S3_6_C12_C12_5 27#define ICC_IGRPEN1_EL1 S3_0_C12_C12_7 28#define ICC_EOIR1_EL1 S3_0_C12_C12_1 29#define ICC_IAR1_EL1 S3_0_C12_C12_0 30#define ICC_PMR_EL1 S3_0_C4_C6_0 31#define ICC_BPR1_EL1 S3_0_C12_C12_3 32 33#endif 34 35.text 36.align 2 37 38GCC_ASM_EXPORT(ArmGicV3GetControlSystemRegisterEnable) 39GCC_ASM_EXPORT(ArmGicV3SetControlSystemRegisterEnable) 40GCC_ASM_EXPORT(ArmGicV3EnableInterruptInterface) 41GCC_ASM_EXPORT(ArmGicV3DisableInterruptInterface) 42GCC_ASM_EXPORT(ArmGicV3EndOfInterrupt) 43GCC_ASM_EXPORT(ArmGicV3AcknowledgeInterrupt) 44GCC_ASM_EXPORT(ArmGicV3SetPriorityMask) 45GCC_ASM_EXPORT(ArmGicV3SetBinaryPointer) 46 47//UINT32 48//EFIAPI 49//ArmGicV3GetControlSystemRegisterEnable ( 50// VOID 51// ); 52ASM_PFX(ArmGicV3GetControlSystemRegisterEnable): 53 EL1_OR_EL2_OR_EL3(x1) 541: mrs x0, ICC_SRE_EL1 55 b 4f 562: mrs x0, ICC_SRE_EL2 57 b 4f 583: mrs x0, ICC_SRE_EL3 594: ret 60 61//VOID 62//EFIAPI 63//ArmGicV3SetControlSystemRegisterEnable ( 64// IN UINT32 ControlSystemRegisterEnable 65// ); 66ASM_PFX(ArmGicV3SetControlSystemRegisterEnable): 67 EL1_OR_EL2_OR_EL3(x1) 681: msr ICC_SRE_EL1, x0 69 b 4f 702: msr ICC_SRE_EL2, x0 71 b 4f 723: msr ICC_SRE_EL3, x0 734: isb 74 ret 75 76//VOID 77//ArmGicV3EnableInterruptInterface ( 78// VOID 79// ); 80ASM_PFX(ArmGicV3EnableInterruptInterface): 81 mov x0, #1 82 msr ICC_IGRPEN1_EL1, x0 83 ret 84 85//VOID 86//ArmGicV3DisableInterruptInterface ( 87// VOID 88// ); 89ASM_PFX(ArmGicV3DisableInterruptInterface): 90 mov x0, #0 91 msr ICC_IGRPEN1_EL1, x0 92 ret 93 94//VOID 95//ArmGicV3EndOfInterrupt ( 96// IN UINTN InterruptId 97// ); 98ASM_PFX(ArmGicV3EndOfInterrupt): 99 msr ICC_EOIR1_EL1, x0 100 ret 101 102//UINTN 103//ArmGicV3AcknowledgeInterrupt ( 104// VOID 105// ); 106ASM_PFX(ArmGicV3AcknowledgeInterrupt): 107 mrs x0, ICC_IAR1_EL1 108 ret 109 110//VOID 111//ArmGicV3SetPriorityMask ( 112// IN UINTN Priority 113// ); 114ASM_PFX(ArmGicV3SetPriorityMask): 115 msr ICC_PMR_EL1, x0 116 ret 117 118//VOID 119//ArmGicV3SetBinaryPointer ( 120// IN UINTN BinaryPoint 121// ); 122ASM_PFX(ArmGicV3SetBinaryPointer): 123 msr ICC_BPR1_EL1, x0 124 ret 125