1#------------------------------------------------------------------------------ 2# 3# Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR> 4# Copyright (c) 2011 - 2014, ARM Limited. All rights reserved. 5# 6# This program and the accompanying materials 7# are licensed and made available under the terms and conditions of the BSD License 8# which accompanies this distribution. The full text of the license may be found at 9# http://opensource.org/licenses/bsd-license.php 10# 11# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, 12# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. 13# 14#------------------------------------------------------------------------------ 15 16#include <AsmMacroIoLib.h> 17 18.text 19.align 2 20GCC_ASM_EXPORT(ArmReadMidr) 21GCC_ASM_EXPORT(ArmCacheInfo) 22GCC_ASM_EXPORT(ArmGetInterruptState) 23GCC_ASM_EXPORT(ArmGetFiqState) 24GCC_ASM_EXPORT(ArmGetTTBR0BaseAddress) 25GCC_ASM_EXPORT(ArmSetTTBR0) 26GCC_ASM_EXPORT(ArmSetDomainAccessControl) 27GCC_ASM_EXPORT(CPSRMaskInsert) 28GCC_ASM_EXPORT(CPSRRead) 29GCC_ASM_EXPORT(ArmReadCpacr) 30GCC_ASM_EXPORT(ArmWriteCpacr) 31GCC_ASM_EXPORT(ArmWriteAuxCr) 32GCC_ASM_EXPORT(ArmReadAuxCr) 33GCC_ASM_EXPORT(ArmInvalidateTlb) 34GCC_ASM_EXPORT(ArmUpdateTranslationTableEntry) 35GCC_ASM_EXPORT(ArmReadScr) 36GCC_ASM_EXPORT(ArmWriteScr) 37GCC_ASM_EXPORT(ArmReadMVBar) 38GCC_ASM_EXPORT(ArmWriteMVBar) 39GCC_ASM_EXPORT(ArmReadHVBar) 40GCC_ASM_EXPORT(ArmWriteHVBar) 41GCC_ASM_EXPORT(ArmCallWFE) 42GCC_ASM_EXPORT(ArmCallSEV) 43GCC_ASM_EXPORT(ArmReadSctlr) 44GCC_ASM_EXPORT(ArmReadCpuActlr) 45GCC_ASM_EXPORT(ArmWriteCpuActlr) 46 47#------------------------------------------------------------------------------ 48 49ASM_PFX(ArmReadMidr): 50 mrc p15,0,R0,c0,c0,0 51 bx LR 52 53ASM_PFX(ArmCacheInfo): 54 mrc p15,0,R0,c0,c0,1 55 bx LR 56 57ASM_PFX(ArmGetInterruptState): 58 mrs R0,CPSR 59 tst R0,#0x80 @Check if IRQ is enabled. 60 moveq R0,#1 61 movne R0,#0 62 bx LR 63 64ASM_PFX(ArmGetFiqState): 65 mrs R0,CPSR 66 tst R0,#0x40 @Check if FIQ is enabled. 67 moveq R0,#1 68 movne R0,#0 69 bx LR 70 71ASM_PFX(ArmSetDomainAccessControl): 72 mcr p15,0,r0,c3,c0,0 73 bx lr 74 75ASM_PFX(CPSRMaskInsert): @ on entry, r0 is the mask and r1 is the field to insert 76 stmfd sp!, {r4-r12, lr} @ save all the banked registers 77 mov r3, sp @ copy the stack pointer into a non-banked register 78 mrs r2, cpsr @ read the cpsr 79 bic r2, r2, r0 @ clear mask in the cpsr 80 and r1, r1, r0 @ clear bits outside the mask in the input 81 orr r2, r2, r1 @ set field 82 msr cpsr_cxsf, r2 @ write back cpsr (may have caused a mode switch) 83 isb 84 mov sp, r3 @ restore stack pointer 85 ldmfd sp!, {r4-r12, lr} @ restore registers 86 bx lr @ return (hopefully thumb-safe!) 87 88ASM_PFX(CPSRRead): 89 mrs r0, cpsr 90 bx lr 91 92ASM_PFX(ArmReadCpacr): 93 mrc p15, 0, r0, c1, c0, 2 94 bx lr 95 96ASM_PFX(ArmWriteCpacr): 97 mcr p15, 0, r0, c1, c0, 2 98 isb 99 bx lr 100 101ASM_PFX(ArmWriteAuxCr): 102 mcr p15, 0, r0, c1, c0, 1 103 bx lr 104 105ASM_PFX(ArmReadAuxCr): 106 mrc p15, 0, r0, c1, c0, 1 107 bx lr 108 109ASM_PFX(ArmSetTTBR0): 110 mcr p15,0,r0,c2,c0,0 111 isb 112 bx lr 113 114ASM_PFX(ArmGetTTBR0BaseAddress): 115 mrc p15,0,r0,c2,c0,0 116 LoadConstantToReg(0xFFFFC000, r1) 117 and r0, r0, r1 118 isb 119 bx lr 120 121// 122//VOID 123//ArmUpdateTranslationTableEntry ( 124// IN VOID *TranslationTableEntry // R0 125// IN VOID *MVA // R1 126// ); 127ASM_PFX(ArmUpdateTranslationTableEntry): 128 mcr p15,0,R0,c7,c14,1 @ DCCIMVAC Clean data cache by MVA 129 dsb 130 mcr p15,0,R1,c8,c7,1 @ TLBIMVA TLB Invalidate MVA 131 mcr p15,0,R9,c7,c5,6 @ BPIALL Invalidate Branch predictor array. R9 == NoOp 132 dsb 133 isb 134 bx lr 135 136ASM_PFX(ArmInvalidateTlb): 137 mov r0,#0 138 mcr p15,0,r0,c8,c7,0 139 mcr p15,0,R9,c7,c5,6 @ BPIALL Invalidate Branch predictor array. R9 == NoOp 140 dsb 141 isb 142 bx lr 143 144ASM_PFX(ArmReadScr): 145 mrc p15, 0, r0, c1, c1, 0 146 bx lr 147 148ASM_PFX(ArmWriteScr): 149 mcr p15, 0, r0, c1, c1, 0 150 bx lr 151 152ASM_PFX(ArmReadHVBar): 153 mrc p15, 4, r0, c12, c0, 0 154 bx lr 155 156ASM_PFX(ArmWriteHVBar): 157 mcr p15, 4, r0, c12, c0, 0 158 bx lr 159 160ASM_PFX(ArmReadMVBar): 161 mrc p15, 0, r0, c12, c0, 1 162 bx lr 163 164ASM_PFX(ArmWriteMVBar): 165 mcr p15, 0, r0, c12, c0, 1 166 bx lr 167 168ASM_PFX(ArmCallWFE): 169 wfe 170 bx lr 171 172ASM_PFX(ArmCallSEV): 173 sev 174 bx lr 175 176ASM_PFX(ArmReadSctlr): 177 mrc p15, 0, r0, c1, c0, 0 @ Read SCTLR into R0 (Read control register configuration data) 178 bx lr 179 180ASM_PFX(ArmReadCpuActlr): 181 mrc p15, 0, r0, c1, c0, 1 182 bx lr 183 184ASM_PFX(ArmWriteCpuActlr): 185 mcr p15, 0, r0, c1, c0, 1 186 dsb 187 isb 188 bx lr 189 190ASM_FUNCTION_REMOVE_IF_UNREFERENCED 191