1/** @file 2This file describes the contents of the ACPI Fixed ACPI Description Table 3(FADT). Some additional ACPI values are defined in Acpi1_0.h and Acpi2_0.h. 4All changes to the FADT contents should be done in this file. 5 6Copyright (c) 2013-2015 Intel Corporation. 7 8This program and the accompanying materials 9are licensed and made available under the terms and conditions of the BSD License 10which accompanies this distribution. The full text of the license may be found at 11http://opensource.org/licenses/bsd-license.php 12 13THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, 14WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. 15 16**/ 17 18#include "Fadt.h" 19 20EFI_ACPI_2_0_FIXED_ACPI_DESCRIPTION_TABLE FADT = { 21 { 22 EFI_ACPI_2_0_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE, 23 sizeof (EFI_ACPI_2_0_FIXED_ACPI_DESCRIPTION_TABLE), 24 EFI_ACPI_2_0_FIXED_ACPI_DESCRIPTION_TABLE_REVISION, 25 0, // to make sum of entire table == 0 26 {EFI_ACPI_OEM_ID}, // OEMID is a 6 bytes long field 27 EFI_ACPI_OEM_TABLE_ID,// OEM table identification(8 bytes long) 28 EFI_ACPI_OEM_REVISION,// OEM revision number 29 EFI_ACPI_CREATOR_ID, // ASL compiler vendor ID 30 EFI_ACPI_CREATOR_REVISION // ASL compiler revision number 31 }, 32 0, // Physical addesss of FACS 33 0, // Physical address of DSDT 34 RESERVED, // reserved 35 PM_PROFILE, // Preferred powermanagement profile 36 SCI_INT_VECTOR, // System vector of SCI interrupt 37 ACPI_RUNTIME_UPDATE, // Port address of SMI command port 38 ACPI_ENABLE, // value to write to port smi_cmd to enable ACPI 39 ACPI_DISABLE, // value to write to port smi_cmd to disable ACPI 40 S4BIOS_REQ, // Value to write to SMI CMD port to enter the S4BIOS state 41 RESERVED, // reserved - must be zero 42 ACPI_RUNTIME_UPDATE, // Port address of Power Mgt 1a Event Reg Blk 43 PM1b_EVT_BLK_ADDRESS, // Port address of Power Mgt 1b Event Reg Blk 44 ACPI_RUNTIME_UPDATE, // Port address of Power Mgt 1a Ctrl Reg Blk 45 PM1b_CNT_BLK_ADDRESS, // Port address of Power Mgt 1b Ctrl Reg Blk 46 ACPI_RUNTIME_UPDATE, // Port address of Power Mgt 2 Ctrl Reg Blk 47 ACPI_RUNTIME_UPDATE, // Port address of Power Mgt Timer Ctrl Reg Blk 48 ACPI_RUNTIME_UPDATE, // Port addr of General Purpose Event 0 Reg Blk 49 GPE1_BLK_ADDRESS, // Port addr of General Purpose Event 1 Reg Blk 50 PM1_EVT_LEN, // Byte Length of ports at pm1X_evt_blk 51 PM1_CNT_LEN, // Byte Length of ports at pm1X_cnt_blk 52 PM2_CNT_LEN, // Byte Length of ports at pm2_cnt_blk 53 PM_TM_LEN, // Byte Length of ports at pm_tm_blk 54 GPE0_BLK_LEN, // Byte Length of ports at gpe0_blk 55 GPE1_BLK_LEN, // Byte Length of ports at gpe1_blk 56 GPE1_BASE, // offset in gpe model where gpe1 events start 57 RESERVED, // reserved 58 P_LVL2_LAT, // worst case HW latency to enter/exit C2 state 59 P_LVL3_LAT, // worst case HW latency to enter/exit C3 state 60 FLUSH_SIZE, // Size of area read to flush caches 61 FLUSH_STRIDE, // Stride used in flushing caches 62 DUTY_OFFSET, // bit location of duty cycle field in p_cnt reg 63 DUTY_WIDTH, // bit width of duty cycle field in p_cnt reg 64 DAY_ALRM, // index to day-of-month alarm in RTC CMOS RAM 65 MON_ALRM, // index to month-of-year alarm in RTC CMOS RAM 66 CENTURY, // index to century in RTC CMOS RAM 67 IAPC_BOOT_ARCH, // IA-PC Boot Architecture Flags 68 RESERVED, // reserved 69 FLAG2, // Fixed feature flags 70 71 { 72 RESET_REG_ADDRESS_SPACE_ID, // Address of the reset register 73 RESET_REG_BIT_WIDTH, 74 RESET_REG_BIT_OFFSET, 75 RESERVED, 76 RESET_REG_ADDRESS 77 }, 78 RESET_VALUE, // Value to write to the RESET_REG port 79 { 80 RESERVED, 81 RESERVED, 82 RESERVED 83 }, 84 0, // 64Bit physical addesss of FACS 85 0, // 64Bit physical address of DSDT 86 87 { 88 PM1a_EVT_BLK_ADDRESS_SPACE_ID, // Extended Port address of Power Mgt 1a Event Reg Blk 89 PM1a_EVT_BLK_BIT_WIDTH, 90 PM1a_EVT_BLK_BIT_OFFSET, 91 RESERVED, 92 ACPI_RUNTIME_UPDATE 93 }, 94 95 { 96 PM1b_EVT_BLK_ADDRESS_SPACE_ID, // Extended Port address of Power Mgt 1b Event Reg Blk 97 PM1b_EVT_BLK_BIT_WIDTH, 98 PM1b_EVT_BLK_BIT_OFFSET, 99 RESERVED, 100 PM1b_EVT_BLK_ADDRESS 101 }, 102 103 { 104 PM1a_CNT_BLK_ADDRESS_SPACE_ID, // Extended Port address of Power Mgt 1a Ctrl Reg Blk 105 PM1a_CNT_BLK_BIT_WIDTH, 106 PM1a_CNT_BLK_BIT_OFFSET, 107 RESERVED, 108 ACPI_RUNTIME_UPDATE 109 }, 110 111 { 112 PM1b_CNT_BLK_ADDRESS_SPACE_ID, // Extended Port address of Power Mgt 1b Ctrl Reg Blk 113 PM1b_CNT_BLK_BIT_WIDTH, 114 PM1b_CNT_BLK_BIT_OFFSET, 115 RESERVED, 116 PM1b_CNT_BLK_ADDRESS 117 }, 118 119 { 120 PM2_CNT_BLK_ADDRESS_SPACE_ID, // Extended Port address of Power Mgt 2 Ctrl Reg Blk 121 PM2_CNT_BLK_BIT_WIDTH, 122 PM2_CNT_BLK_BIT_OFFSET, 123 RESERVED, 124 ACPI_RUNTIME_UPDATE 125 }, 126 127 { 128 PM_TMR_BLK_ADDRESS_SPACE_ID, // Extended Port address of Power Mgt Timer Ctrl Reg Blk 129 PM_TMR_BLK_BIT_WIDTH, 130 PM_TMR_BLK_BIT_OFFSET, 131 RESERVED, 132 ACPI_RUNTIME_UPDATE 133 }, 134 135 { 136 GPE0_BLK_ADDRESS_SPACE_ID, // Extended Port address of General Purpose Event 0 Reg Blk 137 GPE0_BLK_BIT_WIDTH, 138 GPE0_BLK_BIT_OFFSET, 139 RESERVED, 140 ACPI_RUNTIME_UPDATE 141 }, 142 143 { 144 GPE1_BLK_ADDRESS_SPACE_ID, // Extended Port address of General Purpose Event 1 Reg Blk 145 GPE1_BLK_BIT_WIDTH, 146 GPE1_BLK_BIT_OFFSET, 147 RESERVED, 148 GPE1_BLK_ADDRESS 149 } 150}; 151 152VOID* 153ReferenceAcpiTable ( 154 VOID 155 ) 156 157{ 158 // 159 // Reference the table being generated to prevent the optimizer from removing the 160 // data structure from the exeutable 161 // 162 return (VOID*)&FADT; 163} 164