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1 /**
2   Copyright (c) 2009 - 2013, Intel Corporation. All rights reserved.<BR>
3   This program and the accompanying materials
4   are licensed and made available under the terms and conditions of the BSD License
5   which accompanies this distribution.  The full text of the license may be found at
6   http://opensource.org/licenses/bsd-license.php
7 
8   THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
9   WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
10 
11 **/
12 /*++
13 
14 Module Name:
15 
16   PpmPlatformPolicy.h
17 
18 Abstract:
19 
20   Interface definition details between PPM and platform drivers during DXE phase.
21 
22 --*/
23 #ifndef _PPM_PLATFORM_POLICY_H_
24 #define _PPM_PLATFORM_POLICY_H_
25 
26 //
27 //  PPM policy provided by platform for DXE phase {DDABFEAC-EF63-452c-8F39-ED7FAED8265E}
28 //
29 #define PPM_PLATFORM_POLICY_PROTOCOL_GUID \
30   {0xddabfeac, 0xef63, 0x452c, 0x8f, 0x39, 0xed, 0x7f, 0xae, 0xd8, 0x26, 0x5e}
31 
32 //
33 // Extern the GUID for protocol users.
34 //
35 extern EFI_GUID gPpmPlatformPolicyProtocolGuid;
36 
37 //
38 // Forward reference for ANSI C compatibility
39 //
40 typedef struct _PPM_PLATFORM_POLICY_PROTOCOL PPM_PLATFORM_POLICY_PROTOCOL;
41 
42 //
43 // Protocol revision number
44 // Any backwards compatible changes to this protocol will result in an update in the revision number
45 // Major changes will require publication of a new protocol
46 //
47 // Revision 1: Original version
48 // Revision 2: Added T-states field to the PPM_FUNCTION_ENABLES structure, Renamed unused fields - CxPopUpEnable, CxPopDownEnable, FastC4ExitEnable
49 // Revision 3: Extended VidCpuid to 32 bits for extended CPUID support (Penryn)
50 // Revision 4: Added support for extended C6 residency enabling
51 //
52 #define PPM_PLATFORM_POLICY_PROTOCOL_REVISION     1
53 #define PPM_PLATFORM_POLICY_PROTOCOL_REVISION_2   2
54 #define PPM_PLATFORM_POLICY_PROTOCOL_REVISION_3   3
55 #define PPM_PLATFORM_POLICY_PROTOCOL_REVISION_4   4
56 
57 //
58 // Define maximum number of custom VID states supported
59 //
60 #ifndef MAX_CUSTOM_VID_TABLE_STATES
61 #define MAX_CUSTOM_VID_TABLE_STATES               6
62 #endif
63 //
64 // Custom VID table
65 //
66 typedef struct {
67   UINT8   VidNumber;
68   UINT32  VidCpuid;
69   UINT16  VidMaxRatio;
70   UINT16  VidMaxVid;
71   UINT16  StateRatio[MAX_CUSTOM_VID_TABLE_STATES];
72   UINT16  StateVid[MAX_CUSTOM_VID_TABLE_STATES];
73 } PPM_CUSTOM_VID_TABLE;
74 
75 //
76 // PPM functional enables
77 //
78 typedef struct {
79   UINT8   EnableGv                   :1; // 0: Disabled; 1: Enabled
80   UINT8   EnableCx                   :1;
81   UINT8   EnableCxe                  :1;
82   UINT8   EnableC4                   :1;
83   UINT8   EnableC6                   :1;
84   UINT8   EnableC7                   :1;
85   UINT8   EnableTm                   :1;
86   UINT8   Reserve00                  :1;
87   UINT8   Reserve01                  :1;
88   UINT8   EnableTurboMode            :1;
89   UINT8   PowerLimit2                :1;
90   UINT8   EnableProcHot              :1;
91   UINT8   Reserve02                  :1;
92   UINT8   EnableCMP                  :1;
93   UINT8   TStatesEnable              :1;
94   UINT8   Reserve03                  :1;
95   UINT8   Reserve04                  ;
96 
97 } PPM_FUNCTION_ENABLES;
98 
99 
100 //
101 // PPM Turbo settings
102 //
103 typedef struct _PPM_TURBO_SETTINGS {
104   UINT16  PowerLimit1;
105   UINT32  PowerLimit1Time;
106   UINT16  PowerLimit2;
107   UINT8   TurboPowerLimitLock;
108 } PPM_TURBO_SETTINGS;
109 
110 //
111 // Platform Policy
112 //
113 struct _PPM_PLATFORM_POLICY_PROTOCOL {
114   UINT8                                 Revision;
115   PPM_FUNCTION_ENABLES                  FunctionEnables;
116   PPM_CUSTOM_VID_TABLE                  CustomVidTable;
117   PPM_TURBO_SETTINGS                    TurboSettings;
118 
119   UINT8                                 Reserve00;
120   UINT8                                 Reserve01;
121   UINT8                                 Reserve02;
122   UINT8                                 Reserve03;
123   UINT8                                 Reserve04;
124   UINT8                                 Reserve05;
125   UINT8                                 Reserve06;
126 
127   UINT8                                 S3RestoreMsrSwSmiNumber;
128   UINT8                                 Reserve07;
129   UINT32                                Reserve08;
130   UINT8                                 Reserve09;
131   //
132   // Primary and Secondary Plane Current Limits
133   //
134   UINT16                                Reserve10;
135   UINT8                                 Reserve11;
136 };
137 
138 #endif
139