1%mask {s} 1 2%mask {w} 1 3%mask {w1} 1 4%mask {W1} 1 5%mask {W2} 1 6dnl floating point reg suffix 7%mask {D} 1 8%mask {imm8} 8 9%mask {imms8} 8 10%mask {imm16} 16 11%mask {reg} 3 12%mask {oreg} 3 13%mask {reg16} 3 14%mask {reg64} 3 15%mask {tttn} 4 16%mask {mod} 2 17%mask {moda} 2 18%mask {MOD} 2 19%mask {r_m} 3 20dnl like {r_m} but referencing byte register 21%mask {8r_m} 3 22dnl like {r_m} but referencing 16-bit register 23%mask {16r_m} 3 24dnl like {r_m} but referencing 32- or 64-bit register 25%mask {64r_m} 3 26%mask {disp8} 8 27dnl imm really is 8/16/32 bit depending on the situation. 28%mask {imm} 8 29%mask {imm64} 8 30%mask {imms} 8 31%mask {rel} 32 32%mask {abs} 32 33%mask {absval} 32 34%mask {sel} 16 35%mask {imm32} 32 36%mask {ccc} 3 37%mask {ddd} 3 38%mask {sreg3} 3 39%mask {sreg2} 2 40%mask {mmxreg} 3 41%mask {R_M} 3 42%mask {Mod} 2 43%mask {xmmreg} 3 44%mask {R_m} 3 45%mask {xmmreg1} 3 46%mask {xmmreg2} 3 47%mask {mmxreg1} 3 48%mask {mmxreg2} 3 49%mask {predps} 8 50%mask {freg} 3 51%mask {fmod} 2 52%mask {fr_m} 3 53%prefix {R} 54%prefix {RE} 55%suffix {W} 56%suffix {w0} 57%synonym {xmmreg1} {xmmreg} 58%synonym {xmmreg2} {xmmreg} 59%synonym {mmxreg1} {mmxreg} 60%synonym {mmxreg2} {mmxreg} 61ifdef(`i386', 62`%synonym {oreg} {reg} 63%synonym {imm64} {imm} 64')dnl 65 66%% 67ifdef(`i386', 68`00110111:aaa 6911010101,00001010:aad 7011010100,00001010:aam 7100111111:aas 72')dnl 730001010{w},{imm}:adc {imm}{w},{ax}{w} 741000000{w},{mod}010{r_m},{imm}:adc{w} {imm}{w},{mod}{r_m}{w} 751000001{w},{mod}010{r_m},{imms8}:adc{w} {imms8},{mod}{r_m} 760001000{w},{mod}{reg}{r_m}:adc {reg}{w},{mod}{r_m}{w} 770001001{w},{mod}{reg}{r_m}:adc {mod}{r_m}{w},{reg}{w} 780000010{w},{imm}:add {imm}{w},{ax}{w} 791000000{w},{mod}000{r_m},{imm}:add{w} {imm}{w},{mod}{r_m}{w} 8010000011,{mod}000{r_m},{imms8}:add{w} {imms8},{mod}{r_m} 810000000{w},{mod}{reg}{r_m}:add {reg}{w},{mod}{r_m}{w} 820000001{w},{mod}{reg}{r_m}:add {mod}{r_m}{w},{reg}{w} 8301100110,00001111,11010000,{Mod}{xmmreg}{R_m}:addsubpd {Mod}{R_m},{xmmreg} 8411110010,00001111,11010000,{Mod}{xmmreg}{R_m}:addsubps {Mod}{R_m},{xmmreg} 850010010{w},{imm}:and {imm}{w},{ax}{w} 861000000{w},{mod}100{r_m},{imm}:and{w} {imm}{w},{mod}{r_m}{w} 871000001{w},{mod}100{r_m},{imms8}:and{w} {imms8},{mod}{r_m} 880010000{w},{mod}{reg}{r_m}:and {reg}{w},{mod}{r_m}{w} 890010001{w},{mod}{reg}{r_m}:and {mod}{r_m}{w},{reg}{w} 9001100110,00001111,01010100,{Mod}{xmmreg}{R_m}:andpd {Mod}{R_m},{xmmreg} 9100001111,01010100,{Mod}{xmmreg}{R_m}:andps {Mod}{R_m},{xmmreg} 9201100110,00001111,01010101,{Mod}{xmmreg}{R_m}:andnpd {Mod}{R_m},{xmmreg} 9300001111,01010101,{Mod}{xmmreg}{R_m}:andnps {Mod}{R_m},{xmmreg} 94ifdef(`i386', 95`01100011,{mod}{reg16}{r_m}:arpl {reg16},{mod}{r_m} 9601100010,{moda}{reg}{r_m}:bound {reg},{moda}{r_m} 97', 98`01100011,{mod}{reg64}{r_m}:movslq {mod}{r_m},{reg64} 99')dnl 10000001111,10111100,{mod}{reg}{r_m}:bsf {mod}{r_m},{reg} 10100001111,10111101,{mod}{reg}{r_m}:bsr {mod}{r_m},{reg} 10200001111,11001{reg}:bswap {reg} 10300001111,10100011,{mod}{reg}{r_m}:bt {reg},{mod}{r_m} 10400001111,10111010,{mod}100{r_m},{imm8}:bt{w} {imm8},{mod}{r_m} 10500001111,10111011,{mod}{reg}{r_m}:btc {reg},{mod}{r_m} 10600001111,10111010,{mod}111{r_m},{imm8}:btc{w} {imm8},{mod}{r_m} 10700001111,10110011,{mod}{reg}{r_m}:btr {reg},{mod}{r_m} 10800001111,10111010,{mod}110{r_m},{imm8}:btr{w} {imm8},{mod}{r_m} 10900001111,10101011,{mod}{reg}{r_m}:bts {reg},{mod}{r_m} 11000001111,10111010,{mod}101{r_m},{imm8}:bts{w} {imm8},{mod}{r_m} 11111101000,{rel}:call{W} {rel} 11211111111,{mod}010{64r_m}:call{W} *{mod}{64r_m} 113ifdef(`i386', 114`10011010,{absval},{sel}:lcall {sel},{absval} 115')dnl 11611111111,{mod}011{64r_m}:lcall{W} *{mod}{64r_m} 117# SPECIAL 10011000:[{rex.w}?cltq:{dpfx}?cbtw:cwtl] 11810011000:INVALID 119# SPECIAL 10011001:[{rex.w}?cqto:{dpfx}?cltd:cwtd] 12010011001:INVALID 12111111000:clc 12211111100:cld 12311111010:cli 12400001111,00000101:syscall 12500001111,00000110:clts 12600001111,00000111:sysret 12700001111,00110100:sysenter 12800001111,00110101:sysexit 12911110101:cmc 13000001111,0100{tttn},{mod}{reg}{r_m}:cmov{tttn} {mod}{r_m},{reg} 1310011110{w},{imm}:cmp {imm}{w},{ax}{w} 1321000000{w},{mod}111{r_m},{imm}:cmp{w} {imm}{w},{mod}{r_m}{w} 13310000011,{mod}111{r_m},{imms8}:cmp{w} {imms8},{mod}{r_m} 1340011100{w},{mod}{reg}{r_m}:cmp {reg}{w},{mod}{r_m}{w} 1350011101{w},{mod}{reg}{r_m}:cmp {mod}{r_m}{w},{reg}{w} 136ifdef(`ASSEMBLER', 137`11110010,00001111,11000010,{Mod}{xmmreg}{R_m},{imm8}:cmpsd {imm8},{Mod}{R_m},{xmmreg} 13811110011,00001111,11000010,{Mod}{xmmreg}{R_m},{imm8}:cmpss {imm8},{Mod}{R_m},{xmmreg} 13901100110,00001111,11000010,{Mod}{xmmreg}{R_m},{imm8}:cmppd {imm8},{Mod}{R_m},{xmmreg} 14000001111,11000010,{Mod}{xmmreg}{R_m},{imm8}:cmpps {imm8},{Mod}{R_m},{xmmreg} 141', 142`11110010,00001111,11000010,{Mod}{xmmreg}{R_m},{imm8}:INVALID {Mod}{R_m},{xmmreg} 14311110011,00001111,11000010,{Mod}{xmmreg}{R_m},{imm8}:INVALID {Mod}{R_m},{xmmreg} 14401100110,00001111,11000010,{Mod}{xmmreg}{R_m},{imm8}:INVALID {Mod}{R_m},{xmmreg} 14500001111,11000010,{Mod}{xmmreg}{R_m},{imm8}:INVALID {Mod}{R_m},{xmmreg} 146')dnl 1471010011{w}:{RE}cmps{w} {es_di},{ds_si} 14800001111,1011000{w},{mod}{reg}{r_m}:cmpxchg {reg}{w},{mod}{r_m}{w} 149ifdef(`i386', 150`00001111,11000111,{mod}001{r_m}:cmpxchg8b {mod}{r_m} 151', 152`# SPECIAL 00001111,11000111,{mod}001{r_m}:[{rex.w}?cmpxchg16b:cmpxchg8b] {reg},{mod}{r_m} 15300001111,11000111,{mod}001{r_m}:INVALID {mod}{r_m} 154')dnl 15500001111,10100010:cpuid 15611110011,00001111,11100110,{Mod}{xmmreg}{R_m}:cvtdq2pd {Mod}{R_m},{xmmreg} 15711110010,00001111,11100110,{Mod}{xmmreg}{R_m}:cvtpd2dq {Mod}{R_m},{xmmreg} 15801100110,00001111,11100110,{Mod}{xmmreg}{R_m}:cvttpd2dq {Mod}{R_m},{xmmreg} 159ifdef(`i386', 160`00100111:daa 16100101111:das 162')dnl 1631111111{w},{mod}001{r_m}:dec{w} {mod}{r_m}{w} 164ifdef(`i386', 165`01001{reg}:dec {reg} 166')dnl 1671111011{w},{mod}110{r_m}:div{w} {mod}{r_m}{w} 16800001111,01110111:emms 16911001000,{imm16},{imm8}:enter{W} {imm16},{imm8} 17011011001,11010000:fnop 17111011001,11100000:fchs 17211011001,11100001:fabs 17311011001,11100100:ftst 17411011001,11100101:fxam 17511011001,11101000:fld1 17611011001,11101001:fldl2t 17711011001,11101010:fldl2e 17811011001,11101011:fldpi 17911011001,11101100:fldlg2 18011011001,11101101:fldln2 18111011001,11101110:fldz 18211011001,11110000:f2xm1 18311011001,11110001:fyl2x 18411011001,11110010:fptan 18511011001,11110011:fpatan 18611011001,11110100:fxtract 18711011001,11110101:fprem1 18811011001,11110110:fdecstp 18911011001,11110111:fincstp 19011011001,11111000:fprem 19111011001,11111001:fyl2xp1 19211011001,11111010:fsqrt 19311011001,11111011:fsincos 19411011001,11111100:frndint 19511011001,11111101:fscale 19611011001,11111110:fsin 19711011001,11111111:fcos 198# ORDER 19911011000,11000{freg}:fadd {freg},%st 20011011100,11000{freg}:fadd %st,{freg} 20111011{D}00,{mod}000{r_m}:fadd{D} {mod}{r_m} 202# ORDER END 203# ORDER 20411011000,11001{freg}:fmul {freg},%st 20511011100,11001{freg}:fmul %st,{freg} 20611011{D}00,{mod}001{r_m}:fmul{D} {mod}{r_m} 207# ORDER END 208# ORDER 20911011000,11100{freg}:fsub {freg},%st 21011011100,11100{freg}:fsub %st,{freg} 21111011{D}00,{mod}100{r_m}:fsub{D} {mod}{r_m} 212# ORDER END 213# ORDER 21411011000,11101{freg}:fsubr {freg},%st 21511011100,11101{freg}:fsubr %st,{freg} 21611011{D}00,{mod}101{r_m}:fsubr{D} {mod}{r_m} 217# ORDER END 218# ORDER 21911011101,11010{freg}:fst {freg} 22011011{D}01,{mod}010{r_m}:fst{D} {mod}{r_m} 221# ORDER END 222# ORDER 22311011101,11011{freg}:fstp {freg} 22411011{D}01,{mod}011{r_m}:fstp{D} {mod}{r_m} 225# ORDER END 22611011001,{mod}100{r_m}:fldenv {mod}{r_m} 22711011001,{mod}101{r_m}:fldcw {mod}{r_m} 22811011001,{mod}110{r_m}:fnstenv {mod}{r_m} 22911011001,{mod}111{r_m}:fnstcw {mod}{r_m} 23011011001,11001{freg}:fxch {freg} 231# ORDER 23211011110,11000{freg}:faddp %st,{freg} 233ifdef(`ASSEMBLER', 234`11011110,11000001:faddp 235')dnl 236# ORDER 23711011010,11000{freg}:fcmovb {freg},%st 23811011{w1}10,{mod}000{r_m}:fiadd{w1} {mod}{r_m} 239# ORDER END 240# ORDER 24111011010,11001{freg}:fcmove {freg},%st 24211011110,11001{freg}:fmulp %st,{freg} 24311011{w1}10,{mod}001{r_m}:fimul{w1} {mod}{r_m} 244# ORDER END 245# ORDER 24611011110,11100{freg}:fsubp %st,{freg} 24711011{w1}10,{mod}100{r_m}:fisub{w1} {mod}{r_m} 248# ORDER END 249# ORDER 25011011110,11101{freg}:fsubrp %st,{freg} 25111011{w1}10,{mod}101{r_m}:fisubr{w1} {mod}{r_m} 252# ORDER END 253# ORDER 25411011111,11100000:fnstsw %ax 25511011111,{mod}100{r_m}:fbld {mod}{r_m} 256# ORDER END 257# ORDER 25811011111,11110{freg}:fcomip {freg},%st 25911011111,{mod}110{r_m}:fbstp {mod}{r_m} 260# ORDER END 26111011001,11100000:fchs 262# ORDER 26310011011,11011011,11100010:fclex 26410011011,11011011,11100011:finit 26510011011:fwait 266# END ORDER 26711011011,11100010:fnclex 26811011010,11000{freg}:fcmovb {freg},%st 26911011010,11001{freg}:fcmove {freg},%st 27011011010,11010{freg}:fcmovbe {freg},%st 27111011010,11011{freg}:fcmovu {freg},%st 27211011011,11000{freg}:fcmovnb {freg},%st 27311011011,11001{freg}:fcmovne {freg},%st 27411011011,11010{freg}:fcmovnbe {freg},%st 27511011011,11011{freg}:fcmovnu {freg},%st 276# ORDER 27711011000,11010{freg}:fcom {freg} 278ifdef(`ASSEMBLER', 279`11011000,11010001:fcom 280')dnl 28111011{D}00,{mod}010{r_m}:fcom{D} {mod}{r_m} 282# END ORDER 283# ORDER 28411011000,11011{freg}:fcomp {freg} 285ifdef(`ASSEMBLER', 286`11011000,11011001:fcomp 287')dnl 28811011{D}00,{mod}011{r_m}:fcomp{D} {mod}{r_m} 289# END ORDER 29011011110,11011001:fcompp 29111011011,11110{freg}:fcomi {freg},%st 29211011111,11110{freg}:fcomip {freg},%st 29311011011,11101{freg}:fucomi {freg},%st 29411011111,11101{freg}:fucomip {freg},%st 29511011001,11111111:fcos 29611011001,11110110:fdecstp 297# ORDER 29811011000,11110{freg}:fdiv {freg},%st 29911011100,11110{freg}:fdiv %st,{freg} 30011011{D}00,{mod}110{r_m}:fdiv{D} {mod}{r_m} 301# END ORDER 30211011010,{mod}110{r_m}:fidivl {mod}{r_m} 303# ORDER 30411011110,11110{freg}:fdivp %st,{freg} 30511011110,{mod}110{r_m}:fidiv {mod}{r_m} 306# END ORDER 30711011110,11111{freg}:fdivrp %st,{freg} 308ifdef(`ASSEMBLER', 309`11011110,11111001:fdivp 310')dnl 311# ORDER 31211011000,11111{freg}:fdivr {freg},%st 31311011100,11111{freg}:fdivr %st,{freg} 31411011{D}00,{mod}111{r_m}:fdivr{D} {mod}{r_m} 315# END ORDER 31611011010,{mod}111{r_m}:fidivrl {mod}{r_m} 31711011110,{mod}111{r_m}:fidivr {mod}{r_m} 31811011110,11110{freg}:fdivrp %st,{freg} 319ifdef(`ASSEMBLER', 320`11011110,11110001:fdivrp 321')dnl 32211011101,11000{freg}:ffree {freg} 32311011010,11010{freg}:fcmovbe {freg} 32411011{w1}10,{mod}010{r_m}:ficom{w1} {mod}{r_m} 32511011010,11011{freg}:fcmovu {freg} 32611011{w1}10,{mod}011{r_m}:ficomp{w1} {mod}{r_m} 32711011111,{mod}000{r_m}:fild {mod}{r_m} 32811011011,{mod}000{r_m}:fildl {mod}{r_m} 32911011111,{mod}101{r_m}:fildll {mod}{r_m} 33011011001,11110111:fincstp 33111011011,11100011:fninit 33211011{w1}11,{mod}010{r_m}:fist{w1} {mod}{r_m} 33311011{w1}11,{mod}011{r_m}:fistp{w1} {mod}{r_m} 33411011111,{mod}111{r_m}:fistpll {mod}{r_m} 33511011{w1}11,{mod}001{r_m}:fisttp{w1} {mod}{r_m} 33611011101,{mod}001{r_m}:fisttpll {mod}{r_m} 33711011011,{mod}101{r_m}:fldt {mod}{r_m} 33811011011,{mod}111{r_m}:fstpt {mod}{r_m} 339# ORDER 34011011001,11000{freg}:fld {freg} 34111011{D}01,{mod}000{r_m}:fld{D} {mod}{r_m} 342# ORDER END 343# ORDER 34411011101,11100{freg}:fucom {freg} 34511011101,{mod}100{r_m}:frstor {mod}{r_m} 346# ORDER END 34711011101,11101{freg}:fucomp {freg} 34811011101,{mod}110{r_m}:fnsave {mod}{r_m} 34911011101,{mod}111{r_m}:fnstsw {mod}{r_m} 350# 351# 352# 35311110100:hlt 3541111011{w},{mod}111{r_m}:idiv{w} {mod}{r_m}{w} 3551111011{w},{mod}101{r_m}:imul{w} {mod}{r_m}{w} 35600001111,10101111,{mod}{reg}{r_m}:imul {mod}{r_m},{reg} 357011010{s}1,{mod}{reg}{r_m},{imm}:imul {imm}{s},{mod}{r_m},{reg} 3581110010{w},{imm8}:in {imm8},{ax}{w} 3591110110{w}:in {dx},{ax}{w} 3601111111{w},{mod}000{r_m}:inc{w} {mod}{r_m}{w} 361ifdef(`i386', 362`01000{reg}:inc {reg} 363')dnl 3640110110{w}:{R}ins{w} {dx},{es_di} 36511001101,{imm8}:int {imm8} 36611001100:int3 367ifdef(`i386', 368`11001110:into 369')dnl 37000001111,00001000:invd 371# ORDER 37200001111,00000001,11111000:swapgs 37300001111,00000001,{mod}111{r_m}:invlpg {mod}{r_m} 374# ORDER END 37511001111:iret{W1} 3760111{tttn},{disp8}:j{tttn} {disp8} 37700001111,1000{tttn},{rel}:j{tttn} {rel} 37800001111,1001{tttn},{mod}000{8r_m}:set{tttn} {mod}{8r_m} 379# SPECIAL 11100011,{disp8}:[{dpfx}?jcxz:jecxz] {disp8} 38011100011,{disp8}:INVALID {disp8} 38111101011,{disp8}:jmp {disp8} 38211101001,{rel}:jmp{W} {rel} 38311111111,{mod}100{64r_m}:jmp{W} *{mod}{64r_m} 38411101010,{absval},{sel}:ljmp {sel},{absval} 38511111111,{mod}101{64r_m}:ljmp{W} *{mod}{64r_m} 38610011111:lahf 38700001111,00000010,{mod}{reg}{16r_m}:lar {mod}{16r_m},{reg} 388ifdef(`i386', 389`11000101,{mod}{reg}{r_m}:lds {mod}{r_m},{reg} 390')dnl 39110001101,{mod}{reg}{r_m}:lea {mod}{r_m},{reg} 39211001001:leave{W} 393ifdef(`i386', 394`11000100,{mod}{reg}{r_m}:les {mod}{r_m},{reg} 395')dnl 39600001111,10110100,{mod}{reg}{r_m}:lfs {mod}{r_m},{reg} 39700001111,10110101,{mod}{reg}{r_m}:lgs {mod}{r_m},{reg} 398ifdef(`i386', 399`00001111,00000001,{mod}010{r_m}:lgdt{w0} {mod}{r_m} 40000001111,00000001,{mod}011{r_m}:lidt{w0} {mod}{r_m} 401', 402`00001111,00000001,{mod}010{r_m}:lgdt {mod}{r_m} 40300001111,00000001,{mod}011{r_m}:lidt {mod}{r_m} 404')dnl 40500001111,00000000,{mod}010{16r_m}:lldt {mod}{16r_m} 40600001111,00000001,{mod}110{16r_m}:lmsw {mod}{16r_m} 40711110000:lock 4081010110{w}:{R}lods {ds_si},{ax}{w} 40911100010,{disp8}:loop {disp8} 41011100001,{disp8}:loope {disp8} 41111100000,{disp8}:loopne {disp8} 41200001111,00000011,{mod}{reg}{16r_m}:lsl {mod}{16r_m},{reg} 41300001111,10110010,{mod}{reg}{r_m}:lss {mod}{r_m},{reg} 41400001111,00000000,{mod}011{16r_m}:ltr {mod}{16r_m} 4151000100{w},{mod}{reg}{r_m}:mov {reg}{w},{mod}{r_m}{w} 4161000101{w},{mod}{reg}{r_m}:mov {mod}{r_m}{w},{reg}{w} 4171100011{w},{mod}000{r_m},{imm}:mov{w} {imm}{w},{mod}{r_m}{w} 4181011{w}{oreg},{imm64}:mov {imm64}{w},{oreg}{w} 4191010000{w},{abs}:mov {abs},{ax}{w} 4201010001{w},{abs}:mov {ax}{w},{abs} 42100001111,00100000,11{ccc}{reg64}:mov {ccc},{reg64} 42200001111,00100010,11{ccc}{reg64}:mov {reg64},{ccc} 42300001111,00100001,11{ddd}{reg64}:mov {ddd},{reg64} 42400001111,00100011,11{ddd}{reg64}:mov {reg64},{ddd} 42510001100,{mod}{sreg3}{r_m}:mov {sreg3},{mod}{r_m} 42610001110,{mod}{sreg3}{r_m}:mov {mod}{r_m},{sreg3} 4271010010{w}:{R}movs{w} {ds_si},{es_di} 42800001111,10111110,{mod}{reg}{8r_m}:movsbl {mod}{8r_m},{reg} 42900001111,10111111,{mod}{reg}{16r_m}:movswl {mod}{16r_m},{reg} 43000001111,10110110,{mod}{reg}{8r_m}:movzbl {mod}{8r_m},{reg} 43100001111,10110111,{mod}{reg}{16r_m}:movzwl {mod}{16r_m},{reg} 4321111011{w},{mod}100{r_m}:mul{w} {mod}{r_m}{w} 4331111011{w},{mod}011{r_m}:neg{w} {mod}{r_m}{w} 43411110011,10010000:pause 435ifdef(`i386', 436`10010000:nop 437', 438`10010000:INVALID 439')dnl 440# ORDER before out 44111110011,00001111,10111000,{mod}{reg}{r_m}:popcnt {mod}{r_m},{reg} 442# END ORDER 4431111011{w},{mod}010{r_m}:not{w} {mod}{r_m}{w} 4440000100{w},{mod}{reg}{r_m}:or {reg}{w},{mod}{r_m}{w} 4450000101{w},{mod}{reg}{r_m}:or {mod}{r_m}{w},{reg}{w} 4461000000{w},{mod}001{r_m},{imm}:or{w} {imm}{w},{mod}{r_m}{w} 4471000001{w},{mod}001{r_m},{imms8}:or{w} {imms8},{mod}{r_m}{w} 4480000110{w},{imm}:or {imm}{w},{ax}{w} 4491110011{w},{imm8}:out {ax}{w},{imm8} 4501110111{w}:out {ax}{w},{dx} 4510110111{w}:{R}outs{w} {ds_si},{dx} 452ifdef(`i386', 453`10001111,{mod}000{r_m}:pop{w} {mod}{r_m} 454', 455# XXX This is not the cleanest way... 456`10001111,11000{reg64}:pop {reg64} 45710001111,{mod}000{r_m}:pop{W} {mod}{r_m} 458')dnl 45900001111,10{sreg3}001:pop{W} {sreg3} 46010011101:popf{W} 461# XXX This is not the cleanest way... 462ifdef(`i386', 463`11111111,{mod}110{r_m}:push{w} {mod}{r_m} 464', 465`11111111,11110{reg64}:push {reg64} 46611111111,{mod}110{r_m}:pushq {mod}{r_m} 467')dnl 468ifdef(`i386', 469`01010{reg}:push {reg} 47001011{reg}:pop {reg} 471', 472`01010{reg64}:push {reg64} 47301011{reg64}:pop {reg64} 474')dnl 475011010{s}0,{imm}:push{W} {imm}{s} 476000{sreg2}110:push {sreg2} 47700001111,10{sreg3}000:push{W} {sreg3} 478ifdef(`i386', 479`01100000:pusha{W} 48001100001:popa{W} 481')dnl 48210011100:pushf{W} 4831101000{w},{mod}010{r_m}:rcl{w} {mod}{r_m}{w} 4841101001{w},{mod}010{r_m}:rcl{w} %cl,{mod}{r_m}{w} 4851100000{w},{mod}010{r_m},{imm8}:rcl{w} {imm8},{mod}{r_m}{w} 4861101000{w},{mod}011{r_m}:rcr{w} {mod}{r_m}{w} 4871101001{w},{mod}011{r_m}:rcr{w} %cl,{mod}{r_m}{w} 4881100000{w},{mod}011{r_m},{imm8}:rcr{w} {imm8},{mod}{r_m}{w} 48900001111,00110010:rdmsr 49000001111,00110011:rdpmc 49100001111,00110001:rdtsc 49211000011:ret{W} 49311000010,{imm16}:ret{W} {imm16} 49411001011:lret 49511001010,{imm16}:lret {imm16} 4961101000{w},{mod}000{r_m}:rol{w} {mod}{r_m}{w} 4971101001{w},{mod}000{r_m}:rol{w} %cl,{mod}{r_m}{w} 4981100000{w},{mod}000{r_m},{imm8}:rol{w} {imm8},{mod}{r_m}{w} 4991101000{w},{mod}001{r_m}:ror{w} {mod}{r_m}{w} 5001101001{w},{mod}001{r_m}:ror{w} %cl,{mod}{r_m}{w} 5011100000{w},{mod}001{r_m},{imm8}:ror{w} {imm8},{mod}{r_m}{w} 50200001111,10101010:rsm 50310011110:sahf 5041101000{w},{mod}111{r_m}:sar{w} {mod}{r_m}{w} 5051101001{w},{mod}111{r_m}:sar{w} %cl,{mod}{r_m}{w} 5061100000{w},{mod}111{r_m},{imm8}:sar{w} {imm8},{mod}{r_m}{w} 5070001100{w},{mod}{reg}{r_m}:sbb {reg}{w},{mod}{r_m}{w} 5080001101{w},{mod}{reg}{r_m}:sbb {mod}{r_m}{w},{reg}{w} 5090001110{w},{imm}:sbb {imm}{w},{ax}{w} 5101000000{w},{mod}011{r_m},{imm}:sbb{w} {imm}{w},{mod}{r_m}{w} 5111000001{w},{mod}011{r_m},{imms8}:sbb{w} {imms8},{mod}{r_m} 5121010111{w}:{RE}scas {es_di},{ax}{w} 51300001111,1001{tttn},{mod}000{r_m}:set{tttn} {mod}{r_m} 5141101000{w},{mod}100{r_m}:shl{w} {mod}{r_m}{w} 5151101001{w},{mod}100{r_m}:shl{w} %cl,{mod}{r_m}{w} 5161100000{w},{mod}100{r_m},{imm8}:shl{w} {imm8},{mod}{r_m}{w} 5171101000{w},{mod}101{r_m}:shr{w} {mod}{r_m}{w} 51800001111,10100100,{mod}{reg}{r_m},{imm8}:shld {imm8},{reg},{mod}{r_m} 51900001111,10100101,{mod}{reg}{r_m}:shld %cl,{reg},{mod}{r_m} 5201101001{w},{mod}101{r_m}:shr{w} %cl,{mod}{r_m}{w} 5211100000{w},{mod}101{r_m},{imm8}:shr{w} {imm8},{mod}{r_m}{w} 52200001111,10101100,{mod}{reg}{r_m},{imm8}:shrd {imm8},{reg},{mod}{r_m} 52300001111,10101101,{mod}{reg}{r_m}:shrd %cl,{reg},{mod}{r_m} 524# ORDER 52500001111,00000001,11000001:vmcall 52600001111,00000001,11000010:vmlaunch 52700001111,00000001,11000011:vmresume 52800001111,00000001,11000100:vmxoff 52900001111,01111000,{mod}{reg64}{64r_m}:vmread {reg64},{mod}{64r_m} 53000001111,01111001,{mod}{reg64}{64r_m}:vmwrite {mod}{64r_m},{reg64} 531ifdef(`i386', 532`00001111,00000001,{mod}000{r_m}:sgdtl {mod}{r_m} 533', 534`00001111,00000001,{mod}000{r_m}:sgdt {mod}{r_m} 535')dnl 536# ORDER END 537# ORDER 538ifdef(`i386', 539`00001111,00000001,11001000:monitor %eax,%ecx,%edx 54000001111,00000001,11001001:mwait %eax,%ecx 541', 542`00001111,00000001,11001000:monitor %rax,%rcx,%rdx 54300001111,00000001,11001001:mwait %rax,%rcx 544')dnl 545ifdef(`i386', 546`00001111,00000001,{mod}001{r_m}:sidtl {mod}{r_m} 547', 548`00001111,00000001,{mod}001{r_m}:sidt {mod}{r_m} 549')dnl 550# ORDER END 55100001111,00000000,{mod}000{r_m}:sldt {mod}{r_m} 55200001111,00000001,{mod}100{r_m}:smsw {mod}{r_m} 55311111001:stc 55411111101:std 55511111011:sti 5561010101{w}:{R}stos {ax}{w},{es_di} 55700001111,00000000,{mod}001{r_m}:str {mod}{r_m} 5580010100{w},{mod}{reg}{r_m}:sub {reg}{w},{mod}{r_m}{w} 5590010101{w},{mod}{reg}{r_m}:sub {mod}{r_m}{w},{reg}{w} 5600010110{w},{imm}:sub {imm}{w},{ax}{w} 5611000000{w},{mod}101{r_m},{imm}:sub{w} {imm}{w},{mod}{r_m}{w} 5621000001{w},{mod}101{r_m},{imms8}:sub{w} {imms8},{mod}{r_m} 5631000010{w},{mod}{reg}{r_m}:test {reg}{w},{mod}{r_m}{w} 5641010100{w},{imm}:test {imm}{w},{ax}{w} 5651111011{w},{mod}000{r_m},{imm}:test{w} {imm}{w},{mod}{r_m}{w} 56600001111,00001011:ud2a 56700001111,00000000,{mod}100{16r_m}:verr {mod}{16r_m} 56800001111,00000000,{mod}101{16r_m}:verw {mod}{16r_m} 56900001111,00001001:wbinvd 57000001111,00001101,{mod}000{8r_m}:prefetch {mod}{8r_m} 57100001111,00001101,{mod}001{8r_m}:prefetchw {mod}{8r_m} 57200001111,00011000,{mod}000{r_m}:prefetchnta {mod}{r_m} 57300001111,00011000,{mod}001{r_m}:prefetcht0 {mod}{r_m} 57400001111,00011000,{mod}010{r_m}:prefetcht1 {mod}{r_m} 57500001111,00011000,{mod}011{r_m}:prefetcht2 {mod}{r_m} 57600001111,00011111,{mod}{reg}{r_m}:nop{w} {mod}{r_m} 57700001111,00110000:wrmsr 57800001111,1100000{w},{mod}{reg}{r_m}:xadd {reg}{w},{mod}{r_m}{w} 5791000011{w},{mod}{reg}{r_m}:xchg {reg}{w},{mod}{r_m}{w} 58010010{oreg}:xchg {ax},{oreg} 58111010111:xlat {ds_bx} 5820011000{w},{mod}{reg}{r_m}:xor {reg}{w},{mod}{r_m}{w} 5830011001{w},{mod}{reg}{r_m}:xor {mod}{r_m}{w},{reg}{w} 5840011010{w},{imm}:xor {imm}{w},{ax}{w} 5851000000{w},{mod}110{r_m},{imm}:xor{w} {imm}{w},{mod}{r_m}{w} 5861000001{w},{mod}110{r_m},{imms8}:xor{w} {imms8},{mod}{r_m} 58700001111,01110111:emms 58801100110,00001111,11011011,{Mod}{xmmreg}{R_m}:pand {Mod}{R_m},{xmmreg} 58900001111,11011011,{MOD}{mmxreg}{R_M}:pand {MOD}{R_M},{mmxreg} 59001100110,00001111,11011111,{Mod}{xmmreg}{R_m}:pandn {Mod}{R_m},{xmmreg} 59100001111,11011111,{MOD}{mmxreg}{R_M}:pandn {MOD}{R_M},{mmxreg} 59201100110,00001111,11110101,{Mod}{xmmreg}{R_m}:pmaddwd {Mod}{R_m},{xmmreg} 59300001111,11110101,{MOD}{mmxreg}{R_M}:pmaddwd {MOD}{R_M},{mmxreg} 59401100110,00001111,11101011,{Mod}{xmmreg}{R_m}:por {Mod}{R_m},{xmmreg} 59500001111,11101011,{MOD}{mmxreg}{R_M}:por {MOD}{R_M},{mmxreg} 59601100110,00001111,11101111,{Mod}{xmmreg}{R_m}:pxor {Mod}{R_m},{xmmreg} 59700001111,11101111,{MOD}{mmxreg}{R_M}:pxor {MOD}{R_M},{mmxreg} 59800001111,01010101,{Mod}{xmmreg}{R_m}:andnps {Mod}{R_m},{xmmreg} 59900001111,01010100,{Mod}{xmmreg}{R_m}:andps {Mod}{R_m},{xmmreg} 60000001111,11000010,{Mod}{xmmreg}{R_m},00000000:cmpeqps {Mod}{R_m},{xmmreg} 60100001111,11000010,{Mod}{xmmreg}{R_m},00000001:cmpltps {Mod}{R_m},{xmmreg} 60200001111,11000010,{Mod}{xmmreg}{R_m},00000010:cmpleps {Mod}{R_m},{xmmreg} 60300001111,11000010,{Mod}{xmmreg}{R_m},00000011:cmpunordps {Mod}{R_m},{xmmreg} 60400001111,11000010,{Mod}{xmmreg}{R_m},00000100:cmpneqps {Mod}{R_m},{xmmreg} 60500001111,11000010,{Mod}{xmmreg}{R_m},00000101:cmpnltps {Mod}{R_m},{xmmreg} 60600001111,11000010,{Mod}{xmmreg}{R_m},00000110:cmpnleps {Mod}{R_m},{xmmreg} 60700001111,11000010,{Mod}{xmmreg}{R_m},00000111:cmpordps {Mod}{R_m},{xmmreg} 60811110011,00001111,11000010,{Mod}{xmmreg}{R_m},00000000:cmpeqss {Mod}{R_m},{xmmreg} 60911110011,00001111,11000010,{Mod}{xmmreg}{R_m},00000001:cmpltss {Mod}{R_m},{xmmreg} 61011110011,00001111,11000010,{Mod}{xmmreg}{R_m},00000010:cmpless {Mod}{R_m},{xmmreg} 61111110011,00001111,11000010,{Mod}{xmmreg}{R_m},00000011:cmpunordss {Mod}{R_m},{xmmreg} 61211110011,00001111,11000010,{Mod}{xmmreg}{R_m},00000100:cmpneqss {Mod}{R_m},{xmmreg} 61311110011,00001111,11000010,{Mod}{xmmreg}{R_m},00000101:cmpnltss {Mod}{R_m},{xmmreg} 61411110011,00001111,11000010,{Mod}{xmmreg}{R_m},00000110:cmpnless {Mod}{R_m},{xmmreg} 61511110011,00001111,11000010,{Mod}{xmmreg}{R_m},00000111:cmpordss {Mod}{R_m},{xmmreg} 61600001111,10101110,{mod}001{r_m}:fxrstor {mod}{r_m} 61700001111,10101110,{mod}000{r_m}:fxsave {mod}{r_m} 61800001111,10101110,{mod}010{r_m}:ldmxcsr {mod}{r_m} 61900001111,10101110,{mod}011{r_m}:stmxcsr {mod}{r_m} 62011110010,00001111,00010000,{Mod}{xmmreg}{R_m}:movsd {Mod}{R_m},{xmmreg} 62111110011,00001111,00010000,{Mod}{xmmreg}{R_m}:movss {Mod}{R_m},{xmmreg} 62201100110,00001111,00010000,{Mod}{xmmreg}{R_m}:movupd {Mod}{R_m},{xmmreg} 62300001111,00010000,{Mod}{xmmreg}{R_m}:movups {Mod}{R_m},{xmmreg} 62411110010,00001111,00010001,{Mod}{xmmreg}{R_m}:movsd {xmmreg},{Mod}{R_m} 62511110011,00001111,00010001,{Mod}{xmmreg}{R_m}:movss {xmmreg},{Mod}{R_m} 62601100110,00001111,00010001,{Mod}{xmmreg}{R_m}:movupd {xmmreg},{Mod}{R_m} 62700001111,00010001,{Mod}{xmmreg}{R_m}:movups {xmmreg},{Mod}{R_m} 62811110010,00001111,00010010,{Mod}{xmmreg}{R_m}:movddup {Mod}{R_m},{xmmreg} 62911110011,00001111,00010010,{Mod}{xmmreg}{R_m}:movsldup {Mod}{R_m},{xmmreg} 63001100110,00001111,00010010,{Mod}{xmmreg}{R_m}:movlpd {Mod}{R_m},{xmmreg} 63100001111,00010010,11{xmmreg1}{xmmreg2}:movhlps {xmmreg2},{xmmreg1} 63200001111,00010010,{Mod}{xmmreg}{R_m}:movlps {Mod}{R_m},{xmmreg} 63301100110,00001111,00010011,11{xmmreg1}{xmmreg2}:movhlpd {xmmreg1},{xmmreg2} 63400001111,00010011,11{xmmreg1}{xmmreg2}:movhlps {xmmreg1},{xmmreg2} 63501100110,00001111,00010011,{Mod}{xmmreg}{R_m}:movlpd {xmmreg},{Mod}{R_m} 63600001111,00010011,{Mod}{xmmreg}{R_m}:movlps {xmmreg},{Mod}{R_m} 63701100110,00001111,00010100,{Mod}{xmmreg}{R_m}:unpcklpd {Mod}{R_m},{xmmreg} 63800001111,00010100,{Mod}{xmmreg}{R_m}:unpcklps {Mod}{R_m},{xmmreg} 63901100110,00001111,00010101,{Mod}{xmmreg}{R_m}:unpckhpd {Mod}{R_m},{xmmreg} 64000001111,00010101,{Mod}{xmmreg}{R_m}:unpckhps {Mod}{R_m},{xmmreg} 64111110011,00001111,00010110,{Mod}{xmmreg}{R_m}:movshdup {Mod}{R_m},{xmmreg} 64201100110,00001111,00010110,{Mod}{xmmreg}{R_m}:movhpd {Mod}{R_m},{xmmreg} 64300001111,00010110,11{xmmreg1}{xmmreg2}:movlhps {xmmreg2},{xmmreg1} 64400001111,00010110,{Mod}{xmmreg}{R_m}:movhps {Mod}{R_m},{xmmreg} 64501100110,00001111,00010111,11{xmmreg1}{xmmreg2}:movlhpd {xmmreg1},{xmmreg2} 64600001111,00010111,11{xmmreg1}{xmmreg2}:movlhps {xmmreg1},{xmmreg2} 64701100110,00001111,00010111,{Mod}{xmmreg}{R_m}:movhpd {xmmreg},{Mod}{R_m} 64800001111,00010111,{Mod}{xmmreg}{R_m}:movhps {xmmreg},{Mod}{R_m} 64901100110,00001111,00101000,{Mod}{xmmreg}{R_m}:movapd {Mod}{R_m},{xmmreg} 65000001111,00101000,{Mod}{xmmreg}{R_m}:movaps {Mod}{R_m},{xmmreg} 65101100110,00001111,00101001,{Mod}{xmmreg}{R_m}:movapd {xmmreg},{Mod}{R_m} 65200001111,00101001,{Mod}{xmmreg}{R_m}:movaps {xmmreg},{Mod}{R_m} 65311110010,00001111,00101010,{mod}{xmmreg}{r_m}:cvtsi2sd {mod}{r_m},{xmmreg} 65411110011,00001111,00101010,{mod}{xmmreg}{r_m}:cvtsi2ss {mod}{r_m},{xmmreg} 65501100110,00001111,00101010,{MOD}{xmmreg}{R_M}:cvtpi2pd {MOD}{R_M},{xmmreg} 65600001111,00101010,{MOD}{xmmreg}{R_M}:cvtpi2ps {MOD}{R_M},{xmmreg} 65701100110,00001111,00101011,{mod}{xmmreg}{r_m}:movntpd {xmmreg},{mod}{r_m} 65800001111,00101011,{mod}{xmmreg}{r_m}:movntps {xmmreg},{mod}{r_m} 65911110010,00001111,00101100,{Mod}{reg}{R_m}:cvttsd2si {Mod}{R_m},{reg} 66011110011,00001111,00101100,{Mod}{reg}{R_m}:cvttss2si {Mod}{R_m},{reg} 66101100110,00001111,00101100,{Mod}{mmxreg}{R_m}:cvttpd2pi {Mod}{R_m},{mmxreg} 66200001111,00101100,{Mod}{mmxreg}{R_m}:cvttps2pi {Mod}{R_m},{mmxreg} 66301100110,00001111,00101101,{Mod}{mmxreg}{R_m}:cvtpd2pi {Mod}{R_m},{mmxreg} 66411110010,00001111,00101101,{Mod}{reg}{R_m}:cvtsd2si {Mod}{R_m},{reg} 66511110011,00001111,00101101,{Mod}{reg}{R_m}:cvtss2si {Mod}{R_m},{reg} 66600001111,00101101,{Mod}{mmxreg}{R_m}:cvtps2pi {Mod}{R_m},{mmxreg} 66701100110,00001111,00101110,{Mod}{xmmreg}{R_m}:ucomisd {Mod}{R_m},{xmmreg} 66800001111,00101110,{Mod}{xmmreg}{R_m}:ucomiss {Mod}{R_m},{xmmreg} 66901100110,00001111,00101111,{Mod}{xmmreg}{R_m}:comisd {Mod}{R_m},{xmmreg} 67000001111,00101111,{Mod}{xmmreg}{R_m}:comiss {Mod}{R_m},{xmmreg} 67100001111,00110111:getsec 67201100110,00001111,01010000,11{reg}{xmmreg}:movmskpd {xmmreg},{reg} 67300001111,01010000,11{reg}{xmmreg}:movmskps {xmmreg},{reg} 67401100110,00001111,01010001,{Mod}{xmmreg}{R_m}:sqrtpd {Mod}{R_m},{xmmreg} 67511110010,00001111,01010001,{Mod}{xmmreg}{R_m}:sqrtsd {Mod}{R_m},{xmmreg} 67611110011,00001111,01010001,{Mod}{xmmreg}{R_m}:sqrtss {Mod}{R_m},{xmmreg} 67700001111,01010001,{Mod}{xmmreg}{R_m}:sqrtps {Mod}{R_m},{xmmreg} 67811110011,00001111,01010010,{Mod}{xmmreg}{R_m}:rsqrtss {Mod}{R_m},{xmmreg} 67900001111,01010010,{Mod}{xmmreg}{R_m}:rsqrtps {Mod}{R_m},{xmmreg} 68011110011,00001111,01010011,{Mod}{xmmreg}{R_m}:rcpss {Mod}{R_m},{xmmreg} 68100001111,01010011,{Mod}{xmmreg}{R_m}:rcpps {Mod}{R_m},{xmmreg} 68201100110,00001111,01010100,{Mod}{xmmreg}{R_m}:andpd {Mod}{R_m},{xmmreg} 68300001111,01010100,{Mod}{xmmreg}{R_m}:andps {Mod}{R_m},{xmmreg} 68401100110,00001111,01010101,{Mod}{xmmreg}{R_m}:andnpd {Mod}{R_m},{xmmreg} 68500001111,01010101,{Mod}{xmmreg}{R_m}:andnps {Mod}{R_m},{xmmreg} 68601100110,00001111,01010110,{Mod}{xmmreg}{R_m}:orpd {Mod}{R_m},{xmmreg} 68700001111,01010110,{Mod}{xmmreg}{R_m}:orps {Mod}{R_m},{xmmreg} 68801100110,00001111,01010111,{Mod}{xmmreg}{R_m}:xorpd {Mod}{R_m},{xmmreg} 68900001111,01010111,{Mod}{xmmreg}{R_m}:xorps {Mod}{R_m},{xmmreg} 69011110010,00001111,01011000,{Mod}{xmmreg}{R_m}:addsd {Mod}{R_m},{xmmreg} 69111110011,00001111,01011000,{Mod}{xmmreg}{R_m}:addss {Mod}{R_m},{xmmreg} 69201100110,00001111,01011000,{Mod}{xmmreg}{R_m}:addpd {Mod}{R_m},{xmmreg} 69300001111,01011000,{Mod}{xmmreg}{R_m}:addps {Mod}{R_m},{xmmreg} 69411110010,00001111,01011001,{Mod}{xmmreg}{R_m}:mulsd {Mod}{R_m},{xmmreg} 69511110011,00001111,01011001,{Mod}{xmmreg}{R_m}:mulss {Mod}{R_m},{xmmreg} 69601100110,00001111,01011001,{Mod}{xmmreg}{R_m}:mulpd {Mod}{R_m},{xmmreg} 69700001111,01011001,{Mod}{xmmreg}{R_m}:mulps {Mod}{R_m},{xmmreg} 69811110010,00001111,01011010,{Mod}{xmmreg}{R_m}:cvtsd2ss {Mod}{R_m},{xmmreg} 69911110011,00001111,01011010,{Mod}{xmmreg}{R_m}:cvtss2sd {Mod}{R_m},{xmmreg} 70001100110,00001111,01011010,{Mod}{xmmreg}{R_m}:cvtpd2ps {Mod}{R_m},{xmmreg} 70100001111,01011010,{Mod}{xmmreg}{R_m}:cvtps2pd {Mod}{R_m},{xmmreg} 70201100110,00001111,01011011,{Mod}{xmmreg}{R_m}:cvtps2dq {Mod}{R_m},{xmmreg} 70311110011,00001111,01011011,{Mod}{xmmreg}{R_m}:cvttps2dq {Mod}{R_m},{xmmreg} 70400001111,01011011,{Mod}{xmmreg}{R_m}:cvtdq2ps {Mod}{R_m},{xmmreg} 70511110010,00001111,01011100,{Mod}{xmmreg}{R_m}:subsd {Mod}{R_m},{xmmreg} 70611110011,00001111,01011100,{Mod}{xmmreg}{R_m}:subss {Mod}{R_m},{xmmreg} 70701100110,00001111,01011100,{Mod}{xmmreg}{R_m}:subpd {Mod}{R_m},{xmmreg} 70800001111,01011100,{Mod}{xmmreg}{R_m}:subps {Mod}{R_m},{xmmreg} 70911110010,00001111,01011101,{Mod}{xmmreg}{R_m}:minsd {Mod}{R_m},{xmmreg} 71011110011,00001111,01011101,{Mod}{xmmreg}{R_m}:minss {Mod}{R_m},{xmmreg} 71101100110,00001111,01011101,{Mod}{xmmreg}{R_m}:minpd {Mod}{R_m},{xmmreg} 71200001111,01011101,{Mod}{xmmreg}{R_m}:minps {Mod}{R_m},{xmmreg} 71311110010,00001111,01011110,{Mod}{xmmreg}{R_m}:divsd {Mod}{R_m},{xmmreg} 71411110011,00001111,01011110,{Mod}{xmmreg}{R_m}:divss {Mod}{R_m},{xmmreg} 71501100110,00001111,01011110,{Mod}{xmmreg}{R_m}:divpd {Mod}{R_m},{xmmreg} 71600001111,01011110,{Mod}{xmmreg}{R_m}:divps {Mod}{R_m},{xmmreg} 71711110010,00001111,01011111,{Mod}{xmmreg}{R_m}:maxsd {Mod}{R_m},{xmmreg} 71811110011,00001111,01011111,{Mod}{xmmreg}{R_m}:maxss {Mod}{R_m},{xmmreg} 71901100110,00001111,01011111,{Mod}{xmmreg}{R_m}:maxpd {Mod}{R_m},{xmmreg} 72000001111,01011111,{Mod}{xmmreg}{R_m}:maxps {Mod}{R_m},{xmmreg} 72101100110,00001111,01100000,{Mod}{xmmreg}{R_m}:punpcklbw {Mod}{R_m},{xmmreg} 72200001111,01100000,{MOD}{mmxreg}{R_M}:punpcklbw {MOD}{R_M},{mmxreg} 72301100110,00001111,01100001,{Mod}{xmmreg}{R_m}:punpcklwd {Mod}{R_m},{xmmreg} 72400001111,01100001,{MOD}{mmxreg}{R_M}:punpcklwd {MOD}{R_M},{mmxreg} 72501100110,00001111,01100010,{Mod}{xmmreg}{R_m}:punpckldq {Mod}{R_m},{xmmreg} 72600001111,01100010,{MOD}{mmxreg}{R_M}:punpckldq {MOD}{R_M},{mmxreg} 72701100110,00001111,01100011,{Mod}{xmmreg}{R_m}:packsswb {Mod}{R_m},{xmmreg} 72800001111,01100011,{MOD}{mmxreg}{R_M}:packsswb {MOD}{R_M},{mmxreg} 72901100110,00001111,01100100,{Mod}{xmmreg}{R_m}:pcmpgtb {Mod}{R_m},{xmmreg} 73000001111,01100100,{MOD}{mmxreg}{R_M}:pcmpgtb {MOD}{R_M},{mmxreg} 73101100110,00001111,01100101,{Mod}{xmmreg}{R_m}:pcmpgtw {Mod}{R_m},{xmmreg} 73200001111,01100101,{MOD}{mmxreg}{R_M}:pcmpgtw {MOD}{R_M},{mmxreg} 73301100110,00001111,01100110,{Mod}{xmmreg}{R_m}:pcmpgtd {Mod}{R_m},{xmmreg} 73400001111,01100110,{MOD}{mmxreg}{R_M}:pcmpgtd {MOD}{R_M},{mmxreg} 73501100110,00001111,01100111,{Mod}{xmmreg}{R_m}:packuswb {Mod}{R_m},{xmmreg} 73600001111,01100111,{MOD}{mmxreg}{R_M}:packuswb {MOD}{R_M},{mmxreg} 73701100110,00001111,01101000,{Mod}{xmmreg}{R_m}:punpckhbw {Mod}{R_m},{xmmreg} 73800001111,01101000,{MOD}{mmxreg}{R_M}:punpckhbw {MOD}{R_M},{mmxreg} 73901100110,00001111,01101001,{Mod}{xmmreg}{R_m}:punpckhwd {Mod}{R_m},{xmmreg} 74000001111,01101001,{MOD}{mmxreg}{R_M}:punpckhwd {MOD}{R_M},{mmxreg} 74101100110,00001111,01101010,{Mod}{xmmreg}{R_m}:punpckhdq {Mod}{R_m},{xmmreg} 74200001111,01101010,{MOD}{mmxreg}{R_M}:punpckhdq {MOD}{R_M},{mmxreg} 74301100110,00001111,01101011,{Mod}{xmmreg}{R_m}:packssdw {Mod}{R_m},{xmmreg} 74400001111,01101011,{MOD}{mmxreg}{R_M}:packssdw {MOD}{R_M},{mmxreg} 74501100110,00001111,01101100,{Mod}{xmmreg}{R_m}:punpcklqdq {Mod}{R_m},{xmmreg} 74601100110,00001111,01101101,{Mod}{xmmreg}{R_m}:punpckhqdq {Mod}{R_m},{xmmreg} 74701100110,00001111,01101110,{mod}{xmmreg}{r_m}:movd {mod}{r_m},{xmmreg} 74800001111,01101110,{mod}{mmxreg}{r_m}:movd {mod}{r_m},{mmxreg} 74901100110,00001111,01101111,{Mod}{xmmreg}{R_m}:movdqa {Mod}{R_m},{xmmreg} 75011110011,00001111,01101111,{Mod}{xmmreg}{R_m}:movdqu {Mod}{R_m},{xmmreg} 75100001111,01101111,{MOD}{mmxreg}{R_M}:movq {MOD}{R_M},{mmxreg} 75201100110,00001111,01110000,{Mod}{xmmreg}{R_m},{imm8}:pshufd {imm8},{Mod}{R_m},{xmmreg} 75311110010,00001111,01110000,{Mod}{xmmreg}{R_m},{imm8}:pshuflw {imm8},{Mod}{R_m},{xmmreg} 75411110011,00001111,01110000,{Mod}{xmmreg}{R_m},{imm8}:pshufhw {imm8},{Mod}{R_m},{xmmreg} 75500001111,01110000,{MOD}{mmxreg}{R_M},{imm8}:pshufw {imm8},{MOD}{R_M},{mmxreg} 75601100110,00001111,01110100,{Mod}{xmmreg}{R_m}:pcmpeqb {Mod}{R_m},{xmmreg} 75700001111,01110100,{MOD}{mmxreg}{R_M}:pcmpeqb {MOD}{R_M},{mmxreg} 75801100110,00001111,01110101,{Mod}{xmmreg}{R_m}:pcmpeqw {Mod}{R_m},{xmmreg} 75900001111,01110101,{MOD}{mmxreg}{R_M}:pcmpeqw {MOD}{R_M},{mmxreg} 76001100110,00001111,01110110,{Mod}{xmmreg}{R_m}:pcmpeqd {Mod}{R_m},{xmmreg} 76100001111,01110110,{MOD}{mmxreg}{R_M}:pcmpeqd {MOD}{R_M},{mmxreg} 76201100110,00001111,01111100,{Mod}{xmmreg}{R_m}:haddpd {Mod}{R_m},{xmmreg} 76311110010,00001111,01111100,{Mod}{xmmreg}{R_m}:haddps {Mod}{R_m},{xmmreg} 76401100110,00001111,01111101,{Mod}{xmmreg}{R_m}:hsubpd {Mod}{R_m},{xmmreg} 76511110010,00001111,01111101,{Mod}{xmmreg}{R_m}:hsubps {Mod}{R_m},{xmmreg} 76601100110,00001111,01111110,{mod}{xmmreg}{r_m}:movd {xmmreg},{mod}{r_m} 76711110011,00001111,01111110,{Mod}{xmmreg}{R_m}:movq {Mod}{R_m},{xmmreg} 76800001111,01111110,{mod}{mmxreg}{r_m}:movd {mmxreg},{mod}{r_m} 76901100110,00001111,01111111,{Mod}{xmmreg}{R_m}:movdqa {xmmreg},{Mod}{R_m} 77011110011,00001111,01111111,{Mod}{xmmreg}{R_m}:movdqu {xmmreg},{Mod}{R_m} 77100001111,01111111,{MOD}{mmxreg}{R_M}:movq {mmxreg},{MOD}{R_M} 77200001111,11000011,{mod}{reg}{r_m}:movnti {reg},{mod}{r_m} 77301100110,00001111,11000100,{mod}{xmmreg}{r_m},{imm8}:pinsrw {imm8},{mod}{r_m},{xmmreg} 77400001111,11000100,{mod}{mmxreg}{r_m},{imm8}:pinsrw {imm8},{mod}{r_m},{mmxreg} 77501100110,00001111,11000101,11{reg}{xmmreg},{imm8}:pextrw {imm8},{xmmreg},{reg} 77600001111,11000101,11{reg}{mmxreg},{imm8}:pextrw {imm8},{mmxreg},{reg} 77701100110,00001111,11000110,{Mod}{xmmreg}{R_m},{imm8}:shufpd {imm8},{Mod}{R_m},{xmmreg} 77800001111,11000110,{Mod}{xmmreg}{R_m},{imm8}:shufps {imm8},{Mod}{R_m},{xmmreg} 77901100110,00001111,11010001,{Mod}{xmmreg}{R_m}:psrlw {Mod}{R_m},{xmmreg} 78000001111,11010001,{MOD}{mmxreg}{R_M}:psrlw {MOD}{R_M},{mmxreg} 78101100110,00001111,11010010,{Mod}{xmmreg}{R_m}:psrld {Mod}{R_m},{xmmreg} 78200001111,11010010,{MOD}{mmxreg}{R_M}:psrld {MOD}{R_M},{mmxreg} 78301100110,00001111,11010011,{Mod}{xmmreg}{R_m}:psrlq {Mod}{R_m},{xmmreg} 78400001111,11010011,{MOD}{mmxreg}{R_M}:psrlq {MOD}{R_M},{mmxreg} 78501100110,00001111,11010100,{Mod}{xmmreg}{R_m}:paddq {Mod}{R_m},{xmmreg} 78600001111,11010100,{MOD}{mmxreg}{R_M}:paddq {MOD}{R_M},{mmxreg} 78701100110,00001111,11010101,{Mod}{xmmreg}{R_m}:pmullw {Mod}{R_m},{xmmreg} 78800001111,11010101,{MOD}{mmxreg}{R_M}:pmullw {MOD}{R_M},{mmxreg} 78901100110,00001111,11010110,{Mod}{xmmreg}{R_m}:movq {xmmreg},{Mod}{R_m} 79011110010,00001111,11010110,11{mmxreg}{xmmreg}:movdq2q {xmmreg},{mmxreg} 79111110011,00001111,11010110,11{xmmreg}{mmxreg}:movq2dq {mmxreg},{xmmreg} 79201100110,00001111,11010111,11{reg}{xmmreg}:pmovmskb {xmmreg},{reg} 79300001111,11010111,11{reg}{mmxreg}:pmovmskb {mmxreg},{reg} 79401100110,00001111,11011000,{Mod}{xmmreg}{R_m}:psubusb {Mod}{R_m},{xmmreg} 79500001111,11011000,{MOD}{mmxreg}{R_M}:psubusb {MOD}{R_M},{mmxreg} 79601100110,00001111,11011001,{Mod}{xmmreg}{R_m}:psubusw {Mod}{R_m},{xmmreg} 79700001111,11011001,{MOD}{mmxreg}{R_M}:psubusw {MOD}{R_M},{mmxreg} 79801100110,00001111,11011010,{Mod}{xmmreg}{R_m}:pminub {Mod}{R_m},{xmmreg} 79900001111,11011010,{MOD}{mmxreg}{R_M}:pminub {MOD}{R_M},{mmxreg} 80001100110,00001111,11011100,{Mod}{xmmreg}{R_m}:paddusb {Mod}{R_m},{xmmreg} 80100001111,11011100,{MOD}{mmxreg}{R_M}:paddusb {MOD}{R_M},{mmxreg} 80201100110,00001111,11011101,{Mod}{xmmreg}{R_m}:paddusw {Mod}{R_m},{xmmreg} 80300001111,11011101,{MOD}{mmxreg}{R_M}:paddusw {MOD}{R_M},{mmxreg} 80401100110,00001111,11011110,{Mod}{xmmreg}{R_m}:pmaxub {Mod}{R_m},{xmmreg} 80500001111,11011110,{MOD}{mmxreg}{R_M}:pmaxub {MOD}{R_M},{mmxreg} 80601100110,00001111,11100000,{Mod}{xmmreg}{R_m}:pavgb {Mod}{R_m},{xmmreg} 80700001111,11100000,{MOD}{mmxreg}{R_M}:pavgb {MOD}{R_M},{mmxreg} 80801100110,00001111,11100001,{Mod}{xmmreg}{R_m}:psraw {Mod}{R_m},{xmmreg} 80900001111,11100001,{MOD}{mmxreg}{R_M}:psraw {MOD}{R_M},{mmxreg} 81001100110,00001111,11100010,{Mod}{xmmreg}{R_m}:psrad {Mod}{R_m},{xmmreg} 81100001111,11100010,{MOD}{mmxreg}{R_M}:psrad {MOD}{R_M},{mmxreg} 81201100110,00001111,11100011,{Mod}{xmmreg}{R_m}:pavgw {Mod}{R_m},{xmmreg} 81300001111,11100011,{MOD}{mmxreg}{R_M}:pavgw {MOD}{R_M},{mmxreg} 81401100110,00001111,11100100,{Mod}{xmmreg}{R_m}:pmulhuw {Mod}{R_m},{xmmreg} 81500001111,11100100,{MOD}{mmxreg}{R_M}:pmulhuw {MOD}{R_M},{mmxreg} 81601100110,00001111,11100101,{Mod}{xmmreg}{R_m}:pmulhw {Mod}{R_m},{xmmreg} 81700001111,11100101,{MOD}{mmxreg}{R_M}:pmulhw {MOD}{R_M},{mmxreg} 81801100110,00001111,11100111,{Mod}{xmmreg}{R_m}:movntdq {xmmreg},{Mod}{R_m} 81900001111,11100111,{MOD}{mmxreg}{R_M}:movntq {mmxreg},{MOD}{R_M} 82001100110,00001111,11101000,{Mod}{xmmreg}{R_m}:psubsb {Mod}{R_m},{xmmreg} 82100001111,11101000,{MOD}{mmxreg}{R_M}:psubsb {MOD}{R_M},{mmxreg} 82201100110,00001111,11101001,{Mod}{xmmreg}{R_m}:psubsw {Mod}{R_m},{xmmreg} 82300001111,11101001,{MOD}{mmxreg}{R_M}:psubsw {MOD}{R_M},{mmxreg} 82401100110,00001111,11101010,{Mod}{xmmreg}{R_m}:pminsw {Mod}{R_m},{xmmreg} 82500001111,11101010,{MOD}{mmxreg}{R_M}:pminsw {MOD}{R_M},{mmxreg} 82601100110,00001111,11101100,{Mod}{xmmreg}{R_m}:paddsb {Mod}{R_m},{xmmreg} 82700001111,11101100,{MOD}{mmxreg}{R_M}:paddsb {MOD}{R_M},{mmxreg} 82801100110,00001111,11101101,{Mod}{xmmreg}{R_m}:paddsw {Mod}{R_m},{xmmreg} 82900001111,11101101,{MOD}{mmxreg}{R_M}:paddsw {MOD}{R_M},{mmxreg} 83001100110,00001111,11101110,{Mod}{xmmreg}{R_m}:pmaxsw {Mod}{R_m},{xmmreg} 83100001111,11101110,{MOD}{mmxreg}{R_M}:pmaxsw {MOD}{R_M},{mmxreg} 83211110010,00001111,11110000,{mod}{xmmreg}{r_m}:lddqu {mod}{r_m},{xmmreg} 83301100110,00001111,11110001,{Mod}{xmmreg}{R_m}:psllw {Mod}{R_m},{xmmreg} 83400001111,11110001,{MOD}{mmxreg}{R_M}:psllw {MOD}{R_M},{mmxreg} 83501100110,00001111,11110010,{Mod}{xmmreg}{R_m}:pslld {Mod}{R_m},{xmmreg} 83600001111,11110010,{MOD}{mmxreg}{R_M}:pslld {MOD}{R_M},{mmxreg} 83701100110,00001111,11110011,{Mod}{xmmreg}{R_m}:psllq {Mod}{R_m},{xmmreg} 83800001111,11110011,{MOD}{mmxreg}{R_M}:psllq {MOD}{R_M},{mmxreg} 83901100110,00001111,11110100,{Mod}{xmmreg}{R_m}:pmuludq {Mod}{R_m},{xmmreg} 84000001111,11110100,{MOD}{mmxreg}{R_M}:pmuludq {MOD}{R_M},{mmxreg} 84101100110,00001111,11110110,{Mod}{xmmreg}{R_m}:psadbw {Mod}{R_m},{xmmreg} 84200001111,11110110,{MOD}{mmxreg}{R_M}:psadbw {MOD}{R_M},{mmxreg} 84301100110,00001111,11110111,11{xmmreg1}{xmmreg2}:maskmovdqu {xmmreg2},{xmmreg1} 84400001111,11110111,11{mmxreg1}{mmxreg2}:maskmovq {mmxreg2},{mmxreg1} 84501100110,00001111,11111000,{Mod}{xmmreg}{R_m}:psubb {Mod}{R_m},{xmmreg} 84600001111,11111000,{MOD}{mmxreg}{R_M}:psubb {MOD}{R_M},{mmxreg} 84701100110,00001111,11111001,{Mod}{xmmreg}{R_m}:psubw {Mod}{R_m},{xmmreg} 84800001111,11111001,{MOD}{mmxreg}{R_M}:psubw {MOD}{R_M},{mmxreg} 84901100110,00001111,11111010,{Mod}{xmmreg}{R_m}:psubd {Mod}{R_m},{xmmreg} 85000001111,11111010,{MOD}{mmxreg}{R_M}:psubd {MOD}{R_M},{mmxreg} 85101100110,00001111,11111011,{Mod}{xmmreg}{R_m}:psubq {Mod}{R_m},{xmmreg} 85200001111,11111011,{MOD}{mmxreg}{R_M}:psubq {MOD}{R_M},{mmxreg} 85301100110,00001111,11111100,{Mod}{xmmreg}{R_m}:paddb {Mod}{R_m},{xmmreg} 85400001111,11111100,{MOD}{mmxreg}{R_M}:paddb {MOD}{R_M},{mmxreg} 85501100110,00001111,11111101,{Mod}{xmmreg}{R_m}:paddw {Mod}{R_m},{xmmreg} 85600001111,11111101,{MOD}{mmxreg}{R_M}:paddw {MOD}{R_M},{mmxreg} 85701100110,00001111,11111110,{Mod}{xmmreg}{R_m}:paddd {Mod}{R_m},{xmmreg} 85800001111,11111110,{MOD}{mmxreg}{R_M}:paddd {MOD}{R_M},{mmxreg} 85901100110,00001111,00111000,00000000,{Mod}{xmmreg}{R_m}:pshufb {Mod}{R_m},{xmmreg} 86000001111,00111000,00000000,{MOD}{mmxreg}{R_M}:pshufb {MOD}{R_M},{mmxreg} 86101100110,00001111,00111000,00000001,{Mod}{xmmreg}{R_m}:phaddw {Mod}{R_m},{xmmreg} 86200001111,00111000,00000001,{MOD}{mmxreg}{R_M}:phaddw {MOD}{R_M},{mmxreg} 86301100110,00001111,00111000,00000010,{Mod}{xmmreg}{R_m}:phaddd {Mod}{R_m},{xmmreg} 86400001111,00111000,00000010,{MOD}{mmxreg}{R_M}:phaddd {MOD}{R_M},{mmxreg} 86501100110,00001111,00111000,00000011,{Mod}{xmmreg}{R_m}:phaddsw {Mod}{R_m},{xmmreg} 86600001111,00111000,00000011,{MOD}{mmxreg}{R_M}:phaddsw {MOD}{R_M},{mmxreg} 86701100110,00001111,00111000,00000100,{Mod}{xmmreg}{R_m}:pmaddubsw {Mod}{R_m},{xmmreg} 86800001111,00111000,00000100,{MOD}{mmxreg}{R_M}:pmaddubsw {MOD}{R_M},{mmxreg} 86901100110,00001111,00111000,00000101,{Mod}{xmmreg}{R_m}:phsubw {Mod}{R_m},{xmmreg} 87000001111,00111000,00000101,{MOD}{mmxreg}{R_M}:phsubw {MOD}{R_M},{mmxreg} 87101100110,00001111,00111000,00000110,{Mod}{xmmreg}{R_m}:phsubd {Mod}{R_m},{xmmreg} 87200001111,00111000,00000110,{MOD}{mmxreg}{R_M}:phsubd {MOD}{R_M},{mmxreg} 87301100110,00001111,00111000,00000111,{Mod}{xmmreg}{R_m}:phsubsw {Mod}{R_m},{xmmreg} 87400001111,00111000,00000111,{MOD}{mmxreg}{R_M}:phsubsw {MOD}{R_M},{mmxreg} 87501100110,00001111,00111000,00001000,{Mod}{xmmreg}{R_m}:psignb {Mod}{R_m},{xmmreg} 87600001111,00111000,00001000,{MOD}{mmxreg}{R_M}:psignb {MOD}{R_M},{mmxreg} 87701100110,00001111,00111000,00001001,{Mod}{xmmreg}{R_m}:psignw {Mod}{R_m},{xmmreg} 87800001111,00111000,00001001,{MOD}{mmxreg}{R_M}:psignw {MOD}{R_M},{mmxreg} 87901100110,00001111,00111000,00001010,{Mod}{xmmreg}{R_m}:psignd {Mod}{R_m},{xmmreg} 88000001111,00111000,00001010,{MOD}{mmxreg}{R_M}:psignd {MOD}{R_M},{mmxreg} 88101100110,00001111,00111000,00001011,{Mod}{xmmreg}{R_m}:pmulhrsw {Mod}{R_m},{xmmreg} 88200001111,00111000,00001011,{MOD}{mmxreg}{R_M}:pmulhrsw {MOD}{R_M},{mmxreg} 88301100110,00001111,00111000,00011100,{Mod}{xmmreg}{R_m}:pabsb {Mod}{R_m},{xmmreg} 88400001111,00111000,00011100,{MOD}{mmxreg}{R_M}:pabsb {MOD}{R_M},{mmxreg} 88501100110,00001111,00111000,00011101,{Mod}{xmmreg}{R_m}:pabsw {Mod}{R_m},{xmmreg} 88600001111,00111000,00011101,{MOD}{mmxreg}{R_M}:pabsw {MOD}{R_M},{mmxreg} 88701100110,00001111,00111000,00011110,{Mod}{xmmreg}{R_m}:pabsd {Mod}{R_m},{xmmreg} 88800001111,00111000,00011110,{MOD}{mmxreg}{R_M}:pabsd {MOD}{R_M},{mmxreg} 88901100110,00001111,00111010,00001111,{Mod}{xmmreg}{R_m},{imm8}:palignr {imm8},{Mod}{R_m},{xmmreg} 89000001111,00111010,00001111,{MOD}{mmxreg}{R_M},{imm8}:palignr {imm8},{MOD}{R_M},{mmxreg} 89101100110,00001111,11000111,{mod}110{r_m}:vmclear {mod}{r_m} 89211110011,00001111,11000111,{mod}110{r_m}:vmxon {mod}{r_m} 89300001111,11000111,{mod}110{r_m}:vmptrld {mod}{r_m} 89400001111,11000111,{mod}111{r_m}:vmptrst {mod}{r_m} 89501100110,00001111,01110001,11010{xmmreg},{imm8}:psrlw {imm8},{xmmreg} 89600001111,01110001,11010{mmxreg},{imm8}:psrlw {imm8},{mmxreg} 89701100110,00001111,01110001,11100{xmmreg},{imm8}:psraw {imm8},{xmmreg} 89800001111,01110001,11100{mmxreg},{imm8}:psraw {imm8},{mmxreg} 89901100110,00001111,01110001,11110{xmmreg},{imm8}:psllw {imm8},{xmmreg} 90000001111,01110001,11110{mmxreg},{imm8}:psllw {imm8},{mmxreg} 90101100110,00001111,01110010,11010{xmmreg},{imm8}:psrld {imm8},{xmmreg} 90200001111,01110010,11010{mmxreg},{imm8}:psrld {imm8},{mmxreg} 90301100110,00001111,01110010,11100{xmmreg},{imm8}:psrad {imm8},{xmmreg} 90400001111,01110010,11100{mmxreg},{imm8}:psrad {imm8},{mmxreg} 90501100110,00001111,01110010,11110{xmmreg},{imm8}:pslld {imm8},{xmmreg} 90600001111,01110010,11110{mmxreg},{imm8}:pslld {imm8},{mmxreg} 90701100110,00001111,01110011,11010{xmmreg},{imm8}:psrlq {imm8},{xmmreg} 90800001111,01110011,11010{mmxreg},{imm8}:psrlq {imm8},{mmxreg} 90901100110,00001111,01110011,11011{xmmreg},{imm8}:psrldq {imm8},{xmmreg} 91001100110,00001111,01110011,11110{xmmreg},{imm8}:psllq {imm8},{xmmreg} 91100001111,01110011,11110{mmxreg},{imm8}:psllq {imm8},{mmxreg} 91201100110,00001111,01110011,11111{xmmreg},{imm8}:pslldq {imm8},{xmmreg} 91300001111,10101110,11101000:lfence 91400001111,10101110,11110000:mfence 91500001111,10101110,11111000:sfence 91600001111,10101110,{mod}111{r_m}:clflush {mod}{r_m} 91700001111,00001111,{MOD}{mmxreg}{R_M}:INVALID {MOD}{R_M},{mmxreg} 91801100110,00001111,00111010,00001100,{Mod}{xmmreg}{R_m},{imm8}:blendps {imm8},{Mod}{R_m},{xmmreg} 91901100110,00001111,00111010,00001101,{Mod}{xmmreg}{R_m},{imm8}:blendpd {imm8},{Mod}{R_m},{xmmreg} 92001100110,00001111,00111000,00010100,{Mod}{xmmreg}{R_m}:blendvps %xmm0,{Mod}{R_m},{xmmreg} 92101100110,00001111,00111000,00010101,{Mod}{xmmreg}{R_m}:blendvpd %xmm0,{Mod}{R_m},{xmmreg} 92201100110,00001111,00111010,01000000,{Mod}{xmmreg}{R_m},{imm8}:dpps {imm8},{Mod}{R_m},{xmmreg} 92301100110,00001111,00111010,01000001,{Mod}{xmmreg}{R_m},{imm8}:dppd {imm8},{Mod}{R_m},{xmmreg} 92401100110,00001111,00111010,00100001,{Mod}{xmmreg}{R_m},{imm8}:insertps {imm8},{Mod}{R_m},{xmmreg} 925# Mod == 11 is not valid 92601100110,00001111,00111000,00101010,{Mod}{xmmreg}{R_m}:movntdqa {Mod}{R_m},{xmmreg} 92701100110,00001111,00111010,01000010,{Mod}{xmmreg}{R_m},{imm8}:mpsadbw {imm8},{Mod}{R_m},{xmmreg} 92801100110,00001111,00111000,00101011,{Mod}{xmmreg}{R_m}:packusdw {Mod}{R_m},{xmmreg} 92901100110,00001111,00111000,00010000,{Mod}{xmmreg}{R_m}:pblendvb %xmm0,{Mod}{R_m},{xmmreg} 93001100110,00001111,00111010,00001110,{Mod}{xmmreg}{R_m},{imm8}:pblendw {imm8},{Mod}{R_m},{xmmreg} 93101100110,00001111,00111000,00101001,{Mod}{xmmreg}{R_m}:pcmpeqq {Mod}{R_m},{xmmreg} 93201100110,00001111,00111010,01100001,{Mod}{xmmreg}{R_m},{imm8}:pcmpestri {imm8},{Mod}{R_m},{xmmreg} 93301100110,00001111,00111010,01100000,{Mod}{xmmreg}{R_m},{imm8}:pcmpestrm {imm8},{Mod}{R_m},{xmmreg} 93401100110,00001111,00111010,01100011,{Mod}{xmmreg}{R_m},{imm8}:pcmpistri {imm8},{Mod}{R_m},{xmmreg} 93501100110,00001111,00111010,01100010,{Mod}{xmmreg}{R_m},{imm8}:pcmpistrm {imm8},{Mod}{R_m},{xmmreg} 93601100110,00001111,00111000,00110111,{Mod}{xmmreg}{R_m}:pcmpgtq {Mod}{R_m},{xmmreg} 93701100110,00001111,00111000,01000001,{Mod}{xmmreg}{R_m}:phminposuw {Mod}{R_m},{xmmreg} 93801100110,00001111,00111010,00100000,{mod}{xmmreg}{r_m},{imm8}:pinsrb {imm8},{mod}{r_m},{xmmreg} 93901100110,00001111,00111010,00100010,{mod}{xmmreg}{r_m},{imm8}:pinsrd {imm8},{mod}{r_m},{xmmreg} 94001100110,00001111,00111000,00111100,{Mod}{xmmreg}{R_m}:pmaxsb {Mod}{R_m},{xmmreg} 94101100110,00001111,00111000,00111101,{Mod}{xmmreg}{R_m}:pmaxsd {Mod}{R_m},{xmmreg} 94201100110,00001111,00111000,00111111,{Mod}{xmmreg}{R_m}:pmaxud {Mod}{R_m},{xmmreg} 94301100110,00001111,00111000,00111110,{Mod}{xmmreg}{R_m}:pmaxuw {Mod}{R_m},{xmmreg} 94401100110,00001111,00111000,00111000,{Mod}{xmmreg}{R_m}:pminsb {Mod}{R_m},{xmmreg} 94501100110,00001111,00111000,00111001,{Mod}{xmmreg}{R_m}:pminsd {Mod}{R_m},{xmmreg} 94601100110,00001111,00111000,00111011,{Mod}{xmmreg}{R_m}:pminud {Mod}{R_m},{xmmreg} 94701100110,00001111,00111000,00111010,{Mod}{xmmreg}{R_m}:pminuw {Mod}{R_m},{xmmreg} 94801100110,00001111,00111000,00100000,{Mod}{xmmreg}{R_m}:pmovsxbw {Mod}{R_m},{xmmreg} 94901100110,00001111,00111000,00100001,{Mod}{xmmreg}{R_m}:pmovsxbd {Mod}{R_m},{xmmreg} 95001100110,00001111,00111000,00100010,{Mod}{xmmreg}{R_m}:pmovsxbq {Mod}{R_m},{xmmreg} 95101100110,00001111,00111000,00100011,{Mod}{xmmreg}{R_m}:pmovsxwd {Mod}{R_m},{xmmreg} 95201100110,00001111,00111000,00100100,{Mod}{xmmreg}{R_m}:pmovsxwq {Mod}{R_m},{xmmreg} 95301100110,00001111,00111000,00100101,{Mod}{xmmreg}{R_m}:pmovsxdq {Mod}{R_m},{xmmreg} 95401100110,00001111,00111000,00110000,{Mod}{xmmreg}{R_m}:pmovzxbw {Mod}{R_m},{xmmreg} 95501100110,00001111,00111000,00110001,{Mod}{xmmreg}{R_m}:pmovzxbd {Mod}{R_m},{xmmreg} 95601100110,00001111,00111000,00110010,{Mod}{xmmreg}{R_m}:pmovzxbq {Mod}{R_m},{xmmreg} 95701100110,00001111,00111000,00110011,{Mod}{xmmreg}{R_m}:pmovzxwd {Mod}{R_m},{xmmreg} 95801100110,00001111,00111000,00110100,{Mod}{xmmreg}{R_m}:pmovzxwq {Mod}{R_m},{xmmreg} 95901100110,00001111,00111000,00110101,{Mod}{xmmreg}{R_m}:pmovzxdq {Mod}{R_m},{xmmreg} 96001100110,00001111,00111000,00101000,{Mod}{xmmreg}{R_m}:pmuldq {Mod}{R_m},{xmmreg} 96101100110,00001111,00111000,01000000,{Mod}{xmmreg}{R_m}:pmulld {Mod}{R_m},{xmmreg} 96201100110,00001111,00111000,00010111,{Mod}{xmmreg}{R_m}:ptest {Mod}{R_m},{xmmreg} 96301100110,00001111,00111010,00001000,{Mod}{xmmreg}{R_m},{imm8}:roundps {imm8},{Mod}{R_m},{xmmreg} 96401100110,00001111,00111010,00001001,{Mod}{xmmreg}{R_m},{imm8}:roundpd {imm8},{Mod}{R_m},{xmmreg} 96501100110,00001111,00111010,00001010,{Mod}{xmmreg}{R_m},{imm8}:roundss {imm8},{Mod}{R_m},{xmmreg} 96601100110,00001111,00111010,00001011,{Mod}{xmmreg}{R_m},{imm8}:roundsd {imm8},{Mod}{R_m},{xmmreg} 967# ORDER: 968dnl Many previous entries depend on this being last. 969000{sreg2}111:pop {sreg2} 970# ORDER END: 971