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1 //===-- ARMFeatures.h - Checks for ARM instruction features -----*- C++ -*-===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains the code shared between ARM CodeGen and ARM MC
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #ifndef LLVM_LIB_TARGET_ARM_ARMFEATURES_H
15 #define LLVM_LIB_TARGET_ARM_ARMFEATURES_H
16 
17 #include "MCTargetDesc/ARMMCTargetDesc.h"
18 
19 namespace llvm {
20 
21 template<typename InstrType> // could be MachineInstr or MCInst
22 bool IsCPSRDead(InstrType *Instr);
23 
24 template<typename InstrType> // could be MachineInstr or MCInst
isV8EligibleForIT(InstrType * Instr)25 inline bool isV8EligibleForIT(InstrType *Instr) {
26   switch (Instr->getOpcode()) {
27   default:
28     return false;
29   case ARM::tADC:
30   case ARM::tADDi3:
31   case ARM::tADDi8:
32   case ARM::tADDrr:
33   case ARM::tAND:
34   case ARM::tASRri:
35   case ARM::tASRrr:
36   case ARM::tBIC:
37   case ARM::tEOR:
38   case ARM::tLSLri:
39   case ARM::tLSLrr:
40   case ARM::tLSRri:
41   case ARM::tLSRrr:
42   case ARM::tMOVi8:
43   case ARM::tMUL:
44   case ARM::tMVN:
45   case ARM::tORR:
46   case ARM::tROR:
47   case ARM::tRSB:
48   case ARM::tSBC:
49   case ARM::tSUBi3:
50   case ARM::tSUBi8:
51   case ARM::tSUBrr:
52     // Outside of an IT block, these set CPSR.
53     return IsCPSRDead(Instr);
54   case ARM::tADDrSPi:
55   case ARM::tCMNz:
56   case ARM::tCMPi8:
57   case ARM::tCMPr:
58   case ARM::tLDRBi:
59   case ARM::tLDRBr:
60   case ARM::tLDRHi:
61   case ARM::tLDRHr:
62   case ARM::tLDRSB:
63   case ARM::tLDRSH:
64   case ARM::tLDRi:
65   case ARM::tLDRr:
66   case ARM::tLDRspi:
67   case ARM::tSTRBi:
68   case ARM::tSTRBr:
69   case ARM::tSTRHi:
70   case ARM::tSTRHr:
71   case ARM::tSTRi:
72   case ARM::tSTRr:
73   case ARM::tSTRspi:
74   case ARM::tTST:
75     return true;
76 // there are some "conditionally deprecated" opcodes
77   case ARM::tADDspr:
78   case ARM::tBLXr:
79     return Instr->getOperand(2).getReg() != ARM::PC;
80   // ADD PC, SP and BLX PC were always unpredictable,
81   // now on top of it they're deprecated
82   case ARM::tADDrSP:
83   case ARM::tBX:
84     return Instr->getOperand(0).getReg() != ARM::PC;
85   case ARM::tADDhirr:
86     return Instr->getOperand(0).getReg() != ARM::PC &&
87            Instr->getOperand(2).getReg() != ARM::PC;
88   case ARM::tCMPhir:
89   case ARM::tMOVr:
90     return Instr->getOperand(0).getReg() != ARM::PC &&
91            Instr->getOperand(1).getReg() != ARM::PC;
92   }
93 }
94 
95 }
96 
97 #endif
98