1//===- PowerPCInstrFormats.td - PowerPC Instruction Formats --*- tablegen -*-=// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9 10//===----------------------------------------------------------------------===// 11// 12// PowerPC instruction formats 13 14class I<bits<6> opcode, dag OOL, dag IOL, string asmstr, InstrItinClass itin> 15 : Instruction { 16 field bits<32> Inst; 17 field bits<32> SoftFail = 0; 18 let Size = 4; 19 20 bit PPC64 = 0; // Default value, override with isPPC64 21 22 let Namespace = "PPC"; 23 let Inst{0-5} = opcode; 24 let OutOperandList = OOL; 25 let InOperandList = IOL; 26 let AsmString = asmstr; 27 let Itinerary = itin; 28 29 bits<1> PPC970_First = 0; 30 bits<1> PPC970_Single = 0; 31 bits<1> PPC970_Cracked = 0; 32 bits<3> PPC970_Unit = 0; 33 34 /// These fields correspond to the fields in PPCInstrInfo.h. Any changes to 35 /// these must be reflected there! See comments there for what these are. 36 let TSFlags{0} = PPC970_First; 37 let TSFlags{1} = PPC970_Single; 38 let TSFlags{2} = PPC970_Cracked; 39 let TSFlags{5-3} = PPC970_Unit; 40 41 // Fields used for relation models. 42 string BaseName = ""; 43 44 // For cases where multiple instruction definitions really represent the 45 // same underlying instruction but with one definition for 64-bit arguments 46 // and one for 32-bit arguments, this bit breaks the degeneracy between 47 // the two forms and allows TableGen to generate mapping tables. 48 bit Interpretation64Bit = 0; 49} 50 51class PPC970_DGroup_First { bits<1> PPC970_First = 1; } 52class PPC970_DGroup_Single { bits<1> PPC970_Single = 1; } 53class PPC970_DGroup_Cracked { bits<1> PPC970_Cracked = 1; } 54class PPC970_MicroCode; 55 56class PPC970_Unit_Pseudo { bits<3> PPC970_Unit = 0; } 57class PPC970_Unit_FXU { bits<3> PPC970_Unit = 1; } 58class PPC970_Unit_LSU { bits<3> PPC970_Unit = 2; } 59class PPC970_Unit_FPU { bits<3> PPC970_Unit = 3; } 60class PPC970_Unit_CRU { bits<3> PPC970_Unit = 4; } 61class PPC970_Unit_VALU { bits<3> PPC970_Unit = 5; } 62class PPC970_Unit_VPERM { bits<3> PPC970_Unit = 6; } 63class PPC970_Unit_BRU { bits<3> PPC970_Unit = 7; } 64 65// Two joined instructions; used to emit two adjacent instructions as one. 66// The itinerary from the first instruction is used for scheduling and 67// classification. 68class I2<bits<6> opcode1, bits<6> opcode2, dag OOL, dag IOL, string asmstr, 69 InstrItinClass itin> 70 : Instruction { 71 field bits<64> Inst; 72 field bits<64> SoftFail = 0; 73 let Size = 8; 74 75 bit PPC64 = 0; // Default value, override with isPPC64 76 77 let Namespace = "PPC"; 78 let Inst{0-5} = opcode1; 79 let Inst{32-37} = opcode2; 80 let OutOperandList = OOL; 81 let InOperandList = IOL; 82 let AsmString = asmstr; 83 let Itinerary = itin; 84 85 bits<1> PPC970_First = 0; 86 bits<1> PPC970_Single = 0; 87 bits<1> PPC970_Cracked = 0; 88 bits<3> PPC970_Unit = 0; 89 90 /// These fields correspond to the fields in PPCInstrInfo.h. Any changes to 91 /// these must be reflected there! See comments there for what these are. 92 let TSFlags{0} = PPC970_First; 93 let TSFlags{1} = PPC970_Single; 94 let TSFlags{2} = PPC970_Cracked; 95 let TSFlags{5-3} = PPC970_Unit; 96 97 // Fields used for relation models. 98 string BaseName = ""; 99 bit Interpretation64Bit = 0; 100} 101 102// 1.7.1 I-Form 103class IForm<bits<6> opcode, bit aa, bit lk, dag OOL, dag IOL, string asmstr, 104 InstrItinClass itin, list<dag> pattern> 105 : I<opcode, OOL, IOL, asmstr, itin> { 106 let Pattern = pattern; 107 bits<24> LI; 108 109 let Inst{6-29} = LI; 110 let Inst{30} = aa; 111 let Inst{31} = lk; 112} 113 114// 1.7.2 B-Form 115class BForm<bits<6> opcode, bit aa, bit lk, dag OOL, dag IOL, string asmstr> 116 : I<opcode, OOL, IOL, asmstr, IIC_BrB> { 117 bits<7> BIBO; // 2 bits of BI and 5 bits of BO. 118 bits<3> CR; 119 bits<14> BD; 120 121 bits<5> BI; 122 let BI{0-1} = BIBO{5-6}; 123 let BI{2-4} = CR{0-2}; 124 125 let Inst{6-10} = BIBO{4-0}; 126 let Inst{11-15} = BI; 127 let Inst{16-29} = BD; 128 let Inst{30} = aa; 129 let Inst{31} = lk; 130} 131 132class BForm_1<bits<6> opcode, bits<5> bo, bit aa, bit lk, dag OOL, dag IOL, 133 string asmstr> 134 : BForm<opcode, aa, lk, OOL, IOL, asmstr> { 135 let BIBO{4-0} = bo; 136 let BIBO{6-5} = 0; 137 let CR = 0; 138} 139 140class BForm_2<bits<6> opcode, bits<5> bo, bits<5> bi, bit aa, bit lk, 141 dag OOL, dag IOL, string asmstr> 142 : I<opcode, OOL, IOL, asmstr, IIC_BrB> { 143 bits<14> BD; 144 145 let Inst{6-10} = bo; 146 let Inst{11-15} = bi; 147 let Inst{16-29} = BD; 148 let Inst{30} = aa; 149 let Inst{31} = lk; 150} 151 152class BForm_3<bits<6> opcode, bit aa, bit lk, 153 dag OOL, dag IOL, string asmstr> 154 : I<opcode, OOL, IOL, asmstr, IIC_BrB> { 155 bits<5> BO; 156 bits<5> BI; 157 bits<14> BD; 158 159 let Inst{6-10} = BO; 160 let Inst{11-15} = BI; 161 let Inst{16-29} = BD; 162 let Inst{30} = aa; 163 let Inst{31} = lk; 164} 165 166class BForm_4<bits<6> opcode, bits<5> bo, bit aa, bit lk, 167 dag OOL, dag IOL, string asmstr> 168 : I<opcode, OOL, IOL, asmstr, IIC_BrB> { 169 bits<5> BI; 170 bits<14> BD; 171 172 let Inst{6-10} = bo; 173 let Inst{11-15} = BI; 174 let Inst{16-29} = BD; 175 let Inst{30} = aa; 176 let Inst{31} = lk; 177} 178 179// 1.7.3 SC-Form 180class SCForm<bits<6> opcode, bits<1> xo, 181 dag OOL, dag IOL, string asmstr, InstrItinClass itin, 182 list<dag> pattern> 183 : I<opcode, OOL, IOL, asmstr, itin> { 184 bits<7> LEV; 185 186 let Pattern = pattern; 187 188 let Inst{20-26} = LEV; 189 let Inst{30} = xo; 190} 191 192// 1.7.4 D-Form 193class DForm_base<bits<6> opcode, dag OOL, dag IOL, string asmstr, 194 InstrItinClass itin, list<dag> pattern> 195 : I<opcode, OOL, IOL, asmstr, itin> { 196 bits<5> A; 197 bits<5> B; 198 bits<16> C; 199 200 let Pattern = pattern; 201 202 let Inst{6-10} = A; 203 let Inst{11-15} = B; 204 let Inst{16-31} = C; 205} 206 207class DForm_1<bits<6> opcode, dag OOL, dag IOL, string asmstr, 208 InstrItinClass itin, list<dag> pattern> 209 : I<opcode, OOL, IOL, asmstr, itin> { 210 bits<5> A; 211 bits<21> Addr; 212 213 let Pattern = pattern; 214 215 let Inst{6-10} = A; 216 let Inst{11-15} = Addr{20-16}; // Base Reg 217 let Inst{16-31} = Addr{15-0}; // Displacement 218} 219 220class DForm_1a<bits<6> opcode, dag OOL, dag IOL, string asmstr, 221 InstrItinClass itin, list<dag> pattern> 222 : I<opcode, OOL, IOL, asmstr, itin> { 223 bits<5> A; 224 bits<16> C; 225 bits<5> B; 226 227 let Pattern = pattern; 228 229 let Inst{6-10} = A; 230 let Inst{11-15} = B; 231 let Inst{16-31} = C; 232} 233 234 235class DForm_2<bits<6> opcode, dag OOL, dag IOL, string asmstr, 236 InstrItinClass itin, list<dag> pattern> 237 : DForm_base<opcode, OOL, IOL, asmstr, itin, pattern> { 238 239 // Even though ADDICo does not really have an RC bit, provide 240 // the declaration of one here so that isDOT has something to set. 241 bit RC = 0; 242} 243 244class DForm_2_r0<bits<6> opcode, dag OOL, dag IOL, string asmstr, 245 InstrItinClass itin, list<dag> pattern> 246 : I<opcode, OOL, IOL, asmstr, itin> { 247 bits<5> A; 248 bits<16> B; 249 250 let Pattern = pattern; 251 252 let Inst{6-10} = A; 253 let Inst{11-15} = 0; 254 let Inst{16-31} = B; 255} 256 257class DForm_4<bits<6> opcode, dag OOL, dag IOL, string asmstr, 258 InstrItinClass itin, list<dag> pattern> 259 : I<opcode, OOL, IOL, asmstr, itin> { 260 bits<5> B; 261 bits<5> A; 262 bits<16> C; 263 264 let Pattern = pattern; 265 266 let Inst{6-10} = A; 267 let Inst{11-15} = B; 268 let Inst{16-31} = C; 269} 270 271class DForm_4_zero<bits<6> opcode, dag OOL, dag IOL, string asmstr, 272 InstrItinClass itin, list<dag> pattern> 273 : DForm_1<opcode, OOL, IOL, asmstr, itin, pattern> { 274 let A = 0; 275 let Addr = 0; 276} 277 278class DForm_4_fixedreg_zero<bits<6> opcode, bits<5> R, dag OOL, dag IOL, 279 string asmstr, InstrItinClass itin, 280 list<dag> pattern> 281 : DForm_4<opcode, OOL, IOL, asmstr, itin, pattern> { 282 let A = R; 283 let B = R; 284 let C = 0; 285} 286 287class IForm_and_DForm_1<bits<6> opcode1, bit aa, bit lk, bits<6> opcode2, 288 dag OOL, dag IOL, string asmstr, 289 InstrItinClass itin, list<dag> pattern> 290 : I2<opcode1, opcode2, OOL, IOL, asmstr, itin> { 291 bits<5> A; 292 bits<21> Addr; 293 294 let Pattern = pattern; 295 bits<24> LI; 296 297 let Inst{6-29} = LI; 298 let Inst{30} = aa; 299 let Inst{31} = lk; 300 301 let Inst{38-42} = A; 302 let Inst{43-47} = Addr{20-16}; // Base Reg 303 let Inst{48-63} = Addr{15-0}; // Displacement 304} 305 306// This is used to emit BL8+NOP. 307class IForm_and_DForm_4_zero<bits<6> opcode1, bit aa, bit lk, bits<6> opcode2, 308 dag OOL, dag IOL, string asmstr, 309 InstrItinClass itin, list<dag> pattern> 310 : IForm_and_DForm_1<opcode1, aa, lk, opcode2, 311 OOL, IOL, asmstr, itin, pattern> { 312 let A = 0; 313 let Addr = 0; 314} 315 316class DForm_5<bits<6> opcode, dag OOL, dag IOL, string asmstr, 317 InstrItinClass itin> 318 : I<opcode, OOL, IOL, asmstr, itin> { 319 bits<3> BF; 320 bits<1> L; 321 bits<5> RA; 322 bits<16> I; 323 324 let Inst{6-8} = BF; 325 let Inst{9} = 0; 326 let Inst{10} = L; 327 let Inst{11-15} = RA; 328 let Inst{16-31} = I; 329} 330 331class DForm_5_ext<bits<6> opcode, dag OOL, dag IOL, string asmstr, 332 InstrItinClass itin> 333 : DForm_5<opcode, OOL, IOL, asmstr, itin> { 334 let L = PPC64; 335} 336 337class DForm_6<bits<6> opcode, dag OOL, dag IOL, string asmstr, 338 InstrItinClass itin> 339 : DForm_5<opcode, OOL, IOL, asmstr, itin>; 340 341class DForm_6_ext<bits<6> opcode, dag OOL, dag IOL, string asmstr, 342 InstrItinClass itin> 343 : DForm_6<opcode, OOL, IOL, asmstr, itin> { 344 let L = PPC64; 345} 346 347 348// 1.7.5 DS-Form 349class DSForm_1<bits<6> opcode, bits<2> xo, dag OOL, dag IOL, string asmstr, 350 InstrItinClass itin, list<dag> pattern> 351 : I<opcode, OOL, IOL, asmstr, itin> { 352 bits<5> RST; 353 bits<19> DS_RA; 354 355 let Pattern = pattern; 356 357 let Inst{6-10} = RST; 358 let Inst{11-15} = DS_RA{18-14}; // Register # 359 let Inst{16-29} = DS_RA{13-0}; // Displacement. 360 let Inst{30-31} = xo; 361} 362 363// DQ-Form: [PO T RA DQ TX XO] or [PO S RA DQ SX XO] 364class DQ_RD6_RS5_DQ12<bits<6> opcode, bits<3> xo, dag OOL, dag IOL, 365 string asmstr, InstrItinClass itin, list<dag> pattern> 366 : I<opcode, OOL, IOL, asmstr, itin> { 367 bits<6> XT; 368 bits<17> DS_RA; 369 370 let Pattern = pattern; 371 372 let Inst{6-10} = XT{4-0}; 373 let Inst{11-15} = DS_RA{16-12}; // Register # 374 let Inst{16-27} = DS_RA{11-0}; // Displacement. 375 let Inst{28} = XT{5}; 376 let Inst{29-31} = xo; 377} 378 379// 1.7.6 X-Form 380class XForm_base_r3xo<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 381 InstrItinClass itin, list<dag> pattern> 382 : I<opcode, OOL, IOL, asmstr, itin> { 383 bits<5> RST; 384 bits<5> A; 385 bits<5> B; 386 387 let Pattern = pattern; 388 389 bit RC = 0; // set by isDOT 390 391 let Inst{6-10} = RST; 392 let Inst{11-15} = A; 393 let Inst{16-20} = B; 394 let Inst{21-30} = xo; 395 let Inst{31} = RC; 396} 397 398class XForm_tlb<bits<10> xo, dag OOL, dag IOL, string asmstr, 399 InstrItinClass itin> : XForm_base_r3xo<31, xo, OOL, IOL, asmstr, itin, []> { 400 let RST = 0; 401} 402 403class XForm_attn<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 404 InstrItinClass itin> 405 : I<opcode, OOL, IOL, asmstr, itin> { 406 let Inst{21-30} = xo; 407} 408 409// This is the same as XForm_base_r3xo, but the first two operands are swapped 410// when code is emitted. 411class XForm_base_r3xo_swapped 412 <bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 413 InstrItinClass itin> 414 : I<opcode, OOL, IOL, asmstr, itin> { 415 bits<5> A; 416 bits<5> RST; 417 bits<5> B; 418 419 bit RC = 0; // set by isDOT 420 421 let Inst{6-10} = RST; 422 let Inst{11-15} = A; 423 let Inst{16-20} = B; 424 let Inst{21-30} = xo; 425 let Inst{31} = RC; 426} 427 428 429class XForm_1<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 430 InstrItinClass itin, list<dag> pattern> 431 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern>; 432 433class XForm_1a<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 434 InstrItinClass itin, list<dag> pattern> 435 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 436 let RST = 0; 437} 438 439class XForm_rs<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 440 InstrItinClass itin, list<dag> pattern> 441 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 442 let A = 0; 443 let B = 0; 444} 445 446class XForm_tlbws<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 447 InstrItinClass itin, list<dag> pattern> 448 : I<opcode, OOL, IOL, asmstr, itin> { 449 bits<5> RST; 450 bits<5> A; 451 bits<1> WS; 452 453 let Pattern = pattern; 454 455 let Inst{6-10} = RST; 456 let Inst{11-15} = A; 457 let Inst{20} = WS; 458 let Inst{21-30} = xo; 459 let Inst{31} = 0; 460} 461 462class XForm_6<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 463 InstrItinClass itin, list<dag> pattern> 464 : XForm_base_r3xo_swapped<opcode, xo, OOL, IOL, asmstr, itin> { 465 let Pattern = pattern; 466} 467 468class XForm_8<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 469 InstrItinClass itin, list<dag> pattern> 470 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern>; 471 472class XForm_10<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 473 InstrItinClass itin, list<dag> pattern> 474 : XForm_base_r3xo_swapped<opcode, xo, OOL, IOL, asmstr, itin> { 475 let Pattern = pattern; 476} 477 478class XForm_11<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 479 InstrItinClass itin, list<dag> pattern> 480 : XForm_base_r3xo_swapped<opcode, xo, OOL, IOL, asmstr, itin> { 481 let B = 0; 482 let Pattern = pattern; 483} 484 485class XForm_16<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 486 InstrItinClass itin> 487 : I<opcode, OOL, IOL, asmstr, itin> { 488 bits<3> BF; 489 bits<1> L; 490 bits<5> RA; 491 bits<5> RB; 492 493 let Inst{6-8} = BF; 494 let Inst{9} = 0; 495 let Inst{10} = L; 496 let Inst{11-15} = RA; 497 let Inst{16-20} = RB; 498 let Inst{21-30} = xo; 499 let Inst{31} = 0; 500} 501 502class XForm_icbt<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 503 InstrItinClass itin> 504 : I<opcode, OOL, IOL, asmstr, itin> { 505 bits<4> CT; 506 bits<5> RA; 507 bits<5> RB; 508 509 let Inst{6} = 0; 510 let Inst{7-10} = CT; 511 let Inst{11-15} = RA; 512 let Inst{16-20} = RB; 513 let Inst{21-30} = xo; 514 let Inst{31} = 0; 515} 516 517class XForm_sr<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 518 InstrItinClass itin> 519 : I<opcode, OOL, IOL, asmstr, itin> { 520 bits<5> RS; 521 bits<4> SR; 522 523 let Inst{6-10} = RS; 524 let Inst{12-15} = SR; 525 let Inst{21-30} = xo; 526} 527 528class XForm_mbar<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 529 InstrItinClass itin> 530 : I<opcode, OOL, IOL, asmstr, itin> { 531 bits<5> MO; 532 533 let Inst{6-10} = MO; 534 let Inst{21-30} = xo; 535} 536 537class XForm_srin<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 538 InstrItinClass itin> 539 : I<opcode, OOL, IOL, asmstr, itin> { 540 bits<5> RS; 541 bits<5> RB; 542 543 let Inst{6-10} = RS; 544 let Inst{16-20} = RB; 545 let Inst{21-30} = xo; 546} 547 548class XForm_mtmsr<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 549 InstrItinClass itin> 550 : I<opcode, OOL, IOL, asmstr, itin> { 551 bits<5> RS; 552 bits<1> L; 553 554 let Inst{6-10} = RS; 555 let Inst{15} = L; 556 let Inst{21-30} = xo; 557} 558 559class XForm_16_ext<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 560 InstrItinClass itin> 561 : XForm_16<opcode, xo, OOL, IOL, asmstr, itin> { 562 let L = PPC64; 563} 564 565class XForm_17<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 566 InstrItinClass itin> 567 : I<opcode, OOL, IOL, asmstr, itin> { 568 bits<3> BF; 569 bits<5> FRA; 570 bits<5> FRB; 571 572 let Inst{6-8} = BF; 573 let Inst{9-10} = 0; 574 let Inst{11-15} = FRA; 575 let Inst{16-20} = FRB; 576 let Inst{21-30} = xo; 577 let Inst{31} = 0; 578} 579 580// Used for QPX 581class XForm_18<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 582 InstrItinClass itin, list<dag> pattern> 583 : I<opcode, OOL, IOL, asmstr, itin> { 584 bits<5> FRT; 585 bits<5> FRA; 586 bits<5> FRB; 587 588 let Pattern = pattern; 589 590 let Inst{6-10} = FRT; 591 let Inst{11-15} = FRA; 592 let Inst{16-20} = FRB; 593 let Inst{21-30} = xo; 594 let Inst{31} = 0; 595} 596 597class XForm_19<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 598 InstrItinClass itin, list<dag> pattern> 599 : XForm_18<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 600 let FRA = 0; 601} 602 603class XForm_20<bits<6> opcode, bits<6> xo, dag OOL, dag IOL, string asmstr, 604 InstrItinClass itin, list<dag> pattern> 605 : I<opcode, OOL, IOL, asmstr, itin> { 606 bits<5> FRT; 607 bits<5> FRA; 608 bits<5> FRB; 609 bits<4> tttt; 610 611 let Pattern = pattern; 612 613 let Inst{6-10} = FRT; 614 let Inst{11-15} = FRA; 615 let Inst{16-20} = FRB; 616 let Inst{21-24} = tttt; 617 let Inst{25-30} = xo; 618 let Inst{31} = 0; 619} 620 621class XForm_24<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 622 InstrItinClass itin, list<dag> pattern> 623 : I<opcode, OOL, IOL, asmstr, itin> { 624 let Pattern = pattern; 625 let Inst{6-10} = 31; 626 let Inst{11-15} = 0; 627 let Inst{16-20} = 0; 628 let Inst{21-30} = xo; 629 let Inst{31} = 0; 630} 631 632class XForm_24_sync<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 633 string asmstr, InstrItinClass itin, list<dag> pattern> 634 : I<opcode, OOL, IOL, asmstr, itin> { 635 bits<2> L; 636 637 let Pattern = pattern; 638 let Inst{6-8} = 0; 639 let Inst{9-10} = L; 640 let Inst{11-15} = 0; 641 let Inst{16-20} = 0; 642 let Inst{21-30} = xo; 643 let Inst{31} = 0; 644} 645 646class XForm_24_eieio<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 647 string asmstr, InstrItinClass itin, list<dag> pattern> 648 : XForm_24_sync<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 649 let L = 0; 650} 651 652class XForm_25<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 653 InstrItinClass itin, list<dag> pattern> 654 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 655} 656 657class XForm_26<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 658 InstrItinClass itin, list<dag> pattern> 659 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 660 let A = 0; 661} 662 663class XForm_28<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 664 InstrItinClass itin, list<dag> pattern> 665 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 666} 667 668// This is used for MFFS, MTFSB0, MTFSB1. 42 is arbitrary; this series of 669// numbers presumably relates to some document, but I haven't found it. 670class XForm_42<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 671 InstrItinClass itin, list<dag> pattern> 672 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 673 let Pattern = pattern; 674 675 bit RC = 0; // set by isDOT 676 677 let Inst{6-10} = RST; 678 let Inst{11-20} = 0; 679 let Inst{21-30} = xo; 680 let Inst{31} = RC; 681} 682class XForm_43<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 683 InstrItinClass itin, list<dag> pattern> 684 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 685 let Pattern = pattern; 686 bits<5> FM; 687 688 bit RC = 0; // set by isDOT 689 690 let Inst{6-10} = FM; 691 let Inst{11-20} = 0; 692 let Inst{21-30} = xo; 693 let Inst{31} = RC; 694} 695 696class XForm_0<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 697 InstrItinClass itin, list<dag> pattern> 698 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 699 let RST = 0; 700 let A = 0; 701 let B = 0; 702} 703 704class XForm_16b<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 705 InstrItinClass itin, list<dag> pattern> 706 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 707 let RST = 0; 708 let A = 0; 709} 710 711class XForm_htm0<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 712 string asmstr, InstrItinClass itin, list<dag> pattern> 713 : I<opcode, OOL, IOL, asmstr, itin> { 714 bit R; 715 716 bit RC = 1; 717 718 let Inst{6-9} = 0; 719 let Inst{10} = R; 720 let Inst{11-20} = 0; 721 let Inst{21-30} = xo; 722 let Inst{31} = RC; 723} 724 725class XForm_htm1<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 726 string asmstr, InstrItinClass itin, list<dag> pattern> 727 : I<opcode, OOL, IOL, asmstr, itin> { 728 bit A; 729 730 bit RC = 1; 731 732 let Inst{6} = A; 733 let Inst{7-20} = 0; 734 let Inst{21-30} = xo; 735 let Inst{31} = RC; 736} 737 738class XForm_htm2<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 739 InstrItinClass itin, list<dag> pattern> 740 : I<opcode, OOL, IOL, asmstr, itin> { 741 bit L; 742 743 bit RC = 0; // set by isDOT 744 745 let Inst{7-9} = 0; 746 let Inst{10} = L; 747 let Inst{11-20} = 0; 748 let Inst{21-30} = xo; 749 let Inst{31} = RC; 750} 751 752class XForm_htm3<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 753 InstrItinClass itin, list<dag> pattern> 754 : I<opcode, OOL, IOL, asmstr, itin> { 755 bits<3> BF; 756 757 bit RC = 0; 758 759 let Inst{6-8} = BF; 760 let Inst{9-20} = 0; 761 let Inst{21-30} = xo; 762 let Inst{31} = RC; 763} 764 765// [PO RT RA RB XO /] 766class X_BF3_L1_RS5_RS5<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 767 string asmstr, InstrItinClass itin, list<dag> pattern> 768 : I<opcode, OOL, IOL, asmstr, itin> { 769 bits<3> BF; 770 bits<1> L; 771 bits<5> RA; 772 bits<5> RB; 773 774 let Pattern = pattern; 775 776 let Inst{6-8} = BF; 777 let Inst{9} = 0; 778 let Inst{10} = L; 779 let Inst{11-15} = RA; 780 let Inst{16-20} = RB; 781 let Inst{21-30} = xo; 782 let Inst{31} = 0; 783} 784 785// Same as XForm_17 but with GPR's and new naming convention 786class X_BF3_RS5_RS5<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 787 string asmstr, InstrItinClass itin, list<dag> pattern> 788 : I<opcode, OOL, IOL, asmstr, itin> { 789 bits<3> BF; 790 bits<5> RA; 791 bits<5> RB; 792 793 let Pattern = pattern; 794 795 let Inst{6-8} = BF; 796 let Inst{9-10} = 0; 797 let Inst{11-15} = RA; 798 let Inst{16-20} = RB; 799 let Inst{21-30} = xo; 800 let Inst{31} = 0; 801} 802 803// e.g. [PO VRT XO VRB XO /] or [PO VRT XO VRB XO RO] 804class X_RD5_XO5_RS5<bits<6> opcode, bits<5> xo2, bits<10> xo, dag OOL, dag IOL, 805 string asmstr, InstrItinClass itin, list<dag> pattern> 806 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 807 let A = xo2; 808} 809 810class X_BF3_DCMX7_RS5<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 811 string asmstr, InstrItinClass itin, list<dag> pattern> 812 : I<opcode, OOL, IOL, asmstr, itin> { 813 bits<3> BF; 814 bits<7> DCMX; 815 bits<5> VB; 816 817 let Pattern = pattern; 818 819 let Inst{6-8} = BF; 820 let Inst{9-15} = DCMX; 821 let Inst{16-20} = VB; 822 let Inst{21-30} = xo; 823 let Inst{31} = 0; 824} 825 826class X_RD6_IMM8<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 827 string asmstr, InstrItinClass itin, list<dag> pattern> 828 : I<opcode, OOL, IOL, asmstr, itin> { 829 bits<6> XT; 830 bits<8> IMM8; 831 832 let Pattern = pattern; 833 834 let Inst{6-10} = XT{4-0}; 835 let Inst{11-12} = 0; 836 let Inst{13-20} = IMM8; 837 let Inst{21-30} = xo; 838 let Inst{31} = XT{5}; 839} 840 841// XForm_base_r3xo for instructions such as P9 atomics where we don't want 842// to specify an SDAG pattern for matching. 843class X_RD5_RS5_IM5<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 844 string asmstr, InstrItinClass itin> 845 : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, []> { 846} 847 848class X_BF3<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 849 InstrItinClass itin> 850 : XForm_17<opcode, xo, OOL, IOL, asmstr, itin> { 851 let FRA = 0; 852 let FRB = 0; 853} 854 855// [PO /// L RA RB XO /] 856class X_L1_RS5_RS5<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 857 string asmstr, InstrItinClass itin, list<dag> pattern> 858 : XForm_16<opcode, xo, OOL, IOL, asmstr, itin> { 859 let BF = 0; 860 let Pattern = pattern; 861 862 bit RC = 0; 863 let Inst{31} = RC; 864} 865 866// XX*-Form (VSX) 867class XX1Form<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 868 InstrItinClass itin, list<dag> pattern> 869 : I<opcode, OOL, IOL, asmstr, itin> { 870 bits<6> XT; 871 bits<5> A; 872 bits<5> B; 873 874 let Pattern = pattern; 875 876 let Inst{6-10} = XT{4-0}; 877 let Inst{11-15} = A; 878 let Inst{16-20} = B; 879 let Inst{21-30} = xo; 880 let Inst{31} = XT{5}; 881} 882 883class XX1_RS6_RD5_XO<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, 884 string asmstr, InstrItinClass itin, list<dag> pattern> 885 : XX1Form<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 886 let B = 0; 887} 888 889class XX2Form<bits<6> opcode, bits<9> xo, dag OOL, dag IOL, string asmstr, 890 InstrItinClass itin, list<dag> pattern> 891 : I<opcode, OOL, IOL, asmstr, itin> { 892 bits<6> XT; 893 bits<6> XB; 894 895 let Pattern = pattern; 896 897 let Inst{6-10} = XT{4-0}; 898 let Inst{11-15} = 0; 899 let Inst{16-20} = XB{4-0}; 900 let Inst{21-29} = xo; 901 let Inst{30} = XB{5}; 902 let Inst{31} = XT{5}; 903} 904 905class XX2Form_1<bits<6> opcode, bits<9> xo, dag OOL, dag IOL, string asmstr, 906 InstrItinClass itin, list<dag> pattern> 907 : I<opcode, OOL, IOL, asmstr, itin> { 908 bits<3> CR; 909 bits<6> XB; 910 911 let Pattern = pattern; 912 913 let Inst{6-8} = CR; 914 let Inst{9-15} = 0; 915 let Inst{16-20} = XB{4-0}; 916 let Inst{21-29} = xo; 917 let Inst{30} = XB{5}; 918 let Inst{31} = 0; 919} 920 921class XX2Form_2<bits<6> opcode, bits<9> xo, dag OOL, dag IOL, string asmstr, 922 InstrItinClass itin, list<dag> pattern> 923 : I<opcode, OOL, IOL, asmstr, itin> { 924 bits<6> XT; 925 bits<6> XB; 926 bits<2> D; 927 928 let Pattern = pattern; 929 930 let Inst{6-10} = XT{4-0}; 931 let Inst{11-13} = 0; 932 let Inst{14-15} = D; 933 let Inst{16-20} = XB{4-0}; 934 let Inst{21-29} = xo; 935 let Inst{30} = XB{5}; 936 let Inst{31} = XT{5}; 937} 938 939class XX2_RD6_UIM5_RS6<bits<6> opcode, bits<9> xo, dag OOL, dag IOL, 940 string asmstr, InstrItinClass itin, list<dag> pattern> 941 : I<opcode, OOL, IOL, asmstr, itin> { 942 bits<6> XT; 943 bits<6> XB; 944 bits<5> UIM5; 945 946 let Pattern = pattern; 947 948 let Inst{6-10} = XT{4-0}; 949 let Inst{11-15} = UIM5; 950 let Inst{16-20} = XB{4-0}; 951 let Inst{21-29} = xo; 952 let Inst{30} = XB{5}; 953 let Inst{31} = XT{5}; 954} 955 956// [PO T XO B XO BX /] 957class XX2_RD5_XO5_RS6<bits<6> opcode, bits<5> xo2, bits<9> xo, dag OOL, dag IOL, 958 string asmstr, InstrItinClass itin, list<dag> pattern> 959 : I<opcode, OOL, IOL, asmstr, itin> { 960 bits<5> RT; 961 bits<6> XB; 962 963 let Pattern = pattern; 964 965 let Inst{6-10} = RT; 966 let Inst{11-15} = xo2; 967 let Inst{16-20} = XB{4-0}; 968 let Inst{21-29} = xo; 969 let Inst{30} = XB{5}; 970 let Inst{31} = 0; 971} 972 973// [PO T XO B XO BX TX] 974class XX2_RD6_XO5_RS6<bits<6> opcode, bits<5> xo2, bits<9> xo, dag OOL, dag IOL, 975 string asmstr, InstrItinClass itin, list<dag> pattern> 976 : I<opcode, OOL, IOL, asmstr, itin> { 977 bits<6> XT; 978 bits<6> XB; 979 980 let Pattern = pattern; 981 982 let Inst{6-10} = XT{4-0}; 983 let Inst{11-15} = xo2; 984 let Inst{16-20} = XB{4-0}; 985 let Inst{21-29} = xo; 986 let Inst{30} = XB{5}; 987 let Inst{31} = XT{5}; 988} 989 990class XX2_BF3_DCMX7_RS6<bits<6> opcode, bits<9> xo, dag OOL, dag IOL, 991 string asmstr, InstrItinClass itin, list<dag> pattern> 992 : I<opcode, OOL, IOL, asmstr, itin> { 993 bits<3> BF; 994 bits<7> DCMX; 995 bits<6> XB; 996 997 let Pattern = pattern; 998 999 let Inst{6-8} = BF; 1000 let Inst{9-15} = DCMX; 1001 let Inst{16-20} = XB{4-0}; 1002 let Inst{21-29} = xo; 1003 let Inst{30} = XB{5}; 1004 let Inst{31} = 0; 1005} 1006 1007class XX2_RD6_DCMX7_RS6<bits<6> opcode, bits<4> xo1, bits<3> xo2, 1008 dag OOL, dag IOL, string asmstr, InstrItinClass itin, 1009 list<dag> pattern> 1010 : I<opcode, OOL, IOL, asmstr, itin> { 1011 bits<6> XT; 1012 bits<7> DCMX; 1013 bits<6> XB; 1014 1015 let Pattern = pattern; 1016 1017 let Inst{6-10} = XT{4-0}; 1018 let Inst{11-15} = DCMX{4-0}; 1019 let Inst{16-20} = XB{4-0}; 1020 let Inst{21-24} = xo1; 1021 let Inst{25} = DCMX{5}; 1022 let Inst{26-28} = xo2; 1023 let Inst{29} = DCMX{6}; 1024 let Inst{30} = XB{5}; 1025 let Inst{31} = XT{5}; 1026} 1027 1028class XX3Form<bits<6> opcode, bits<8> xo, dag OOL, dag IOL, string asmstr, 1029 InstrItinClass itin, list<dag> pattern> 1030 : I<opcode, OOL, IOL, asmstr, itin> { 1031 bits<6> XT; 1032 bits<6> XA; 1033 bits<6> XB; 1034 1035 let Pattern = pattern; 1036 1037 let Inst{6-10} = XT{4-0}; 1038 let Inst{11-15} = XA{4-0}; 1039 let Inst{16-20} = XB{4-0}; 1040 let Inst{21-28} = xo; 1041 let Inst{29} = XA{5}; 1042 let Inst{30} = XB{5}; 1043 let Inst{31} = XT{5}; 1044} 1045 1046class XX3Form_1<bits<6> opcode, bits<8> xo, dag OOL, dag IOL, string asmstr, 1047 InstrItinClass itin, list<dag> pattern> 1048 : I<opcode, OOL, IOL, asmstr, itin> { 1049 bits<3> CR; 1050 bits<6> XA; 1051 bits<6> XB; 1052 1053 let Pattern = pattern; 1054 1055 let Inst{6-8} = CR; 1056 let Inst{9-10} = 0; 1057 let Inst{11-15} = XA{4-0}; 1058 let Inst{16-20} = XB{4-0}; 1059 let Inst{21-28} = xo; 1060 let Inst{29} = XA{5}; 1061 let Inst{30} = XB{5}; 1062 let Inst{31} = 0; 1063} 1064 1065class XX3Form_2<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, string asmstr, 1066 InstrItinClass itin, list<dag> pattern> 1067 : I<opcode, OOL, IOL, asmstr, itin> { 1068 bits<6> XT; 1069 bits<6> XA; 1070 bits<6> XB; 1071 bits<2> D; 1072 1073 let Pattern = pattern; 1074 1075 let Inst{6-10} = XT{4-0}; 1076 let Inst{11-15} = XA{4-0}; 1077 let Inst{16-20} = XB{4-0}; 1078 let Inst{21} = 0; 1079 let Inst{22-23} = D; 1080 let Inst{24-28} = xo; 1081 let Inst{29} = XA{5}; 1082 let Inst{30} = XB{5}; 1083 let Inst{31} = XT{5}; 1084} 1085 1086class XX3Form_Rc<bits<6> opcode, bits<7> xo, dag OOL, dag IOL, string asmstr, 1087 InstrItinClass itin, list<dag> pattern> 1088 : I<opcode, OOL, IOL, asmstr, itin> { 1089 bits<6> XT; 1090 bits<6> XA; 1091 bits<6> XB; 1092 1093 let Pattern = pattern; 1094 1095 bit RC = 0; // set by isDOT 1096 1097 let Inst{6-10} = XT{4-0}; 1098 let Inst{11-15} = XA{4-0}; 1099 let Inst{16-20} = XB{4-0}; 1100 let Inst{21} = RC; 1101 let Inst{22-28} = xo; 1102 let Inst{29} = XA{5}; 1103 let Inst{30} = XB{5}; 1104 let Inst{31} = XT{5}; 1105} 1106 1107class XX4Form<bits<6> opcode, bits<2> xo, dag OOL, dag IOL, string asmstr, 1108 InstrItinClass itin, list<dag> pattern> 1109 : I<opcode, OOL, IOL, asmstr, itin> { 1110 bits<6> XT; 1111 bits<6> XA; 1112 bits<6> XB; 1113 bits<6> XC; 1114 1115 let Pattern = pattern; 1116 1117 let Inst{6-10} = XT{4-0}; 1118 let Inst{11-15} = XA{4-0}; 1119 let Inst{16-20} = XB{4-0}; 1120 let Inst{21-25} = XC{4-0}; 1121 let Inst{26-27} = xo; 1122 let Inst{28} = XC{5}; 1123 let Inst{29} = XA{5}; 1124 let Inst{30} = XB{5}; 1125 let Inst{31} = XT{5}; 1126} 1127 1128// DCB_Form - Form X instruction, used for dcb* instructions. 1129class DCB_Form<bits<10> xo, bits<5> immfield, dag OOL, dag IOL, string asmstr, 1130 InstrItinClass itin, list<dag> pattern> 1131 : I<31, OOL, IOL, asmstr, itin> { 1132 bits<5> A; 1133 bits<5> B; 1134 1135 let Pattern = pattern; 1136 1137 let Inst{6-10} = immfield; 1138 let Inst{11-15} = A; 1139 let Inst{16-20} = B; 1140 let Inst{21-30} = xo; 1141 let Inst{31} = 0; 1142} 1143 1144class DCB_Form_hint<bits<10> xo, dag OOL, dag IOL, string asmstr, 1145 InstrItinClass itin, list<dag> pattern> 1146 : I<31, OOL, IOL, asmstr, itin> { 1147 bits<5> TH; 1148 bits<5> A; 1149 bits<5> B; 1150 1151 let Pattern = pattern; 1152 1153 let Inst{6-10} = TH; 1154 let Inst{11-15} = A; 1155 let Inst{16-20} = B; 1156 let Inst{21-30} = xo; 1157 let Inst{31} = 0; 1158} 1159 1160// DSS_Form - Form X instruction, used for altivec dss* instructions. 1161class DSS_Form<bits<1> T, bits<10> xo, dag OOL, dag IOL, string asmstr, 1162 InstrItinClass itin, list<dag> pattern> 1163 : I<31, OOL, IOL, asmstr, itin> { 1164 bits<2> STRM; 1165 bits<5> A; 1166 bits<5> B; 1167 1168 let Pattern = pattern; 1169 1170 let Inst{6} = T; 1171 let Inst{7-8} = 0; 1172 let Inst{9-10} = STRM; 1173 let Inst{11-15} = A; 1174 let Inst{16-20} = B; 1175 let Inst{21-30} = xo; 1176 let Inst{31} = 0; 1177} 1178 1179// 1.7.7 XL-Form 1180class XLForm_1<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 1181 InstrItinClass itin, list<dag> pattern> 1182 : I<opcode, OOL, IOL, asmstr, itin> { 1183 bits<5> CRD; 1184 bits<5> CRA; 1185 bits<5> CRB; 1186 1187 let Pattern = pattern; 1188 1189 let Inst{6-10} = CRD; 1190 let Inst{11-15} = CRA; 1191 let Inst{16-20} = CRB; 1192 let Inst{21-30} = xo; 1193 let Inst{31} = 0; 1194} 1195 1196class XLForm_1_ext<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 1197 InstrItinClass itin, list<dag> pattern> 1198 : I<opcode, OOL, IOL, asmstr, itin> { 1199 bits<5> CRD; 1200 1201 let Pattern = pattern; 1202 1203 let Inst{6-10} = CRD; 1204 let Inst{11-15} = CRD; 1205 let Inst{16-20} = CRD; 1206 let Inst{21-30} = xo; 1207 let Inst{31} = 0; 1208} 1209 1210class XLForm_2<bits<6> opcode, bits<10> xo, bit lk, dag OOL, dag IOL, string asmstr, 1211 InstrItinClass itin, list<dag> pattern> 1212 : I<opcode, OOL, IOL, asmstr, itin> { 1213 bits<5> BO; 1214 bits<5> BI; 1215 bits<2> BH; 1216 1217 let Pattern = pattern; 1218 1219 let Inst{6-10} = BO; 1220 let Inst{11-15} = BI; 1221 let Inst{16-18} = 0; 1222 let Inst{19-20} = BH; 1223 let Inst{21-30} = xo; 1224 let Inst{31} = lk; 1225} 1226 1227class XLForm_2_br<bits<6> opcode, bits<10> xo, bit lk, 1228 dag OOL, dag IOL, string asmstr, InstrItinClass itin, list<dag> pattern> 1229 : XLForm_2<opcode, xo, lk, OOL, IOL, asmstr, itin, pattern> { 1230 bits<7> BIBO; // 2 bits of BI and 5 bits of BO. 1231 bits<3> CR; 1232 1233 let BO = BIBO{4-0}; 1234 let BI{0-1} = BIBO{5-6}; 1235 let BI{2-4} = CR{0-2}; 1236 let BH = 0; 1237} 1238 1239class XLForm_2_br2<bits<6> opcode, bits<10> xo, bits<5> bo, bit lk, 1240 dag OOL, dag IOL, string asmstr, InstrItinClass itin, list<dag> pattern> 1241 : XLForm_2<opcode, xo, lk, OOL, IOL, asmstr, itin, pattern> { 1242 let BO = bo; 1243 let BH = 0; 1244} 1245 1246class XLForm_2_ext<bits<6> opcode, bits<10> xo, bits<5> bo, bits<5> bi, bit lk, 1247 dag OOL, dag IOL, string asmstr, InstrItinClass itin, list<dag> pattern> 1248 : XLForm_2<opcode, xo, lk, OOL, IOL, asmstr, itin, pattern> { 1249 let BO = bo; 1250 let BI = bi; 1251 let BH = 0; 1252} 1253 1254class XLForm_3<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 1255 InstrItinClass itin> 1256 : I<opcode, OOL, IOL, asmstr, itin> { 1257 bits<3> BF; 1258 bits<3> BFA; 1259 1260 let Inst{6-8} = BF; 1261 let Inst{9-10} = 0; 1262 let Inst{11-13} = BFA; 1263 let Inst{14-15} = 0; 1264 let Inst{16-20} = 0; 1265 let Inst{21-30} = xo; 1266 let Inst{31} = 0; 1267} 1268 1269class XLForm_4<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 1270 InstrItinClass itin> 1271 : I<opcode, OOL, IOL, asmstr, itin> { 1272 bits<3> BF; 1273 bit W; 1274 bits<4> U; 1275 1276 bit RC = 0; 1277 1278 let Inst{6-8} = BF; 1279 let Inst{9-10} = 0; 1280 let Inst{11-14} = 0; 1281 let Inst{15} = W; 1282 let Inst{16-19} = U; 1283 let Inst{20} = 0; 1284 let Inst{21-30} = xo; 1285 let Inst{31} = RC; 1286} 1287 1288class XLForm_S<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 1289 InstrItinClass itin, list<dag> pattern> 1290 : I<opcode, OOL, IOL, asmstr, itin> { 1291 bits<1> S; 1292 1293 let Pattern = pattern; 1294 1295 let Inst{6-19} = 0; 1296 let Inst{20} = S; 1297 let Inst{21-30} = xo; 1298 let Inst{31} = 0; 1299} 1300 1301class XLForm_2_and_DSForm_1<bits<6> opcode1, bits<10> xo1, bit lk, 1302 bits<6> opcode2, bits<2> xo2, 1303 dag OOL, dag IOL, string asmstr, 1304 InstrItinClass itin, list<dag> pattern> 1305 : I2<opcode1, opcode2, OOL, IOL, asmstr, itin> { 1306 bits<5> BO; 1307 bits<5> BI; 1308 bits<2> BH; 1309 1310 bits<5> RST; 1311 bits<19> DS_RA; 1312 1313 let Pattern = pattern; 1314 1315 let Inst{6-10} = BO; 1316 let Inst{11-15} = BI; 1317 let Inst{16-18} = 0; 1318 let Inst{19-20} = BH; 1319 let Inst{21-30} = xo1; 1320 let Inst{31} = lk; 1321 1322 let Inst{38-42} = RST; 1323 let Inst{43-47} = DS_RA{18-14}; // Register # 1324 let Inst{48-61} = DS_RA{13-0}; // Displacement. 1325 let Inst{62-63} = xo2; 1326} 1327 1328class XLForm_2_ext_and_DSForm_1<bits<6> opcode1, bits<10> xo1, 1329 bits<5> bo, bits<5> bi, bit lk, 1330 bits<6> opcode2, bits<2> xo2, 1331 dag OOL, dag IOL, string asmstr, 1332 InstrItinClass itin, list<dag> pattern> 1333 : XLForm_2_and_DSForm_1<opcode1, xo1, lk, opcode2, xo2, 1334 OOL, IOL, asmstr, itin, pattern> { 1335 let BO = bo; 1336 let BI = bi; 1337 let BH = 0; 1338} 1339 1340// 1.7.8 XFX-Form 1341class XFXForm_1<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 1342 InstrItinClass itin> 1343 : I<opcode, OOL, IOL, asmstr, itin> { 1344 bits<5> RT; 1345 bits<10> SPR; 1346 1347 let Inst{6-10} = RT; 1348 let Inst{11} = SPR{4}; 1349 let Inst{12} = SPR{3}; 1350 let Inst{13} = SPR{2}; 1351 let Inst{14} = SPR{1}; 1352 let Inst{15} = SPR{0}; 1353 let Inst{16} = SPR{9}; 1354 let Inst{17} = SPR{8}; 1355 let Inst{18} = SPR{7}; 1356 let Inst{19} = SPR{6}; 1357 let Inst{20} = SPR{5}; 1358 let Inst{21-30} = xo; 1359 let Inst{31} = 0; 1360} 1361 1362class XFXForm_1_ext<bits<6> opcode, bits<10> xo, bits<10> spr, 1363 dag OOL, dag IOL, string asmstr, InstrItinClass itin> 1364 : XFXForm_1<opcode, xo, OOL, IOL, asmstr, itin> { 1365 let SPR = spr; 1366} 1367 1368class XFXForm_3<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 1369 InstrItinClass itin> 1370 : I<opcode, OOL, IOL, asmstr, itin> { 1371 bits<5> RT; 1372 1373 let Inst{6-10} = RT; 1374 let Inst{11-20} = 0; 1375 let Inst{21-30} = xo; 1376 let Inst{31} = 0; 1377} 1378 1379class XFXForm_3p<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 1380 InstrItinClass itin, list<dag> pattern> 1381 : I<opcode, OOL, IOL, asmstr, itin> { 1382 bits<5> RT; 1383 bits<10> Entry; 1384 let Pattern = pattern; 1385 1386 let Inst{6-10} = RT; 1387 let Inst{11-20} = Entry; 1388 let Inst{21-30} = xo; 1389 let Inst{31} = 0; 1390} 1391 1392class XFXForm_5<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 1393 InstrItinClass itin> 1394 : I<opcode, OOL, IOL, asmstr, itin> { 1395 bits<8> FXM; 1396 bits<5> rS; 1397 1398 let Inst{6-10} = rS; 1399 let Inst{11} = 0; 1400 let Inst{12-19} = FXM; 1401 let Inst{20} = 0; 1402 let Inst{21-30} = xo; 1403 let Inst{31} = 0; 1404} 1405 1406class XFXForm_5a<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 1407 InstrItinClass itin> 1408 : I<opcode, OOL, IOL, asmstr, itin> { 1409 bits<5> ST; 1410 bits<8> FXM; 1411 1412 let Inst{6-10} = ST; 1413 let Inst{11} = 1; 1414 let Inst{12-19} = FXM; 1415 let Inst{20} = 0; 1416 let Inst{21-30} = xo; 1417 let Inst{31} = 0; 1418} 1419 1420class XFXForm_7<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 1421 InstrItinClass itin> 1422 : XFXForm_1<opcode, xo, OOL, IOL, asmstr, itin>; 1423 1424class XFXForm_7_ext<bits<6> opcode, bits<10> xo, bits<10> spr, 1425 dag OOL, dag IOL, string asmstr, InstrItinClass itin> 1426 : XFXForm_7<opcode, xo, OOL, IOL, asmstr, itin> { 1427 let SPR = spr; 1428} 1429 1430// XFL-Form - MTFSF 1431// This is probably 1.7.9, but I don't have the reference that uses this 1432// numbering scheme... 1433class XFLForm<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 1434 InstrItinClass itin, list<dag>pattern> 1435 : I<opcode, OOL, IOL, asmstr, itin> { 1436 bits<8> FM; 1437 bits<5> rT; 1438 1439 bit RC = 0; // set by isDOT 1440 let Pattern = pattern; 1441 1442 let Inst{6} = 0; 1443 let Inst{7-14} = FM; 1444 let Inst{15} = 0; 1445 let Inst{16-20} = rT; 1446 let Inst{21-30} = xo; 1447 let Inst{31} = RC; 1448} 1449 1450class XFLForm_1<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 1451 InstrItinClass itin, list<dag>pattern> 1452 : I<opcode, OOL, IOL, asmstr, itin> { 1453 bit L; 1454 bits<8> FLM; 1455 bit W; 1456 bits<5> FRB; 1457 1458 bit RC = 0; // set by isDOT 1459 let Pattern = pattern; 1460 1461 let Inst{6} = L; 1462 let Inst{7-14} = FLM; 1463 let Inst{15} = W; 1464 let Inst{16-20} = FRB; 1465 let Inst{21-30} = xo; 1466 let Inst{31} = RC; 1467} 1468 1469// 1.7.10 XS-Form - SRADI. 1470class XSForm_1<bits<6> opcode, bits<9> xo, dag OOL, dag IOL, string asmstr, 1471 InstrItinClass itin, list<dag> pattern> 1472 : I<opcode, OOL, IOL, asmstr, itin> { 1473 bits<5> A; 1474 bits<5> RS; 1475 bits<6> SH; 1476 1477 bit RC = 0; // set by isDOT 1478 let Pattern = pattern; 1479 1480 let Inst{6-10} = RS; 1481 let Inst{11-15} = A; 1482 let Inst{16-20} = SH{4,3,2,1,0}; 1483 let Inst{21-29} = xo; 1484 let Inst{30} = SH{5}; 1485 let Inst{31} = RC; 1486} 1487 1488// 1.7.11 XO-Form 1489class XOForm_1<bits<6> opcode, bits<9> xo, bit oe, dag OOL, dag IOL, string asmstr, 1490 InstrItinClass itin, list<dag> pattern> 1491 : I<opcode, OOL, IOL, asmstr, itin> { 1492 bits<5> RT; 1493 bits<5> RA; 1494 bits<5> RB; 1495 1496 let Pattern = pattern; 1497 1498 bit RC = 0; // set by isDOT 1499 1500 let Inst{6-10} = RT; 1501 let Inst{11-15} = RA; 1502 let Inst{16-20} = RB; 1503 let Inst{21} = oe; 1504 let Inst{22-30} = xo; 1505 let Inst{31} = RC; 1506} 1507 1508class XOForm_3<bits<6> opcode, bits<9> xo, bit oe, 1509 dag OOL, dag IOL, string asmstr, InstrItinClass itin, list<dag> pattern> 1510 : XOForm_1<opcode, xo, oe, OOL, IOL, asmstr, itin, pattern> { 1511 let RB = 0; 1512} 1513 1514// 1.7.12 A-Form 1515class AForm_1<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, string asmstr, 1516 InstrItinClass itin, list<dag> pattern> 1517 : I<opcode, OOL, IOL, asmstr, itin> { 1518 bits<5> FRT; 1519 bits<5> FRA; 1520 bits<5> FRC; 1521 bits<5> FRB; 1522 1523 let Pattern = pattern; 1524 1525 bit RC = 0; // set by isDOT 1526 1527 let Inst{6-10} = FRT; 1528 let Inst{11-15} = FRA; 1529 let Inst{16-20} = FRB; 1530 let Inst{21-25} = FRC; 1531 let Inst{26-30} = xo; 1532 let Inst{31} = RC; 1533} 1534 1535class AForm_2<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, string asmstr, 1536 InstrItinClass itin, list<dag> pattern> 1537 : AForm_1<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 1538 let FRC = 0; 1539} 1540 1541class AForm_3<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, string asmstr, 1542 InstrItinClass itin, list<dag> pattern> 1543 : AForm_1<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 1544 let FRB = 0; 1545} 1546 1547class AForm_4<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, string asmstr, 1548 InstrItinClass itin, list<dag> pattern> 1549 : I<opcode, OOL, IOL, asmstr, itin> { 1550 bits<5> RT; 1551 bits<5> RA; 1552 bits<5> RB; 1553 bits<5> COND; 1554 1555 let Pattern = pattern; 1556 1557 let Inst{6-10} = RT; 1558 let Inst{11-15} = RA; 1559 let Inst{16-20} = RB; 1560 let Inst{21-25} = COND; 1561 let Inst{26-30} = xo; 1562 let Inst{31} = 0; 1563} 1564 1565// Used for QPX 1566class AForm_4a<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, string asmstr, 1567 InstrItinClass itin, list<dag> pattern> 1568 : AForm_1<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 1569 let FRA = 0; 1570 let FRC = 0; 1571} 1572 1573// 1.7.13 M-Form 1574class MForm_1<bits<6> opcode, dag OOL, dag IOL, string asmstr, 1575 InstrItinClass itin, list<dag> pattern> 1576 : I<opcode, OOL, IOL, asmstr, itin> { 1577 bits<5> RA; 1578 bits<5> RS; 1579 bits<5> RB; 1580 bits<5> MB; 1581 bits<5> ME; 1582 1583 let Pattern = pattern; 1584 1585 bit RC = 0; // set by isDOT 1586 1587 let Inst{6-10} = RS; 1588 let Inst{11-15} = RA; 1589 let Inst{16-20} = RB; 1590 let Inst{21-25} = MB; 1591 let Inst{26-30} = ME; 1592 let Inst{31} = RC; 1593} 1594 1595class MForm_2<bits<6> opcode, dag OOL, dag IOL, string asmstr, 1596 InstrItinClass itin, list<dag> pattern> 1597 : MForm_1<opcode, OOL, IOL, asmstr, itin, pattern> { 1598} 1599 1600// 1.7.14 MD-Form 1601class MDForm_1<bits<6> opcode, bits<3> xo, dag OOL, dag IOL, string asmstr, 1602 InstrItinClass itin, list<dag> pattern> 1603 : I<opcode, OOL, IOL, asmstr, itin> { 1604 bits<5> RA; 1605 bits<5> RS; 1606 bits<6> SH; 1607 bits<6> MBE; 1608 1609 let Pattern = pattern; 1610 1611 bit RC = 0; // set by isDOT 1612 1613 let Inst{6-10} = RS; 1614 let Inst{11-15} = RA; 1615 let Inst{16-20} = SH{4,3,2,1,0}; 1616 let Inst{21-26} = MBE{4,3,2,1,0,5}; 1617 let Inst{27-29} = xo; 1618 let Inst{30} = SH{5}; 1619 let Inst{31} = RC; 1620} 1621 1622class MDSForm_1<bits<6> opcode, bits<4> xo, dag OOL, dag IOL, string asmstr, 1623 InstrItinClass itin, list<dag> pattern> 1624 : I<opcode, OOL, IOL, asmstr, itin> { 1625 bits<5> RA; 1626 bits<5> RS; 1627 bits<5> RB; 1628 bits<6> MBE; 1629 1630 let Pattern = pattern; 1631 1632 bit RC = 0; // set by isDOT 1633 1634 let Inst{6-10} = RS; 1635 let Inst{11-15} = RA; 1636 let Inst{16-20} = RB; 1637 let Inst{21-26} = MBE{4,3,2,1,0,5}; 1638 let Inst{27-30} = xo; 1639 let Inst{31} = RC; 1640} 1641 1642 1643// E-1 VA-Form 1644 1645// VAForm_1 - DACB ordering. 1646class VAForm_1<bits<6> xo, dag OOL, dag IOL, string asmstr, 1647 InstrItinClass itin, list<dag> pattern> 1648 : I<4, OOL, IOL, asmstr, itin> { 1649 bits<5> VD; 1650 bits<5> VA; 1651 bits<5> VC; 1652 bits<5> VB; 1653 1654 let Pattern = pattern; 1655 1656 let Inst{6-10} = VD; 1657 let Inst{11-15} = VA; 1658 let Inst{16-20} = VB; 1659 let Inst{21-25} = VC; 1660 let Inst{26-31} = xo; 1661} 1662 1663// VAForm_1a - DABC ordering. 1664class VAForm_1a<bits<6> xo, dag OOL, dag IOL, string asmstr, 1665 InstrItinClass itin, list<dag> pattern> 1666 : I<4, OOL, IOL, asmstr, itin> { 1667 bits<5> VD; 1668 bits<5> VA; 1669 bits<5> VB; 1670 bits<5> VC; 1671 1672 let Pattern = pattern; 1673 1674 let Inst{6-10} = VD; 1675 let Inst{11-15} = VA; 1676 let Inst{16-20} = VB; 1677 let Inst{21-25} = VC; 1678 let Inst{26-31} = xo; 1679} 1680 1681class VAForm_2<bits<6> xo, dag OOL, dag IOL, string asmstr, 1682 InstrItinClass itin, list<dag> pattern> 1683 : I<4, OOL, IOL, asmstr, itin> { 1684 bits<5> VD; 1685 bits<5> VA; 1686 bits<5> VB; 1687 bits<4> SH; 1688 1689 let Pattern = pattern; 1690 1691 let Inst{6-10} = VD; 1692 let Inst{11-15} = VA; 1693 let Inst{16-20} = VB; 1694 let Inst{21} = 0; 1695 let Inst{22-25} = SH; 1696 let Inst{26-31} = xo; 1697} 1698 1699// E-2 VX-Form 1700class VXForm_1<bits<11> xo, dag OOL, dag IOL, string asmstr, 1701 InstrItinClass itin, list<dag> pattern> 1702 : I<4, OOL, IOL, asmstr, itin> { 1703 bits<5> VD; 1704 bits<5> VA; 1705 bits<5> VB; 1706 1707 let Pattern = pattern; 1708 1709 let Inst{6-10} = VD; 1710 let Inst{11-15} = VA; 1711 let Inst{16-20} = VB; 1712 let Inst{21-31} = xo; 1713} 1714 1715class VXForm_setzero<bits<11> xo, dag OOL, dag IOL, string asmstr, 1716 InstrItinClass itin, list<dag> pattern> 1717 : VXForm_1<xo, OOL, IOL, asmstr, itin, pattern> { 1718 let VA = VD; 1719 let VB = VD; 1720} 1721 1722 1723class VXForm_2<bits<11> xo, dag OOL, dag IOL, string asmstr, 1724 InstrItinClass itin, list<dag> pattern> 1725 : I<4, OOL, IOL, asmstr, itin> { 1726 bits<5> VD; 1727 bits<5> VB; 1728 1729 let Pattern = pattern; 1730 1731 let Inst{6-10} = VD; 1732 let Inst{11-15} = 0; 1733 let Inst{16-20} = VB; 1734 let Inst{21-31} = xo; 1735} 1736 1737class VXForm_3<bits<11> xo, dag OOL, dag IOL, string asmstr, 1738 InstrItinClass itin, list<dag> pattern> 1739 : I<4, OOL, IOL, asmstr, itin> { 1740 bits<5> VD; 1741 bits<5> IMM; 1742 1743 let Pattern = pattern; 1744 1745 let Inst{6-10} = VD; 1746 let Inst{11-15} = IMM; 1747 let Inst{16-20} = 0; 1748 let Inst{21-31} = xo; 1749} 1750 1751/// VXForm_4 - VX instructions with "VD,0,0" register fields, like mfvscr. 1752class VXForm_4<bits<11> xo, dag OOL, dag IOL, string asmstr, 1753 InstrItinClass itin, list<dag> pattern> 1754 : I<4, OOL, IOL, asmstr, itin> { 1755 bits<5> VD; 1756 1757 let Pattern = pattern; 1758 1759 let Inst{6-10} = VD; 1760 let Inst{11-15} = 0; 1761 let Inst{16-20} = 0; 1762 let Inst{21-31} = xo; 1763} 1764 1765/// VXForm_5 - VX instructions with "0,0,VB" register fields, like mtvscr. 1766class VXForm_5<bits<11> xo, dag OOL, dag IOL, string asmstr, 1767 InstrItinClass itin, list<dag> pattern> 1768 : I<4, OOL, IOL, asmstr, itin> { 1769 bits<5> VB; 1770 1771 let Pattern = pattern; 1772 1773 let Inst{6-10} = 0; 1774 let Inst{11-15} = 0; 1775 let Inst{16-20} = VB; 1776 let Inst{21-31} = xo; 1777} 1778 1779// e.g. [PO VRT EO VRB XO] 1780class VXForm_RD5_XO5_RS5<bits<11> xo, bits<5> eo, dag OOL, dag IOL, 1781 string asmstr, InstrItinClass itin, list<dag> pattern> 1782 : I<4, OOL, IOL, asmstr, itin> { 1783 bits<5> RD; 1784 bits<5> VB; 1785 1786 let Pattern = pattern; 1787 1788 let Inst{6-10} = RD; 1789 let Inst{11-15} = eo; 1790 let Inst{16-20} = VB; 1791 let Inst{21-31} = xo; 1792} 1793 1794/// VXForm_CR - VX crypto instructions with "VRT, VRA, ST, SIX" 1795class VXForm_CR<bits<11> xo, dag OOL, dag IOL, string asmstr, 1796 InstrItinClass itin, list<dag> pattern> 1797 : I<4, OOL, IOL, asmstr, itin> { 1798 bits<5> VD; 1799 bits<5> VA; 1800 bits<1> ST; 1801 bits<4> SIX; 1802 1803 let Pattern = pattern; 1804 1805 let Inst{6-10} = VD; 1806 let Inst{11-15} = VA; 1807 let Inst{16} = ST; 1808 let Inst{17-20} = SIX; 1809 let Inst{21-31} = xo; 1810} 1811 1812/// VXForm_BX - VX crypto instructions with "VRT, VRA, 0 - like vsbox" 1813class VXForm_BX<bits<11> xo, dag OOL, dag IOL, string asmstr, 1814 InstrItinClass itin, list<dag> pattern> 1815 : I<4, OOL, IOL, asmstr, itin> { 1816 bits<5> VD; 1817 bits<5> VA; 1818 1819 let Pattern = pattern; 1820 1821 let Inst{6-10} = VD; 1822 let Inst{11-15} = VA; 1823 let Inst{16-20} = 0; 1824 let Inst{21-31} = xo; 1825} 1826 1827// E-4 VXR-Form 1828class VXRForm_1<bits<10> xo, dag OOL, dag IOL, string asmstr, 1829 InstrItinClass itin, list<dag> pattern> 1830 : I<4, OOL, IOL, asmstr, itin> { 1831 bits<5> VD; 1832 bits<5> VA; 1833 bits<5> VB; 1834 bit RC = 0; 1835 1836 let Pattern = pattern; 1837 1838 let Inst{6-10} = VD; 1839 let Inst{11-15} = VA; 1840 let Inst{16-20} = VB; 1841 let Inst{21} = RC; 1842 let Inst{22-31} = xo; 1843} 1844 1845// VX-Form: [PO VRT EO VRB 1 PS XO] 1846class VX_RD5_EO5_RS5_PS1_XO9<bits<5> eo, bits<9> xo, 1847 dag OOL, dag IOL, string asmstr, 1848 InstrItinClass itin, list<dag> pattern> 1849 : I<4, OOL, IOL, asmstr, itin> { 1850 bits<5> VD; 1851 bits<5> VB; 1852 bit PS; 1853 1854 let Pattern = pattern; 1855 1856 let Inst{6-10} = VD; 1857 let Inst{11-15} = eo; 1858 let Inst{16-20} = VB; 1859 let Inst{21} = 1; 1860 let Inst{22} = PS; 1861 let Inst{23-31} = xo; 1862} 1863 1864// VX-Form: [PO VRT VRA VRB 1 PS XO] or [PO VRT VRA VRB 1 / XO] 1865class VX_RD5_RSp5_PS1_XO9<bits<9> xo, dag OOL, dag IOL, string asmstr, 1866 InstrItinClass itin, list<dag> pattern> 1867 : I<4, OOL, IOL, asmstr, itin> { 1868 bits<5> VD; 1869 bits<5> VA; 1870 bits<5> VB; 1871 bit PS; 1872 1873 let Pattern = pattern; 1874 1875 let Inst{6-10} = VD; 1876 let Inst{11-15} = VA; 1877 let Inst{16-20} = VB; 1878 let Inst{21} = 1; 1879 let Inst{22} = PS; 1880 let Inst{23-31} = xo; 1881} 1882 1883// Z23-Form (used by QPX) 1884class Z23Form_1<bits<6> opcode, bits<8> xo, dag OOL, dag IOL, string asmstr, 1885 InstrItinClass itin, list<dag> pattern> 1886 : I<opcode, OOL, IOL, asmstr, itin> { 1887 bits<5> FRT; 1888 bits<5> FRA; 1889 bits<5> FRB; 1890 bits<2> idx; 1891 1892 let Pattern = pattern; 1893 1894 bit RC = 0; // set by isDOT 1895 1896 let Inst{6-10} = FRT; 1897 let Inst{11-15} = FRA; 1898 let Inst{16-20} = FRB; 1899 let Inst{21-22} = idx; 1900 let Inst{23-30} = xo; 1901 let Inst{31} = RC; 1902} 1903 1904class Z23Form_2<bits<6> opcode, bits<8> xo, dag OOL, dag IOL, string asmstr, 1905 InstrItinClass itin, list<dag> pattern> 1906 : Z23Form_1<opcode, xo, OOL, IOL, asmstr, itin, pattern> { 1907 let FRB = 0; 1908} 1909 1910class Z23Form_3<bits<6> opcode, bits<8> xo, dag OOL, dag IOL, string asmstr, 1911 InstrItinClass itin, list<dag> pattern> 1912 : I<opcode, OOL, IOL, asmstr, itin> { 1913 bits<5> FRT; 1914 bits<12> idx; 1915 1916 let Pattern = pattern; 1917 1918 bit RC = 0; // set by isDOT 1919 1920 let Inst{6-10} = FRT; 1921 let Inst{11-22} = idx; 1922 let Inst{23-30} = xo; 1923 let Inst{31} = RC; 1924} 1925 1926//===----------------------------------------------------------------------===// 1927class Pseudo<dag OOL, dag IOL, string asmstr, list<dag> pattern> 1928 : I<0, OOL, IOL, asmstr, NoItinerary> { 1929 let isCodeGenOnly = 1; 1930 let PPC64 = 0; 1931 let Pattern = pattern; 1932 let Inst{31-0} = 0; 1933} 1934