1//===-- XCore.td - Describe the XCore Target Machine -------*- tablegen -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This is the top level entry point for the XCore target. 11// 12//===----------------------------------------------------------------------===// 13 14//===----------------------------------------------------------------------===// 15// Target-independent interfaces which we are implementing 16//===----------------------------------------------------------------------===// 17 18include "llvm/Target/Target.td" 19 20//===----------------------------------------------------------------------===// 21// Descriptions 22//===----------------------------------------------------------------------===// 23 24include "XCoreRegisterInfo.td" 25include "XCoreInstrInfo.td" 26include "XCoreCallingConv.td" 27 28def XCoreInstrInfo : InstrInfo; 29 30//===----------------------------------------------------------------------===// 31// XCore processors supported. 32//===----------------------------------------------------------------------===// 33 34class Proc<string Name, list<SubtargetFeature> Features> 35 : Processor<Name, NoItineraries, Features>; 36 37def : Proc<"generic", []>; 38def : Proc<"xs1b-generic", []>; 39 40//===----------------------------------------------------------------------===// 41// Declare the target which we are implementing 42//===----------------------------------------------------------------------===// 43 44def XCore : Target { 45 // Pull in Instruction Info: 46 let InstructionSet = XCoreInstrInfo; 47} 48