1; RUN: llc -verify-machineinstrs -mtriple=arm64-apple-ios7.0 -disable-fp-elim -o - %s | FileCheck %s 2 3; When generating DAG selection tables, TableGen used to only flag an 4; instruction as needing a chain on its own account if it had a built-in pattern 5; which used the chain. This meant that the AArch64 load/stores weren't 6; recognised and so both loads from %locvar below were coalesced into a single 7; LS8_LDR instruction (same operands other than the non-existent chain) and the 8; increment was lost at return. 9 10; This was obviously a Bad Thing. 11 12declare void @bar(i8*) 13 14define i64 @test_chains() { 15; CHECK-LABEL: test_chains: 16 17 %locvar = alloca i8 18 19 call void @bar(i8* %locvar) 20; CHECK: bl {{_?bar}} 21 22 %inc.1 = load i8, i8* %locvar 23 %inc.2 = zext i8 %inc.1 to i64 24 %inc.3 = add i64 %inc.2, 1 25 %inc.4 = trunc i64 %inc.3 to i8 26 store i8 %inc.4, i8* %locvar 27 28; CHECK: ldurb {{w[0-9]+}}, [x29, [[LOCADDR:#-?[0-9]+]]] 29; CHECK: add {{w[0-9]+}}, {{w[0-9]+}}, #1 30; CHECK: sturb w[[STRVAL:[0-9]+]], [x29, [[LOCADDR]]] 31; CHECK; and w0, w[[STRVAL]], #0xff 32 33 %ret.1 = load i8, i8* %locvar 34 %ret.2 = zext i8 %ret.1 to i64 35 ret i64 %ret.2 36; CHECK: ret 37} 38