1; RUN: llc -march=amdgcn -mcpu=bonaire -verify-machineinstrs -mattr=+load-store-opt < %s | FileCheck -check-prefix=SI %s 2 3@lds = addrspace(3) global [512 x float] undef, align 4 4 5; SI-LABEL: @simple_write2st64_one_val_f32_0_1 6; SI-DAG: buffer_load_dword [[VAL:v[0-9]+]] 7; SI-DAG: v_lshlrev_b32_e32 [[VPTR:v[0-9]+]], 2, v{{[0-9]+}} 8; SI: ds_write2st64_b32 [[VPTR]], [[VAL]], [[VAL]] offset1:1 9; SI: s_endpgm 10define void @simple_write2st64_one_val_f32_0_1(float addrspace(1)* %C, float addrspace(1)* %in) #0 { 11 %x.i = tail call i32 @llvm.amdgcn.workitem.id.x() #1 12 %in.gep = getelementptr float, float addrspace(1)* %in, i32 %x.i 13 %val = load float, float addrspace(1)* %in.gep, align 4 14 %arrayidx0 = getelementptr inbounds [512 x float], [512 x float] addrspace(3)* @lds, i32 0, i32 %x.i 15 store float %val, float addrspace(3)* %arrayidx0, align 4 16 %add.x = add nsw i32 %x.i, 64 17 %arrayidx1 = getelementptr inbounds [512 x float], [512 x float] addrspace(3)* @lds, i32 0, i32 %add.x 18 store float %val, float addrspace(3)* %arrayidx1, align 4 19 ret void 20} 21 22; SI-LABEL: @simple_write2st64_two_val_f32_2_5 23; SI-DAG: buffer_load_dword [[VAL0:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}} 24; SI-DAG: buffer_load_dword [[VAL1:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4 25; SI-DAG: v_lshlrev_b32_e32 [[VPTR:v[0-9]+]], 2, v{{[0-9]+}} 26; SI: ds_write2st64_b32 [[VPTR]], [[VAL0]], [[VAL1]] offset0:2 offset1:5 27; SI: s_endpgm 28define void @simple_write2st64_two_val_f32_2_5(float addrspace(1)* %C, float addrspace(1)* %in) #0 { 29 %x.i = tail call i32 @llvm.amdgcn.workitem.id.x() #1 30 %in.gep.0 = getelementptr float, float addrspace(1)* %in, i32 %x.i 31 %in.gep.1 = getelementptr float, float addrspace(1)* %in.gep.0, i32 1 32 %val0 = load volatile float, float addrspace(1)* %in.gep.0, align 4 33 %val1 = load volatile float, float addrspace(1)* %in.gep.1, align 4 34 %add.x.0 = add nsw i32 %x.i, 128 35 %arrayidx0 = getelementptr inbounds [512 x float], [512 x float] addrspace(3)* @lds, i32 0, i32 %add.x.0 36 store float %val0, float addrspace(3)* %arrayidx0, align 4 37 %add.x.1 = add nsw i32 %x.i, 320 38 %arrayidx1 = getelementptr inbounds [512 x float], [512 x float] addrspace(3)* @lds, i32 0, i32 %add.x.1 39 store float %val1, float addrspace(3)* %arrayidx1, align 4 40 ret void 41} 42 43; SI-LABEL: @simple_write2st64_two_val_max_offset_f32 44; SI-DAG: buffer_load_dword [[VAL0:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}} 45; SI-DAG: buffer_load_dword [[VAL1:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4 46; SI-DAG: v_lshlrev_b32_e32 [[VPTR:v[0-9]+]], 2, v{{[0-9]+}} 47; SI: ds_write2st64_b32 [[VPTR]], [[VAL0]], [[VAL1]] offset1:255 48; SI: s_endpgm 49define void @simple_write2st64_two_val_max_offset_f32(float addrspace(1)* %C, float addrspace(1)* %in, float addrspace(3)* %lds) #0 { 50 %x.i = tail call i32 @llvm.amdgcn.workitem.id.x() #1 51 %in.gep.0 = getelementptr float, float addrspace(1)* %in, i32 %x.i 52 %in.gep.1 = getelementptr float, float addrspace(1)* %in.gep.0, i32 1 53 %val0 = load volatile float, float addrspace(1)* %in.gep.0, align 4 54 %val1 = load volatile float, float addrspace(1)* %in.gep.1, align 4 55 %arrayidx0 = getelementptr inbounds float, float addrspace(3)* %lds, i32 %x.i 56 store float %val0, float addrspace(3)* %arrayidx0, align 4 57 %add.x = add nsw i32 %x.i, 16320 58 %arrayidx1 = getelementptr inbounds float, float addrspace(3)* %lds, i32 %add.x 59 store float %val1, float addrspace(3)* %arrayidx1, align 4 60 ret void 61} 62 63; SI-LABEL: @simple_write2st64_two_val_max_offset_f64 64; SI-DAG: buffer_load_dwordx2 [[VAL0:v\[[0-9]+:[0-9]+\]]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}} 65; SI-DAG: buffer_load_dwordx2 [[VAL1:v\[[0-9]+:[0-9]+\]]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:8 66; SI-DAG: v_add_i32_e32 [[VPTR:v[0-9]+]], 67; SI: ds_write2st64_b64 [[VPTR]], [[VAL0]], [[VAL1]] offset0:4 offset1:127 68; SI: s_endpgm 69define void @simple_write2st64_two_val_max_offset_f64(double addrspace(1)* %C, double addrspace(1)* %in, double addrspace(3)* %lds) #0 { 70 %x.i = tail call i32 @llvm.amdgcn.workitem.id.x() #1 71 %in.gep.0 = getelementptr double, double addrspace(1)* %in, i32 %x.i 72 %in.gep.1 = getelementptr double, double addrspace(1)* %in.gep.0, i32 1 73 %val0 = load volatile double, double addrspace(1)* %in.gep.0, align 8 74 %val1 = load volatile double, double addrspace(1)* %in.gep.1, align 8 75 %add.x.0 = add nsw i32 %x.i, 256 76 %arrayidx0 = getelementptr inbounds double, double addrspace(3)* %lds, i32 %add.x.0 77 store double %val0, double addrspace(3)* %arrayidx0, align 8 78 %add.x.1 = add nsw i32 %x.i, 8128 79 %arrayidx1 = getelementptr inbounds double, double addrspace(3)* %lds, i32 %add.x.1 80 store double %val1, double addrspace(3)* %arrayidx1, align 8 81 ret void 82} 83 84; SI-LABEL: @byte_size_only_divisible_64_write2st64_f64 85; SI-NOT: ds_write2st64_b64 86; SI: ds_write2_b64 {{v[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}} offset1:8 87; SI: s_endpgm 88define void @byte_size_only_divisible_64_write2st64_f64(double addrspace(1)* %C, double addrspace(1)* %in, double addrspace(3)* %lds) #0 { 89 %x.i = tail call i32 @llvm.amdgcn.workitem.id.x() #1 90 %in.gep = getelementptr double, double addrspace(1)* %in, i32 %x.i 91 %val = load double, double addrspace(1)* %in.gep, align 8 92 %arrayidx0 = getelementptr inbounds double, double addrspace(3)* %lds, i32 %x.i 93 store double %val, double addrspace(3)* %arrayidx0, align 8 94 %add.x = add nsw i32 %x.i, 8 95 %arrayidx1 = getelementptr inbounds double, double addrspace(3)* %lds, i32 %add.x 96 store double %val, double addrspace(3)* %arrayidx1, align 8 97 ret void 98} 99 100; Function Attrs: nounwind readnone 101declare i32 @llvm.amdgcn.workitem.id.x() #1 102 103; Function Attrs: nounwind readnone 104declare i32 @llvm.amdgcn.workitem.id.y() #1 105 106attributes #0 = { nounwind } 107attributes #1 = { nounwind readnone } 108attributes #2 = { convergent nounwind } 109