1; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s 2; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s 3; RUN: llc -march=r600 -mcpu=cypress < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s 4 5declare float @llvm.minnum.f32(float, float) #0 6declare <2 x float> @llvm.minnum.v2f32(<2 x float>, <2 x float>) #0 7declare <4 x float> @llvm.minnum.v4f32(<4 x float>, <4 x float>) #0 8declare <8 x float> @llvm.minnum.v8f32(<8 x float>, <8 x float>) #0 9declare <16 x float> @llvm.minnum.v16f32(<16 x float>, <16 x float>) #0 10 11; FUNC-LABEL: @test_fmin_f32 12; SI: v_min_f32_e32 13 14; EG: MEM_RAT_CACHELESS STORE_RAW [[OUT:T[0-9]+\.[XYZW]]] 15; EG: MIN_DX10 {{.*}}[[OUT]] 16define void @test_fmin_f32(float addrspace(1)* %out, float %a, float %b) nounwind { 17 %val = call float @llvm.minnum.f32(float %a, float %b) #0 18 store float %val, float addrspace(1)* %out, align 4 19 ret void 20} 21 22; FUNC-LABEL: @test_fmin_v2f32 23; SI: v_min_f32_e32 24; SI: v_min_f32_e32 25 26; EG: MEM_RAT_CACHELESS STORE_RAW [[OUT:T[0-9]+]] 27; EG: MIN_DX10 {{.*}}[[OUT]] 28; EG: MIN_DX10 {{.*}}[[OUT]] 29define void @test_fmin_v2f32(<2 x float> addrspace(1)* %out, <2 x float> %a, <2 x float> %b) nounwind { 30 %val = call <2 x float> @llvm.minnum.v2f32(<2 x float> %a, <2 x float> %b) #0 31 store <2 x float> %val, <2 x float> addrspace(1)* %out, align 8 32 ret void 33} 34 35; FUNC-LABEL: @test_fmin_v4f32 36; SI: v_min_f32_e32 37; SI: v_min_f32_e32 38; SI: v_min_f32_e32 39; SI: v_min_f32_e32 40 41; EG: MEM_RAT_CACHELESS STORE_RAW [[OUT:T[0-9]+]] 42; EG: MIN_DX10 {{.*}}[[OUT]] 43; EG: MIN_DX10 {{.*}}[[OUT]] 44; EG: MIN_DX10 {{.*}}[[OUT]] 45; EG: MIN_DX10 {{.*}}[[OUT]] 46define void @test_fmin_v4f32(<4 x float> addrspace(1)* %out, <4 x float> %a, <4 x float> %b) nounwind { 47 %val = call <4 x float> @llvm.minnum.v4f32(<4 x float> %a, <4 x float> %b) #0 48 store <4 x float> %val, <4 x float> addrspace(1)* %out, align 16 49 ret void 50} 51 52; FUNC-LABEL: @test_fmin_v8f32 53; SI: v_min_f32_e32 54; SI: v_min_f32_e32 55; SI: v_min_f32_e32 56; SI: v_min_f32_e32 57; SI: v_min_f32_e32 58; SI: v_min_f32_e32 59; SI: v_min_f32_e32 60; SI: v_min_f32_e32 61 62; EG: MEM_RAT_CACHELESS STORE_RAW [[OUT1:T[0-9]+]] 63; EG: MEM_RAT_CACHELESS STORE_RAW [[OUT2:T[0-9]+]] 64; EG-DAG: MIN_DX10 {{.*}}[[OUT1]].X 65; EG-DAG: MIN_DX10 {{.*}}[[OUT1]].Y 66; EG-DAG: MIN_DX10 {{.*}}[[OUT1]].Z 67; EG-DAG: MIN_DX10 {{.*}}[[OUT1]].W 68; EG-DAG: MIN_DX10 {{.*}}[[OUT2]].X 69; EG-DAG: MIN_DX10 {{.*}}[[OUT2]].Y 70; EG-DAG: MIN_DX10 {{.*}}[[OUT2]].Z 71; EG-DAG: MIN_DX10 {{.*}}[[OUT2]].W 72define void @test_fmin_v8f32(<8 x float> addrspace(1)* %out, <8 x float> %a, <8 x float> %b) nounwind { 73 %val = call <8 x float> @llvm.minnum.v8f32(<8 x float> %a, <8 x float> %b) #0 74 store <8 x float> %val, <8 x float> addrspace(1)* %out, align 32 75 ret void 76} 77 78; FUNC-LABEL: @test_fmin_v16f32 79; SI: v_min_f32_e32 80; SI: v_min_f32_e32 81; SI: v_min_f32_e32 82; SI: v_min_f32_e32 83; SI: v_min_f32_e32 84; SI: v_min_f32_e32 85; SI: v_min_f32_e32 86; SI: v_min_f32_e32 87; SI: v_min_f32_e32 88; SI: v_min_f32_e32 89; SI: v_min_f32_e32 90; SI: v_min_f32_e32 91; SI: v_min_f32_e32 92; SI: v_min_f32_e32 93; SI: v_min_f32_e32 94; SI: v_min_f32_e32 95 96; EG: MEM_RAT_CACHELESS STORE_RAW [[OUT1:T[0-9]+]] 97; EG: MEM_RAT_CACHELESS STORE_RAW [[OUT2:T[0-9]+]] 98; EG: MEM_RAT_CACHELESS STORE_RAW [[OUT3:T[0-9]+]] 99; EG: MEM_RAT_CACHELESS STORE_RAW [[OUT4:T[0-9]+]] 100; EG-DAG: MIN_DX10 {{.*}}[[OUT1]].X 101; EG-DAG: MIN_DX10 {{.*}}[[OUT1]].Y 102; EG-DAG: MIN_DX10 {{.*}}[[OUT1]].Z 103; EG-DAG: MIN_DX10 {{.*}}[[OUT1]].W 104; EG-DAG: MIN_DX10 {{.*}}[[OUT2]].X 105; EG-DAG: MIN_DX10 {{.*}}[[OUT2]].Y 106; EG-DAG: MIN_DX10 {{.*}}[[OUT2]].Z 107; EG-DAG: MIN_DX10 {{.*}}[[OUT2]].W 108; EG-DAG: MIN_DX10 {{.*}}[[OUT3]].X 109; EG-DAG: MIN_DX10 {{.*}}[[OUT3]].Y 110; EG-DAG: MIN_DX10 {{.*}}[[OUT3]].Z 111; EG-DAG: MIN_DX10 {{.*}}[[OUT3]].W 112; EG-DAG: MIN_DX10 {{.*}}[[OUT4]].X 113; EG-DAG: MIN_DX10 {{.*}}[[OUT4]].Y 114; EG-DAG: MIN_DX10 {{.*}}[[OUT4]].Z 115; EG-DAG: MIN_DX10 {{.*}}[[OUT4]].W 116define void @test_fmin_v16f32(<16 x float> addrspace(1)* %out, <16 x float> %a, <16 x float> %b) nounwind { 117 %val = call <16 x float> @llvm.minnum.v16f32(<16 x float> %a, <16 x float> %b) #0 118 store <16 x float> %val, <16 x float> addrspace(1)* %out, align 64 119 ret void 120} 121 122; FUNC-LABEL: @constant_fold_fmin_f32 123; SI-NOT: v_min_f32_e32 124; SI: v_mov_b32_e32 [[REG:v[0-9]+]], 1.0 125; SI: buffer_store_dword [[REG]] 126 127; EG: MEM_RAT_CACHELESS STORE_RAW [[OUT:T[0-9]+\.[XYZW]]] 128; EG-NOT: MIN_DX10 129; EG: MOV {{.*}}[[OUT]], literal.{{[xy]}} 130define void @constant_fold_fmin_f32(float addrspace(1)* %out) nounwind { 131 %val = call float @llvm.minnum.f32(float 1.0, float 2.0) #0 132 store float %val, float addrspace(1)* %out, align 4 133 ret void 134} 135 136; FUNC-LABEL: @constant_fold_fmin_f32_nan_nan 137; SI-NOT: v_min_f32_e32 138; SI: v_mov_b32_e32 [[REG:v[0-9]+]], 0x7fc00000 139; SI: buffer_store_dword [[REG]] 140 141; EG: MEM_RAT_CACHELESS STORE_RAW [[OUT:T[0-9]+\.[XYZW]]] 142; EG-NOT: MIN_DX10 143; EG: MOV {{.*}}[[OUT]], literal.{{[xy]}} 144; EG: 2143289344({{nan|1\.#QNAN0e\+00}}) 145define void @constant_fold_fmin_f32_nan_nan(float addrspace(1)* %out) nounwind { 146 %val = call float @llvm.minnum.f32(float 0x7FF8000000000000, float 0x7FF8000000000000) #0 147 store float %val, float addrspace(1)* %out, align 4 148 ret void 149} 150 151; FUNC-LABEL: @constant_fold_fmin_f32_val_nan 152; SI-NOT: v_min_f32_e32 153; SI: v_mov_b32_e32 [[REG:v[0-9]+]], 1.0 154; SI: buffer_store_dword [[REG]] 155 156; EG: MEM_RAT_CACHELESS STORE_RAW [[OUT:T[0-9]+\.[XYZW]]] 157; EG-NOT: MIN_DX10 158; EG: MOV {{.*}}[[OUT]], literal.{{[xy]}} 159define void @constant_fold_fmin_f32_val_nan(float addrspace(1)* %out) nounwind { 160 %val = call float @llvm.minnum.f32(float 1.0, float 0x7FF8000000000000) #0 161 store float %val, float addrspace(1)* %out, align 4 162 ret void 163} 164 165; FUNC-LABEL: @constant_fold_fmin_f32_nan_val 166; SI-NOT: v_min_f32_e32 167; SI: v_mov_b32_e32 [[REG:v[0-9]+]], 1.0 168; SI: buffer_store_dword [[REG]] 169 170; EG: MEM_RAT_CACHELESS STORE_RAW [[OUT:T[0-9]+\.[XYZW]]] 171; EG-NOT: MIN_DX10 172; EG: MOV {{.*}}[[OUT]], literal.{{[xy]}} 173define void @constant_fold_fmin_f32_nan_val(float addrspace(1)* %out) nounwind { 174 %val = call float @llvm.minnum.f32(float 0x7FF8000000000000, float 1.0) #0 175 store float %val, float addrspace(1)* %out, align 4 176 ret void 177} 178 179; FUNC-LABEL: @constant_fold_fmin_f32_p0_p0 180; SI-NOT: v_min_f32_e32 181; SI: v_mov_b32_e32 [[REG:v[0-9]+]], 0 182; SI: buffer_store_dword [[REG]] 183 184; EG: MEM_RAT_CACHELESS STORE_RAW [[OUT:T[0-9]+\.[XYZW]]] 185; EG-NOT: MIN_DX10 186; EG: MOV {{.*}}[[OUT]], literal.{{[xy]}} 187define void @constant_fold_fmin_f32_p0_p0(float addrspace(1)* %out) nounwind { 188 %val = call float @llvm.minnum.f32(float 0.0, float 0.0) #0 189 store float %val, float addrspace(1)* %out, align 4 190 ret void 191} 192 193; FUNC-LABEL: @constant_fold_fmin_f32_p0_n0 194; SI-NOT: v_min_f32_e32 195; SI: v_mov_b32_e32 [[REG:v[0-9]+]], 0 196; SI: buffer_store_dword [[REG]] 197 198; EG: MEM_RAT_CACHELESS STORE_RAW [[OUT:T[0-9]+\.[XYZW]]] 199; EG-NOT: MIN_DX10 200; EG: MOV {{.*}}[[OUT]], literal.{{[xy]}} 201define void @constant_fold_fmin_f32_p0_n0(float addrspace(1)* %out) nounwind { 202 %val = call float @llvm.minnum.f32(float 0.0, float -0.0) #0 203 store float %val, float addrspace(1)* %out, align 4 204 ret void 205} 206 207; FUNC-LABEL: @constant_fold_fmin_f32_n0_p0 208; SI-NOT: v_min_f32_e32 209; SI: v_bfrev_b32_e32 [[REG:v[0-9]+]], 1{{$}} 210; SI: buffer_store_dword [[REG]] 211 212; EG: MEM_RAT_CACHELESS STORE_RAW [[OUT:T[0-9]+\.[XYZW]]] 213; EG-NOT: MIN_DX10 214; EG: MOV {{.*}}[[OUT]], literal.{{[xy]}} 215define void @constant_fold_fmin_f32_n0_p0(float addrspace(1)* %out) nounwind { 216 %val = call float @llvm.minnum.f32(float -0.0, float 0.0) #0 217 store float %val, float addrspace(1)* %out, align 4 218 ret void 219} 220 221; FUNC-LABEL: @constant_fold_fmin_f32_n0_n0 222; SI-NOT: v_min_f32_e32 223; SI: v_bfrev_b32_e32 [[REG:v[0-9]+]], 1{{$}} 224; SI: buffer_store_dword [[REG]] 225 226; EG: MEM_RAT_CACHELESS STORE_RAW [[OUT:T[0-9]+\.[XYZW]]] 227; EG-NOT: MIN_DX10 228; EG: MOV {{.*}}[[OUT]], literal.{{[xy]}} 229define void @constant_fold_fmin_f32_n0_n0(float addrspace(1)* %out) nounwind { 230 %val = call float @llvm.minnum.f32(float -0.0, float -0.0) #0 231 store float %val, float addrspace(1)* %out, align 4 232 ret void 233} 234 235; FUNC-LABEL: @fmin_var_immediate_f32 236; SI: v_min_f32_e64 {{v[0-9]+}}, 2.0, {{s[0-9]+}} 237 238; EG: MEM_RAT_CACHELESS STORE_RAW [[OUT:T[0-9]+\.[XYZW]]] 239; EG: MIN_DX10 {{.*}}[[OUT]], {{KC0\[[0-9]\].[XYZW]}}, literal.{{[xy]}} 240define void @fmin_var_immediate_f32(float addrspace(1)* %out, float %a) nounwind { 241 %val = call float @llvm.minnum.f32(float %a, float 2.0) #0 242 store float %val, float addrspace(1)* %out, align 4 243 ret void 244} 245 246; FUNC-LABEL: @fmin_immediate_var_f32 247; SI: v_min_f32_e64 {{v[0-9]+}}, 2.0, {{s[0-9]+}} 248 249; EG: MEM_RAT_CACHELESS STORE_RAW [[OUT:T[0-9]+\.[XYZW]]] 250; EG: MIN_DX10 {{.*}}[[OUT]], {{KC0\[[0-9]\].[XYZW]}}, literal.{{[xy]}} 251define void @fmin_immediate_var_f32(float addrspace(1)* %out, float %a) nounwind { 252 %val = call float @llvm.minnum.f32(float 2.0, float %a) #0 253 store float %val, float addrspace(1)* %out, align 4 254 ret void 255} 256 257; FUNC-LABEL: @fmin_var_literal_f32 258; SI: v_mov_b32_e32 [[REG:v[0-9]+]], 0x42c60000 259; SI: v_min_f32_e32 {{v[0-9]+}}, {{s[0-9]+}}, [[REG]] 260 261; EG: MEM_RAT_CACHELESS STORE_RAW [[OUT:T[0-9]+\.[XYZW]]] 262; EG: MIN_DX10 {{.*}}[[OUT]], {{KC0\[[0-9]\].[XYZW]}}, literal.{{[xy]}} 263define void @fmin_var_literal_f32(float addrspace(1)* %out, float %a) nounwind { 264 %val = call float @llvm.minnum.f32(float %a, float 99.0) #0 265 store float %val, float addrspace(1)* %out, align 4 266 ret void 267} 268 269; FUNC-LABEL: @fmin_literal_var_f32 270; SI: v_mov_b32_e32 [[REG:v[0-9]+]], 0x42c60000 271; SI: v_min_f32_e32 {{v[0-9]+}}, {{s[0-9]+}}, [[REG]] 272 273; EG: MEM_RAT_CACHELESS STORE_RAW [[OUT:T[0-9]+\.[XYZW]]] 274; EG: MIN_DX10 {{.*}}[[OUT]], {{KC0\[[0-9]\].[XYZW]}}, literal.{{[xy]}} 275define void @fmin_literal_var_f32(float addrspace(1)* %out, float %a) nounwind { 276 %val = call float @llvm.minnum.f32(float 99.0, float %a) #0 277 store float %val, float addrspace(1)* %out, align 4 278 ret void 279} 280 281attributes #0 = { nounwind readnone } 282