1; RUN: llc < %s -O0 -fast-isel-abort=1 -verify-machineinstrs -relocation-model=dynamic-no-pic -mtriple=armv7-apple-ios | FileCheck %s --check-prefix=ARM 2; RUN: llc < %s -O0 -fast-isel-abort=1 -verify-machineinstrs -relocation-model=dynamic-no-pic -mtriple=armv7-linux-gnueabi | FileCheck %s --check-prefix=ARM 3; RUN: llc < %s -O0 -fast-isel-abort=1 -verify-machineinstrs -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-ios | FileCheck %s --check-prefix=THUMB 4 5; Test add with non-legal types 6 7define void @add_i1(i1 %a, i1 %b) nounwind ssp { 8entry: 9; ARM: add_i1 10; THUMB: add_i1 11 %a.addr = alloca i1, align 4 12 %0 = add i1 %a, %b 13; ARM: add r0, r0, r1 14; THUMB: add r0, r1 15 store i1 %0, i1* %a.addr, align 4 16 ret void 17} 18 19define void @add_i8(i8 %a, i8 %b) nounwind ssp { 20entry: 21; ARM: add_i8 22; THUMB: add_i8 23 %a.addr = alloca i8, align 4 24 %0 = add i8 %a, %b 25; ARM: add r0, r0, r1 26; THUMB: add r0, r1 27 store i8 %0, i8* %a.addr, align 4 28 ret void 29} 30 31define void @add_i16(i16 %a, i16 %b) nounwind ssp { 32entry: 33; ARM: add_i16 34; THUMB: add_i16 35 %a.addr = alloca i16, align 4 36 %0 = add i16 %a, %b 37; ARM: add r0, r0, r1 38; THUMB: add r0, r1 39 store i16 %0, i16* %a.addr, align 4 40 ret void 41} 42 43; Test or with non-legal types 44 45define void @or_i1(i1 %a, i1 %b) nounwind ssp { 46entry: 47; ARM: or_i1 48; THUMB: or_i1 49 %a.addr = alloca i1, align 4 50 %0 = or i1 %a, %b 51; ARM: orr r0, r0, r1 52; THUMB: orrs r0, r1 53 store i1 %0, i1* %a.addr, align 4 54 ret void 55} 56 57define void @or_i8(i8 %a, i8 %b) nounwind ssp { 58entry: 59; ARM: or_i8 60; THUMB: or_i8 61 %a.addr = alloca i8, align 4 62 %0 = or i8 %a, %b 63; ARM: orr r0, r0, r1 64; THUMB: orrs r0, r1 65 store i8 %0, i8* %a.addr, align 4 66 ret void 67} 68 69define void @or_i16(i16 %a, i16 %b) nounwind ssp { 70entry: 71; ARM: or_i16 72; THUMB: or_i16 73 %a.addr = alloca i16, align 4 74 %0 = or i16 %a, %b 75; ARM: orr r0, r0, r1 76; THUMB: orrs r0, r1 77 store i16 %0, i16* %a.addr, align 4 78 ret void 79} 80 81; Test sub with non-legal types 82 83define void @sub_i1(i1 %a, i1 %b) nounwind ssp { 84entry: 85; ARM: sub_i1 86; THUMB: sub_i1 87 %a.addr = alloca i1, align 4 88 %0 = sub i1 %a, %b 89; ARM: sub r0, r0, r1 90; THUMB: subs r0, r0, r1 91 store i1 %0, i1* %a.addr, align 4 92 ret void 93} 94 95define void @sub_i8(i8 %a, i8 %b) nounwind ssp { 96entry: 97; ARM: sub_i8 98; THUMB: sub_i8 99 %a.addr = alloca i8, align 4 100 %0 = sub i8 %a, %b 101; ARM: sub r0, r0, r1 102; THUMB: subs r0, r0, r1 103 store i8 %0, i8* %a.addr, align 4 104 ret void 105} 106 107define void @sub_i16(i16 %a, i16 %b) nounwind ssp { 108entry: 109; ARM: sub_i16 110; THUMB: sub_i16 111 %a.addr = alloca i16, align 4 112 %0 = sub i16 %a, %b 113; ARM: sub r0, r0, r1 114; THUMB: subs r0, r0, r1 115 store i16 %0, i16* %a.addr, align 4 116 ret void 117} 118