1; RUN: llc -mattr=+fp16 < %s | FileCheck %s 2 3target datalayout = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64" 4target triple = "armv7a--none-eabi" 5 6; CHECK-LABEL: test_vec3: 7; CHECK-DAG: vcvtb.f32.f16 [[SREG1:s[0-9]+]], 8; CHECK-DAG: vcvt.f32.s32 [[SREG2:s[0-9]+]], 9; CHECK-DAG: vcvtb.f16.f32 [[SREG3:s[0-9]+]], [[SREG2]] 10; CHECK-DAG: vcvtb.f32.f16 [[SREG4:s[0-9]+]], [[SREG3]] 11; CHECK: vadd.f32 [[SREG5:s[0-9]+]], [[SREG4]], [[SREG1]] 12; CHECK-NEXT: vcvtb.f16.f32 [[SREG6:s[0-9]+]], [[SREG5]] 13; CHECK-NEXT: vmov [[RREG1:r[0-9]+]], [[SREG6]] 14; CHECK-NEXT: uxth [[RREG2:r[0-9]+]], [[RREG1]] 15; CHECK-NEXT: pkhbt [[RREG3:r[0-9]+]], [[RREG1]], [[RREG1]], lsl #16 16; CHECK-DAG: strh [[RREG1]], [r0, #4] 17; CHECK-DAG: vmov [[DREG:d[0-9]+]], [[RREG3]], [[RREG2]] 18; CHECK-DAG: vst1.32 {[[DREG]][0]}, [r0:32] 19; CHECK-NEXT: bx lr 20define void @test_vec3(<3 x half>* %arr, i32 %i) #0 { 21 %H = sitofp i32 %i to half 22 %S = fadd half %H, 0xH4A00 23 %1 = insertelement <3 x half> undef, half %S, i32 0 24 %2 = insertelement <3 x half> %1, half %S, i32 1 25 %3 = insertelement <3 x half> %2, half %S, i32 2 26 store <3 x half> %3, <3 x half>* %arr, align 8 27 ret void 28} 29 30; CHECK-LABEL: test_bitcast: 31; CHECK: vcvtb.f16.f32 32; CHECK: vcvtb.f16.f32 33; CHECK: vcvtb.f16.f32 34; CHECK: pkhbt 35; CHECK: uxth 36define void @test_bitcast(<3 x half> %inp, <3 x i16>* %arr) #0 { 37 %bc = bitcast <3 x half> %inp to <3 x i16> 38 store <3 x i16> %bc, <3 x i16>* %arr, align 8 39 ret void 40} 41 42attributes #0 = { nounwind } 43