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1; RUN: llc < %s -mtriple=armv7 -mattr=+db | FileCheck %s
2; RUN: llc < %s -mtriple=thumbv7 -mattr=+db | FileCheck %s
3
4; CHECK-LABEL: test
5define void @test() {
6  call void @llvm.arm.dmb(i32 3)     ; CHECK: dmb osh
7  call void @llvm.arm.dsb(i32 7)     ; CHECK: dsb nsh
8  call void @llvm.arm.isb(i32 15)    ; CHECK: isb sy
9  ret void
10}
11
12; Important point is that the compiler should not reorder memory access
13; instructions around DMB.
14; Failure to do so, two STRs will collapse into one STRD.
15; CHECK-LABEL: test_dmb_reordering
16define void @test_dmb_reordering(i32 %a, i32 %b, i32* %d) {
17  store i32 %a, i32* %d              ; CHECK: str {{r[0-9]+}}, [{{r[0-9]+}}]
18
19  call void @llvm.arm.dmb(i32 15)    ; CHECK: dmb sy
20
21  %d1 = getelementptr i32, i32* %d, i32 1
22  store i32 %b, i32* %d1             ; CHECK: str {{r[0-9]+}}, [{{r[0-9]+}}, #4]
23
24  ret void
25}
26
27; Similarly for DSB.
28; CHECK-LABEL: test_dsb_reordering
29define void @test_dsb_reordering(i32 %a, i32 %b, i32* %d) {
30  store i32 %a, i32* %d              ; CHECK: str {{r[0-9]+}}, [{{r[0-9]+}}]
31
32  call void @llvm.arm.dsb(i32 15)    ; CHECK: dsb sy
33
34  %d1 = getelementptr i32, i32* %d, i32 1
35  store i32 %b, i32* %d1             ; CHECK: str {{r[0-9]+}}, [{{r[0-9]+}}, #4]
36
37  ret void
38}
39
40; And ISB.
41; CHECK-LABEL: test_isb_reordering
42define void @test_isb_reordering(i32 %a, i32 %b, i32* %d) {
43  store i32 %a, i32* %d              ; CHECK: str {{r[0-9]+}}, [{{r[0-9]+}}]
44
45  call void @llvm.arm.isb(i32 15)    ; CHECK: isb sy
46
47  %d1 = getelementptr i32, i32* %d, i32 1
48  store i32 %b, i32* %d1             ; CHECK: str {{r[0-9]+}}, [{{r[0-9]+}}, #4]
49
50  ret void
51}
52
53declare void @llvm.arm.dmb(i32)
54declare void @llvm.arm.dsb(i32)
55declare void @llvm.arm.isb(i32)
56