1; RUN: llc -mtriple=arm-eabi -mattr=+neon %s -o - | FileCheck %s 2 3define <8 x i8> @vhsubs8(<8 x i8>* %A, <8 x i8>* %B) nounwind { 4;CHECK-LABEL: vhsubs8: 5;CHECK: vhsub.s8 6 %tmp1 = load <8 x i8>, <8 x i8>* %A 7 %tmp2 = load <8 x i8>, <8 x i8>* %B 8 %tmp3 = call <8 x i8> @llvm.arm.neon.vhsubs.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2) 9 ret <8 x i8> %tmp3 10} 11 12define <4 x i16> @vhsubs16(<4 x i16>* %A, <4 x i16>* %B) nounwind { 13;CHECK-LABEL: vhsubs16: 14;CHECK: vhsub.s16 15 %tmp1 = load <4 x i16>, <4 x i16>* %A 16 %tmp2 = load <4 x i16>, <4 x i16>* %B 17 %tmp3 = call <4 x i16> @llvm.arm.neon.vhsubs.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2) 18 ret <4 x i16> %tmp3 19} 20 21define <2 x i32> @vhsubs32(<2 x i32>* %A, <2 x i32>* %B) nounwind { 22;CHECK-LABEL: vhsubs32: 23;CHECK: vhsub.s32 24 %tmp1 = load <2 x i32>, <2 x i32>* %A 25 %tmp2 = load <2 x i32>, <2 x i32>* %B 26 %tmp3 = call <2 x i32> @llvm.arm.neon.vhsubs.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2) 27 ret <2 x i32> %tmp3 28} 29 30define <8 x i8> @vhsubu8(<8 x i8>* %A, <8 x i8>* %B) nounwind { 31;CHECK-LABEL: vhsubu8: 32;CHECK: vhsub.u8 33 %tmp1 = load <8 x i8>, <8 x i8>* %A 34 %tmp2 = load <8 x i8>, <8 x i8>* %B 35 %tmp3 = call <8 x i8> @llvm.arm.neon.vhsubu.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2) 36 ret <8 x i8> %tmp3 37} 38 39define <4 x i16> @vhsubu16(<4 x i16>* %A, <4 x i16>* %B) nounwind { 40;CHECK-LABEL: vhsubu16: 41;CHECK: vhsub.u16 42 %tmp1 = load <4 x i16>, <4 x i16>* %A 43 %tmp2 = load <4 x i16>, <4 x i16>* %B 44 %tmp3 = call <4 x i16> @llvm.arm.neon.vhsubu.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2) 45 ret <4 x i16> %tmp3 46} 47 48define <2 x i32> @vhsubu32(<2 x i32>* %A, <2 x i32>* %B) nounwind { 49;CHECK-LABEL: vhsubu32: 50;CHECK: vhsub.u32 51 %tmp1 = load <2 x i32>, <2 x i32>* %A 52 %tmp2 = load <2 x i32>, <2 x i32>* %B 53 %tmp3 = call <2 x i32> @llvm.arm.neon.vhsubu.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2) 54 ret <2 x i32> %tmp3 55} 56 57define <16 x i8> @vhsubQs8(<16 x i8>* %A, <16 x i8>* %B) nounwind { 58;CHECK-LABEL: vhsubQs8: 59;CHECK: vhsub.s8 60 %tmp1 = load <16 x i8>, <16 x i8>* %A 61 %tmp2 = load <16 x i8>, <16 x i8>* %B 62 %tmp3 = call <16 x i8> @llvm.arm.neon.vhsubs.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2) 63 ret <16 x i8> %tmp3 64} 65 66define <8 x i16> @vhsubQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind { 67;CHECK-LABEL: vhsubQs16: 68;CHECK: vhsub.s16 69 %tmp1 = load <8 x i16>, <8 x i16>* %A 70 %tmp2 = load <8 x i16>, <8 x i16>* %B 71 %tmp3 = call <8 x i16> @llvm.arm.neon.vhsubs.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2) 72 ret <8 x i16> %tmp3 73} 74 75define <4 x i32> @vhsubQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind { 76;CHECK-LABEL: vhsubQs32: 77;CHECK: vhsub.s32 78 %tmp1 = load <4 x i32>, <4 x i32>* %A 79 %tmp2 = load <4 x i32>, <4 x i32>* %B 80 %tmp3 = call <4 x i32> @llvm.arm.neon.vhsubs.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2) 81 ret <4 x i32> %tmp3 82} 83 84define <16 x i8> @vhsubQu8(<16 x i8>* %A, <16 x i8>* %B) nounwind { 85;CHECK-LABEL: vhsubQu8: 86;CHECK: vhsub.u8 87 %tmp1 = load <16 x i8>, <16 x i8>* %A 88 %tmp2 = load <16 x i8>, <16 x i8>* %B 89 %tmp3 = call <16 x i8> @llvm.arm.neon.vhsubu.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2) 90 ret <16 x i8> %tmp3 91} 92 93define <8 x i16> @vhsubQu16(<8 x i16>* %A, <8 x i16>* %B) nounwind { 94;CHECK-LABEL: vhsubQu16: 95;CHECK: vhsub.u16 96 %tmp1 = load <8 x i16>, <8 x i16>* %A 97 %tmp2 = load <8 x i16>, <8 x i16>* %B 98 %tmp3 = call <8 x i16> @llvm.arm.neon.vhsubu.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2) 99 ret <8 x i16> %tmp3 100} 101 102define <4 x i32> @vhsubQu32(<4 x i32>* %A, <4 x i32>* %B) nounwind { 103;CHECK-LABEL: vhsubQu32: 104;CHECK: vhsub.u32 105 %tmp1 = load <4 x i32>, <4 x i32>* %A 106 %tmp2 = load <4 x i32>, <4 x i32>* %B 107 %tmp3 = call <4 x i32> @llvm.arm.neon.vhsubu.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2) 108 ret <4 x i32> %tmp3 109} 110 111declare <8 x i8> @llvm.arm.neon.vhsubs.v8i8(<8 x i8>, <8 x i8>) nounwind readnone 112declare <4 x i16> @llvm.arm.neon.vhsubs.v4i16(<4 x i16>, <4 x i16>) nounwind readnone 113declare <2 x i32> @llvm.arm.neon.vhsubs.v2i32(<2 x i32>, <2 x i32>) nounwind readnone 114 115declare <8 x i8> @llvm.arm.neon.vhsubu.v8i8(<8 x i8>, <8 x i8>) nounwind readnone 116declare <4 x i16> @llvm.arm.neon.vhsubu.v4i16(<4 x i16>, <4 x i16>) nounwind readnone 117declare <2 x i32> @llvm.arm.neon.vhsubu.v2i32(<2 x i32>, <2 x i32>) nounwind readnone 118 119declare <16 x i8> @llvm.arm.neon.vhsubs.v16i8(<16 x i8>, <16 x i8>) nounwind readnone 120declare <8 x i16> @llvm.arm.neon.vhsubs.v8i16(<8 x i16>, <8 x i16>) nounwind readnone 121declare <4 x i32> @llvm.arm.neon.vhsubs.v4i32(<4 x i32>, <4 x i32>) nounwind readnone 122 123declare <16 x i8> @llvm.arm.neon.vhsubu.v16i8(<16 x i8>, <16 x i8>) nounwind readnone 124declare <8 x i16> @llvm.arm.neon.vhsubu.v8i16(<8 x i16>, <8 x i16>) nounwind readnone 125declare <4 x i32> @llvm.arm.neon.vhsubu.v4i32(<4 x i32>, <4 x i32>) nounwind readnone 126