1; RUN: llc -mtriple=armv8 -mcpu=cyclone < %s | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-NOTSWIFT 2; RUN: llc -mtriple=armv8 -mcpu=swift < %s | FileCheck %s 3; RUN: llc -mtriple=armv8 -mcpu=cortex-a57 < %s | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-NOTSWIFT 4 5declare arm_aapcs_vfpcc void @take_vec64(<2 x i32>) 6 7define void @test_vec64() { 8; CHECK-LABEL: test_vec64: 9 10 call arm_aapcs_vfpcc void @take_vec64(<2 x i32> <i32 0, i32 0>) 11 call arm_aapcs_vfpcc void @take_vec64(<2 x i32> <i32 0, i32 0>) 12; CHECK-NOTSWIFT-NOT: vmov.f64 d0, 13; CHECK: vmov.i32 d0, #0 14; CHECK: bl 15; CHECK: vmov.i32 d0, #0 16; CHECK: bl 17 18 ret void 19} 20 21declare arm_aapcs_vfpcc void @take_vec128(<8 x i16>) 22 23define void @test_vec128() { 24; CHECK-LABEL: test_vec128: 25 26 call arm_aapcs_vfpcc void @take_vec128(<8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>) 27 call arm_aapcs_vfpcc void @take_vec128(<8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>) 28; CHECK-NOT: vmov.f64 [[ZEROREG:d[0-9]+]], 29; CHECK: vmov.i32 q0, #0 30; CHECK: bl 31; CHECK: vmov.i32 q0, #0 32; CHECK: bl 33 34 ret void 35} 36 37declare void @take_i32(i32) 38 39define void @test_i32() { 40; CHECK-LABEL: test_i32: 41 42 call arm_aapcs_vfpcc void @take_i32(i32 0) 43 call arm_aapcs_vfpcc void @take_i32(i32 0) 44; CHECK-NOTSWIFT-NOT: vmov.f64 [[ZEROREG:d[0-9]+]], 45; CHECK: mov r0, #0 46; CHECK: bl 47; CHECK: mov r0, #0 48; CHECK: bl 49 50; It doesn't particularly matter what Swift does here, there isn't carefully 51; crafted behaviour that we might break in Cyclone. 52 53 ret void 54} 55