1; RUN: llc -march=hexagon -mcpu=hexagonv5 < %s | FileCheck %s 2; Generate various cmpb instruction followed by if (p0) .. if (!p0)... 3target triple = "hexagon" 4 5define i32 @Func_3Ugt(i32 %Enum_Par_Val, i32 %pv2) nounwind readnone { 6entry: 7; CHECK-NOT: mux 8 %cmp = icmp ugt i32 %Enum_Par_Val, %pv2 9 %selv = zext i1 %cmp to i32 10 ret i32 %selv 11} 12 13define i32 @Func_3Uge(i32 %Enum_Par_Val, i32 %pv2) nounwind readnone { 14entry: 15; CHECK-NOT: mux 16 %cmp = icmp uge i32 %Enum_Par_Val, %pv2 17 %selv = zext i1 %cmp to i32 18 ret i32 %selv 19} 20 21define i32 @Func_3Ult(i32 %Enum_Par_Val, i32 %pv2) nounwind readnone { 22entry: 23; CHECK-NOT: mux 24 %cmp = icmp ult i32 %Enum_Par_Val, %pv2 25 %selv = zext i1 %cmp to i32 26 ret i32 %selv 27} 28 29define i32 @Func_3Ule(i32 %Enum_Par_Val, i32 %pv2) nounwind readnone { 30entry: 31; CHECK-NOT: mux 32 %cmp = icmp ule i32 %Enum_Par_Val, %pv2 33 %selv = zext i1 %cmp to i32 34 ret i32 %selv 35} 36 37define i32 @Func_3Ueq(i32 %Enum_Par_Val, i32 %pv2) nounwind readnone { 38entry: 39; CHECK-NOT: mux 40 %cmp = icmp eq i32 %Enum_Par_Val, %pv2 41 %selv = zext i1 %cmp to i32 42 ret i32 %selv 43} 44 45define i32 @Func_3Une(i32 %Enum_Par_Val, i32 %pv2) nounwind readnone { 46entry: 47; CHECK-NOT: mux 48 %cmp = icmp ne i32 %Enum_Par_Val, %pv2 49 %selv = zext i1 %cmp to i32 50 ret i32 %selv 51} 52 53define i32 @Func_3UneC(i32 %Enum_Par_Val) nounwind readnone { 54entry: 55; CHECK-NOT: mux 56 %cmp = icmp ne i32 %Enum_Par_Val, 122 57 %selv = zext i1 %cmp to i32 58 ret i32 %selv 59} 60 61define i32 @Func_3gt(i32 %Enum_Par_Val, i32 %pv2) nounwind readnone { 62entry: 63; CHECK-NOT: mux 64 %cmp = icmp sgt i32 %Enum_Par_Val, %pv2 65 %selv = zext i1 %cmp to i32 66 ret i32 %selv 67} 68 69define i32 @Func_3ge(i32 %Enum_Par_Val, i32 %pv2) nounwind readnone { 70entry: 71; CHECK-NOT: mux 72 %cmp = icmp sge i32 %Enum_Par_Val, %pv2 73 %selv = zext i1 %cmp to i32 74 ret i32 %selv 75} 76 77define i32 @Func_3lt(i32 %Enum_Par_Val, i32 %pv2) nounwind readnone { 78entry: 79; CHECK-NOT: mux 80 %cmp = icmp slt i32 %Enum_Par_Val, %pv2 81 %selv = zext i1 %cmp to i32 82 ret i32 %selv 83} 84 85define i32 @Func_3le(i32 %Enum_Par_Val, i32 %pv2) nounwind readnone { 86entry: 87; CHECK-NOT: mux 88 %cmp = icmp sle i32 %Enum_Par_Val, %pv2 89 %selv = zext i1 %cmp to i32 90 ret i32 %selv 91} 92 93define i32 @Func_3eq(i32 %Enum_Par_Val, i32 %pv2) nounwind readnone { 94entry: 95; CHECK-NOT: mux 96 %cmp = icmp eq i32 %Enum_Par_Val, %pv2 97 %selv = zext i1 %cmp to i32 98 ret i32 %selv 99} 100 101define i32 @Func_3ne(i32 %Enum_Par_Val, i32 %pv2) nounwind readnone { 102entry: 103; CHECK-NOT: mux 104 %cmp = icmp ne i32 %Enum_Par_Val, %pv2 105 %selv = zext i1 %cmp to i32 106 ret i32 %selv 107} 108 109define i32 @Func_3neC(i32 %Enum_Par_Val) nounwind readnone { 110entry: 111; CHECK-NOT: mux 112 %cmp = icmp ne i32 %Enum_Par_Val, 122 113 %selv = zext i1 %cmp to i32 114 ret i32 %selv 115} 116