1; RUN: llc < %s -asm-verbose=false | FileCheck %s 2 3; Test that basic 32-bit integer operations assemble as expected. 4 5target datalayout = "E-m:e-p:32:32-i64:64-a:0:32-n32-S64" 6target triple = "lanai" 7 8; Function Attrs: nounwind readnone 9declare i32 @llvm.ctpop.i32(i32) #1 10 11; Function Attrs: nounwind readnone 12declare i32 @llvm.ctlz.i32(i32, i1) #1 13 14; Function Attrs: nounwind readnone 15declare i32 @llvm.cttz.i32(i32, i1) #1 16 17; CHECK-LABEL: add32: 18; CHECK: add %r{{[0-9]+}}, %r{{[0-9]+}}, %rv 19define i32 @add32(i32 %x, i32 %y) { 20 %a = add i32 %x, %y 21 ret i32 %a 22} 23 24; CHECK-LABEL: sub32: 25; CHECK: sub %r{{[0-9]+}}, %r{{[0-9]+}}, %rv 26define i32 @sub32(i32 %x, i32 %y) { 27 %a = sub i32 %x, %y 28 ret i32 %a 29} 30 31; CHECK-LABEL: mul32: 32; CHECK: bt __mulsi3 33define i32 @mul32(i32 %x, i32 %y) { 34 %a = mul i32 %x, %y 35 ret i32 %a 36} 37 38; CHECK-LABEL: sdiv32: 39; CHECK: bt __divsi3 40define i32 @sdiv32(i32 %x, i32 %y) { 41 %a = sdiv i32 %x, %y 42 ret i32 %a 43} 44 45; CHECK-LABEL: udiv32: 46; CHECK: bt __udivsi3 47define i32 @udiv32(i32 %x, i32 %y) { 48 %a = udiv i32 %x, %y 49 ret i32 %a 50} 51 52; CHECK-LABEL: srem32: 53; CHECK: bt __modsi3 54define i32 @srem32(i32 %x, i32 %y) { 55 %a = srem i32 %x, %y 56 ret i32 %a 57} 58 59; CHECK-LABEL: urem32: 60; CHECK: bt __umodsi3 61define i32 @urem32(i32 %x, i32 %y) { 62 %a = urem i32 %x, %y 63 ret i32 %a 64} 65 66; CHECK-LABEL: and32: 67; CHECK: and %r{{[0-9]+}}, %r{{[0-9]+}}, %rv 68define i32 @and32(i32 %x, i32 %y) { 69 %a = and i32 %x, %y 70 ret i32 %a 71} 72 73; CHECK-LABEL: or32: 74; CHECK: or %r{{[0-9]+}}, %r{{[0-9]+}}, %rv 75define i32 @or32(i32 %x, i32 %y) { 76 %a = or i32 %x, %y 77 ret i32 %a 78} 79 80; CHECK-LABEL: xor32: 81; CHECK: xor %r{{[0-9]+}}, %r{{[0-9]+}}, %rv 82define i32 @xor32(i32 %x, i32 %y) { 83 %a = xor i32 %x, %y 84 ret i32 %a 85} 86 87; CHECK-LABEL: shl32: 88; CHECK: sh %r{{[0-9]+}}, %r{{[0-9]+}}, %rv 89define i32 @shl32(i32 %x, i32 %y) { 90 %a = shl i32 %x, %y 91 ret i32 %a 92} 93 94; CHECK-LABEL: shr32: 95; CHECK: sub %r0, %r{{[0-9]+}}, %r{{[0-9]+}} 96; CHECK: sh %r{{[0-9]+}}, %r{{[0-9]+}}, %rv 97define i32 @shr32(i32 %x, i32 %y) { 98 %a = lshr i32 %x, %y 99 ret i32 %a 100} 101 102; CHECK-LABEL: sar32 103; CHECK: sub %r0, %r{{[0-9]+}}, %r{{[0-9]+}} 104; CHECK: sha %r{{[0-9]+}}, %r{{[0-9]+}}, %rv 105define i32 @sar32(i32 %x, i32 %y) { 106 %a = ashr i32 %x, %y 107 ret i32 %a 108} 109 110; CHECK-LABEL: clz32: 111; CHECK: leadz %r{{[0-9]+}}, %rv 112define i32 @clz32(i32 %x) { 113 %a = call i32 @llvm.ctlz.i32(i32 %x, i1 false) 114 ret i32 %a 115} 116 117; CHECK-LABEL: clz32_zero_undef: 118; CHECK-NOT: sub.f 119; CHECK: leadz %r{{[0-9]+}}, %rv 120define i32 @clz32_zero_undef(i32 %x) { 121 %a = call i32 @llvm.ctlz.i32(i32 %x, i1 true) 122 ret i32 %a 123} 124 125; CHECK-LABEL: ctz32: 126; CHECK: trailz %r{{[0-9]+}}, %rv 127define i32 @ctz32(i32 %x) { 128 %a = call i32 @llvm.cttz.i32(i32 %x, i1 false) 129 ret i32 %a 130} 131 132; CHECK-LABEL: ctz32_zero_undef: 133; CHECK-NOT: sub.f 134; CHECK: trailz %r{{[0-9]+}}, %rv 135define i32 @ctz32_zero_undef(i32 %x) { 136 %a = call i32 @llvm.cttz.i32(i32 %x, i1 true) 137 ret i32 %a 138} 139 140; CHECK-LABEL: popcnt32: 141; CHECK: popc %r{{[0-9]+}}, %rv 142define i32 @popcnt32(i32 %x) { 143 %a = call i32 @llvm.ctpop.i32(i32 %x) 144 ret i32 %a 145} 146