1; RUN: llc < %s -march=mipsel -mcpu=mips32 -O0 -relocation-model=pic 2; RUN: llc < %s -march=mipsel -mcpu=mips32r2 -O0 -relocation-model=pic 3 4; The test is just to make sure it is able to allocate 5; registers for this example. There was an issue with allocating AC0 6; after a mul instruction. 7 8declare { i32, i1 } @llvm.smul.with.overflow.i32(i32, i32) 9 10define i32 @foo(i32 %a, i32 %b) { 11entry: 12 %0 = mul i32 %a, %b 13 %1 = call { i32, i1 } @llvm.smul.with.overflow.i32(i32 %0, i32 %b) 14 %2 = extractvalue { i32, i1 } %1, 0 15 ret i32 %2 16} 17