1; Test the MSA intrinsics that are encoded with the 3RF instruction format and 2; take an integer as an operand. 3 4; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s 5; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s | FileCheck %s 6 7@llvm_mips_fexp2_w_ARG1 = global <4 x float> <float 0.000000e+00, float 1.000000e+00, float 2.000000e+00, float 3.000000e+00>, align 16 8@llvm_mips_fexp2_w_ARG2 = global <4 x i32> <i32 4, i32 5, i32 6, i32 7>, align 16 9@llvm_mips_fexp2_w_RES = global <4 x float> <float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00>, align 16 10 11define void @llvm_mips_fexp2_w_test() nounwind { 12entry: 13 %0 = load <4 x float>, <4 x float>* @llvm_mips_fexp2_w_ARG1 14 %1 = load <4 x i32>, <4 x i32>* @llvm_mips_fexp2_w_ARG2 15 %2 = tail call <4 x float> @llvm.mips.fexp2.w(<4 x float> %0, <4 x i32> %1) 16 store <4 x float> %2, <4 x float>* @llvm_mips_fexp2_w_RES 17 ret void 18} 19 20declare <4 x float> @llvm.mips.fexp2.w(<4 x float>, <4 x i32>) nounwind 21 22; CHECK: llvm_mips_fexp2_w_test: 23; CHECK: ld.w 24; CHECK: ld.w 25; CHECK: fexp2.w 26; CHECK: st.w 27; CHECK: .size llvm_mips_fexp2_w_test 28; 29@llvm_mips_fexp2_d_ARG1 = global <2 x double> <double 0.000000e+00, double 1.000000e+00>, align 16 30@llvm_mips_fexp2_d_ARG2 = global <2 x i64> <i64 2, i64 3>, align 16 31@llvm_mips_fexp2_d_RES = global <2 x double> <double 0.000000e+00, double 0.000000e+00>, align 16 32 33define void @llvm_mips_fexp2_d_test() nounwind { 34entry: 35 %0 = load <2 x double>, <2 x double>* @llvm_mips_fexp2_d_ARG1 36 %1 = load <2 x i64>, <2 x i64>* @llvm_mips_fexp2_d_ARG2 37 %2 = tail call <2 x double> @llvm.mips.fexp2.d(<2 x double> %0, <2 x i64> %1) 38 store <2 x double> %2, <2 x double>* @llvm_mips_fexp2_d_RES 39 ret void 40} 41 42declare <2 x double> @llvm.mips.fexp2.d(<2 x double>, <2 x i64>) nounwind 43 44; CHECK: llvm_mips_fexp2_d_test: 45; CHECK: ld.d 46; CHECK: ld.d 47; CHECK: fexp2.d 48; CHECK: st.d 49; CHECK: .size llvm_mips_fexp2_d_test 50; 51