1; RUN: llc < %s -march=nvptx -mcpu=sm_20 | FileCheck %s --check-prefix=SM20 2; RUN: llc < %s -march=nvptx -mcpu=sm_30 | FileCheck %s --check-prefix=SM30 3 4target triple = "nvptx-unknown-cuda" 5 6@tex0 = internal addrspace(1) global i64 0, align 8 7@surf0 = internal addrspace(1) global i64 0, align 8 8 9declare i32 @llvm.nvvm.txq.width(i64) 10declare i32 @llvm.nvvm.txq.height(i64) 11declare i32 @llvm.nvvm.suq.width(i64) 12declare i32 @llvm.nvvm.suq.height(i64) 13declare i64 @llvm.nvvm.texsurf.handle.internal.p1i64(i64 addrspace(1)*) 14 15 16; SM20-LABEL: @t0 17; SM30-LABEL: @t0 18define i32 @t0(i64 %texHandle) { 19; SM20: txq.width.b32 20; SM30: txq.width.b32 21 %width = tail call i32 @llvm.nvvm.txq.width(i64 %texHandle) 22 ret i32 %width 23} 24 25; SM20-LABEL: @t1 26; SM30-LABEL: @t1 27define i32 @t1() { 28; SM30: mov.u64 %rd[[HANDLE:[0-9]+]], tex0 29 %texHandle = tail call i64 @llvm.nvvm.texsurf.handle.internal.p1i64(i64 addrspace(1)* @tex0) 30; SM20: txq.width.b32 %r{{[0-9]+}}, [tex0] 31; SM30: txq.width.b32 %r{{[0-9]+}}, [%rd[[HANDLE:[0-9]+]]] 32 %width = tail call i32 @llvm.nvvm.txq.width(i64 %texHandle) 33 ret i32 %width 34} 35 36 37; SM20-LABEL: @t2 38; SM30-LABEL: @t2 39define i32 @t2(i64 %texHandle) { 40; SM20: txq.height.b32 41; SM30: txq.height.b32 42 %height = tail call i32 @llvm.nvvm.txq.height(i64 %texHandle) 43 ret i32 %height 44} 45 46; SM20-LABEL: @t3 47; SM30-LABEL: @t3 48define i32 @t3() { 49; SM30: mov.u64 %rd[[HANDLE:[0-9]+]], tex0 50 %texHandle = tail call i64 @llvm.nvvm.texsurf.handle.internal.p1i64(i64 addrspace(1)* @tex0) 51; SM20: txq.height.b32 %r{{[0-9]+}}, [tex0] 52; SM30: txq.height.b32 %r{{[0-9]+}}, [%rd[[HANDLE:[0-9]+]]] 53 %height = tail call i32 @llvm.nvvm.txq.height(i64 %texHandle) 54 ret i32 %height 55} 56 57 58; SM20-LABEL: @s0 59; SM30-LABEL: @s0 60define i32 @s0(i64 %surfHandle) { 61; SM20: suq.width.b32 62; SM30: suq.width.b32 63 %width = tail call i32 @llvm.nvvm.suq.width(i64 %surfHandle) 64 ret i32 %width 65} 66 67; SM20-LABEL: @s1 68; SM30-LABEL: @s1 69define i32 @s1() { 70; SM30: mov.u64 %rd[[HANDLE:[0-9]+]], surf0 71 %surfHandle = tail call i64 @llvm.nvvm.texsurf.handle.internal.p1i64(i64 addrspace(1)* @surf0) 72; SM20: suq.width.b32 %r{{[0-9]+}}, [surf0] 73; SM30: suq.width.b32 %r{{[0-9]+}}, [%rd[[HANDLE:[0-9]+]]] 74 %width = tail call i32 @llvm.nvvm.suq.width(i64 %surfHandle) 75 ret i32 %width 76} 77 78 79; SM20-LABEL: @s2 80; SM30-LABEL: @s2 81define i32 @s2(i64 %surfHandle) { 82; SM20: suq.height.b32 83; SM30: suq.height.b32 84 %height = tail call i32 @llvm.nvvm.suq.height(i64 %surfHandle) 85 ret i32 %height 86} 87 88; SM20-LABEL: @s3 89; SM30-LABEL: @s3 90define i32 @s3() { 91; SM30: mov.u64 %rd[[HANDLE:[0-9]+]], surf0 92 %surfHandle = tail call i64 @llvm.nvvm.texsurf.handle.internal.p1i64(i64 addrspace(1)* @surf0) 93; SM20: suq.height.b32 %r{{[0-9]+}}, [surf0] 94; SM30: suq.height.b32 %r{{[0-9]+}}, [%rd[[HANDLE:[0-9]+]]] 95 %height = tail call i32 @llvm.nvvm.suq.height(i64 %surfHandle) 96 ret i32 %height 97} 98 99 100 101!nvvm.annotations = !{!1, !2} 102!1 = !{i64 addrspace(1)* @tex0, !"texture", i32 1} 103!2 = !{i64 addrspace(1)* @surf0, !"surface", i32 1} 104