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1; RUN: llc < %s | FileCheck %s
2; RUN: llc < %s -regalloc=fast -optimize-regalloc=0 | FileCheck %s
3; The first argument of subfc must not be the same as any other register.
4
5; CHECK: subfc [[REG:r.]],
6; CHECK-NOT: [[REG]]
7; CHECK: InlineAsm End
8; PR1357
9
10target datalayout = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64"
11target triple = "powerpc-apple-darwin8.8.0"
12
13;long long test(int A, int B, int C) {
14;  unsigned X, Y;
15;  __asm__ ("subf%I3c %1,%4,%3\n\tsubfze %0,%2"
16;                 : "=r" (X), "=&r" (Y)
17;                 : "r" (A), "rI" (B), "r" (C));
18;  return ((long long)Y << 32) | X;
19;}
20
21define i64 @test(i32 %A, i32 %B, i32 %C) nounwind {
22entry:
23	%Y = alloca i32, align 4		; <i32*> [#uses=2]
24	%tmp4 = call i32 asm "subf${3:I}c $1,$4,$3\0A\09subfze $0,$2", "=r,=*&r,r,rI,r"( i32* %Y, i32 %A, i32 %B, i32 %C )		; <i32> [#uses=1]
25	%tmp5 = load i32, i32* %Y		; <i32> [#uses=1]
26	%tmp56 = zext i32 %tmp5 to i64		; <i64> [#uses=1]
27	%tmp7 = shl i64 %tmp56, 32		; <i64> [#uses=1]
28	%tmp89 = zext i32 %tmp4 to i64		; <i64> [#uses=1]
29	%tmp10 = or i64 %tmp7, %tmp89		; <i64> [#uses=1]
30	ret i64 %tmp10
31}
32