1; RUN: llc -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr8 -mattr=-vsx < %s | FileCheck %s 2; RUN: llc -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr8 -mattr=-vsx < %s | FileCheck %s 3; RUN: llc -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 -mattr=+power8-vector -mattr=-vsx < %s | FileCheck %s 4; RUN: llc -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr8 < %s | FileCheck %s -check-prefix=CHECK-VSX 5 6@vsc = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 0, i8 1, i8 2, i8 3, i8 4, i8 5>, align 16 7@vsc2 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 0, i8 1, i8 2, i8 3, i8 4, i8 5>, align 16 8@vuc = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 0, i8 1, i8 2, i8 3, i8 4, i8 5>, align 16 9@vuc2 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 0, i8 1, i8 2, i8 3, i8 4, i8 5>, align 16 10@res_vll = common global <2 x i64> zeroinitializer, align 16 11@res_vull = common global <2 x i64> zeroinitializer, align 16 12@res_vsc = common global <16 x i8> zeroinitializer, align 16 13@res_vuc = common global <16 x i8> zeroinitializer, align 16 14 15; Function Attrs: nounwind 16define void @test1() { 17entry: 18 %0 = load <16 x i8>, <16 x i8>* @vsc, align 16 19 %1 = load <16 x i8>, <16 x i8>* @vsc2, align 16 20 %2 = call <2 x i64> @llvm.ppc.altivec.vbpermq(<16 x i8> %0, <16 x i8> %1) 21 store <2 x i64> %2, <2 x i64>* @res_vll, align 16 22 ret void 23; CHECK-LABEL: @test1 24; CHECK: lvx [[REG1:[0-9]+]], 0, 3 25; CHECK: lvx [[REG2:[0-9]+]], 0, 4 26; CHECK: vbpermq {{[0-9]+}}, [[REG1]], [[REG2]] 27; CHECK-VSX: vbpermq {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}} 28} 29 30; Function Attrs: nounwind 31define void @test2() { 32entry: 33 %0 = load <16 x i8>, <16 x i8>* @vuc, align 16 34 %1 = load <16 x i8>, <16 x i8>* @vuc2, align 16 35 %2 = call <2 x i64> @llvm.ppc.altivec.vbpermq(<16 x i8> %0, <16 x i8> %1) 36 store <2 x i64> %2, <2 x i64>* @res_vull, align 16 37 ret void 38; CHECK-LABEL: @test2 39; CHECK: lvx [[REG1:[0-9]+]], 0, 3 40; CHECK: lvx [[REG2:[0-9]+]], 0, 4 41; CHECK: vbpermq {{[0-9]+}}, [[REG1]], [[REG2]] 42; CHECK-VSX: vbpermq {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}} 43} 44 45; Function Attrs: nounwind 46define void @test3() { 47entry: 48 %0 = load <16 x i8>, <16 x i8>* @vsc, align 16 49 %1 = call <16 x i8> @llvm.ppc.altivec.vgbbd(<16 x i8> %0) 50 store <16 x i8> %1, <16 x i8>* @res_vsc, align 16 51 ret void 52; CHECK-LABEL: @test3 53; CHECK: lvx [[REG1:[0-9]+]], 54; CHECK: vgbbd {{[0-9]+}}, [[REG1]] 55; CHECK-VSX: vgbbd {{[0-9]+}}, {{[0-9]+}} 56} 57 58; Function Attrs: nounwind 59define void @test4() { 60entry: 61 %0 = load <16 x i8>, <16 x i8>* @vuc, align 16 62 %1 = call <16 x i8> @llvm.ppc.altivec.vgbbd(<16 x i8> %0) 63 store <16 x i8> %1, <16 x i8>* @res_vuc, align 16 64 ret void 65; CHECK-LABEL: @test4 66; CHECK: lvx [[REG1:[0-9]+]], 67; CHECK: vgbbd {{[0-9]+}}, [[REG1]] 68; CHECK-VSX: vgbbd {{[0-9]+}}, {{[0-9]+}} 69} 70 71; Function Attrs: nounwind readnone 72declare <2 x i64> @llvm.ppc.altivec.vbpermq(<16 x i8>, <16 x i8>) 73 74; Function Attrs: nounwind readnone 75declare <16 x i8> @llvm.ppc.altivec.vgbbd(<16 x i8>) 76