1; RUN: llc -mcpu pwr7 < %s | FileCheck %s 2target datalayout = "E-m:e-i64:64-n32:64" 3target triple = "powerpc64-unknown-linux-gnu" 4 5; Function Attrs: nounwind readnone 6define zeroext i16 @test16(i16 zeroext %x, i16 zeroext %y) #0 { 7entry: 8 %0 = xor i16 %y, %x 9 %1 = and i16 %0, 255 10 %cmp = icmp eq i16 %1, 0 11 %cmp20 = icmp ult i16 %0, 256 12 %conv25 = select i1 %cmp, i32 255, i32 0 13 %conv27 = select i1 %cmp20, i32 65280, i32 0 14 %or = or i32 %conv25, %conv27 15 %conv29 = trunc i32 %or to i16 16 ret i16 %conv29 17 18; CHECK-LABEL: @test16 19; CHECK: cmpb [[REG1:[0-9]+]], 4, 3 20; CHECK: clrldi 3, [[REG1]], 48 21; CHECK: blr 22} 23 24define zeroext i16 @test16p1(i16 zeroext %x, i16 zeroext %y) #0 { 25entry: 26 %0 = xor i16 %y, %x 27 %1 = and i16 %0, 255 28 %cmp = icmp eq i16 %1, 0 29 %cmp20 = icmp ult i16 %0, 256 30 %conv28 = select i1 %cmp, i32 5, i32 0 31 %conv30 = select i1 %cmp20, i32 65280, i32 0 32 %or = or i32 %conv28, %conv30 33 %conv32 = trunc i32 %or to i16 34 ret i16 %conv32 35 36; CHECK-LABEL: @test16p1 37; CHECK: cmpb [[REG1:[0-9]+]], 4, 3 38; CHECK: andi. 3, [[REG1]], 65285 39; CHECK: blr 40} 41 42; Function Attrs: nounwind readnone 43define zeroext i16 @test16p2(i16 zeroext %x, i16 zeroext %y) #0 { 44entry: 45 %0 = xor i16 %y, %x 46 %1 = and i16 %0, 255 47 %cmp = icmp eq i16 %1, 0 48 %cmp20 = icmp ult i16 %0, 256 49 %conv28 = select i1 %cmp, i32 255, i32 0 50 %conv30 = select i1 %cmp20, i32 1280, i32 0 51 %or = or i32 %conv28, %conv30 52 %conv32 = trunc i32 %or to i16 53 ret i16 %conv32 54 55; CHECK-LABEL: @test16p2 56; CHECK: cmpb [[REG1:[0-9]+]], 4, 3 57; CHECK: andi. 3, [[REG1]], 1535 58; CHECK: blr 59} 60 61; Function Attrs: nounwind readnone 62define zeroext i16 @test16p3(i16 zeroext %x, i16 zeroext %y) #0 { 63entry: 64 %0 = xor i16 %y, %x 65 %1 = and i16 %0, 255 66 %cmp = icmp eq i16 %1, 0 67 %cmp20 = icmp ult i16 %0, 256 68 %conv27 = select i1 %cmp, i32 255, i32 0 69 %conv29 = select i1 %cmp20, i32 1024, i32 1280 70 %or = or i32 %conv27, %conv29 71 %conv31 = trunc i32 %or to i16 72 ret i16 %conv31 73 74; CHECK-LABEL: @test16p3 75; CHECK: cmpb [[REG1:[0-9]+]], 4, 3 76; CHECK: clrldi [[REG2:[0-9]+]], [[REG1]], 55 77; CHECK: xori 3, [[REG2]], 1280 78; CHECK: blr 79} 80 81define zeroext i32 @test32(i32 zeroext %x, i32 zeroext %y) #0 { 82entry: 83 %0 = xor i32 %y, %x 84 %1 = and i32 %0, 255 85 %cmp = icmp eq i32 %1, 0 86 %2 = and i32 %0, 65280 87 %cmp28 = icmp eq i32 %2, 0 88 %3 = and i32 %0, 16711680 89 %cmp34 = icmp eq i32 %3, 0 90 %cmp40 = icmp ult i32 %0, 16777216 91 %conv44 = select i1 %cmp, i32 255, i32 0 92 %conv45 = select i1 %cmp28, i32 65280, i32 0 93 %conv47 = select i1 %cmp34, i32 16711680, i32 0 94 %conv50 = select i1 %cmp40, i32 -16777216, i32 0 95 %or = or i32 %conv45, %conv50 96 %or49 = or i32 %or, %conv44 97 %or52 = or i32 %or49, %conv47 98 ret i32 %or52 99 100; CHECK-LABEL: @test32 101; CHECK: cmpb [[REG1:[0-9]+]], 4, 3 102; CHECK: clrldi 3, [[REG1]], 32 103; CHECK: blr 104} 105 106define zeroext i32 @test32p1(i32 zeroext %x, i32 zeroext %y) #0 { 107entry: 108 %0 = xor i32 %y, %x 109 %1 = and i32 %0, 255 110 %cmp = icmp eq i32 %1, 0 111 %2 = and i32 %0, 65280 112 %cmp28 = icmp eq i32 %2, 0 113 %3 = and i32 %0, 16711680 114 %cmp34 = icmp eq i32 %3, 0 115 %cmp40 = icmp ult i32 %0, 16777216 116 %conv47 = select i1 %cmp, i32 255, i32 0 117 %conv48 = select i1 %cmp28, i32 65280, i32 0 118 %conv50 = select i1 %cmp34, i32 458752, i32 0 119 %conv53 = select i1 %cmp40, i32 -16777216, i32 0 120 %or = or i32 %conv48, %conv53 121 %or52 = or i32 %or, %conv47 122 %or55 = or i32 %or52, %conv50 123 ret i32 %or55 124 125; CHECK-LABEL: @test32p1 126; CHECK: li [[REG1:[0-9]+]], 0 127; CHECK: cmpb [[REG4:[0-9]+]], 4, 3 128; CHECK: oris [[REG2:[0-9]+]], [[REG1]], 65287 129; CHECK: ori [[REG3:[0-9]+]], [[REG2]], 65535 130; CHECK: and 3, [[REG4]], [[REG3]] 131; CHECK: blr 132} 133 134define zeroext i32 @test32p2(i32 zeroext %x, i32 zeroext %y) #0 { 135entry: 136 %0 = xor i32 %y, %x 137 %1 = and i32 %0, 255 138 %cmp = icmp eq i32 %1, 0 139 %2 = and i32 %0, 65280 140 %cmp22 = icmp eq i32 %2, 0 141 %cmp28 = icmp ult i32 %0, 16777216 142 %conv32 = select i1 %cmp, i32 255, i32 0 143 %conv33 = select i1 %cmp22, i32 65280, i32 0 144 %conv35 = select i1 %cmp28, i32 -16777216, i32 0 145 %or = or i32 %conv33, %conv35 146 %or37 = or i32 %or, %conv32 147 ret i32 %or37 148 149; CHECK-LABEL: @test32p2 150; CHECK: li [[REG1:[0-9]+]], 0 151; CHECK: cmpb [[REG4:[0-9]+]], 4, 3 152; CHECK: oris [[REG2:[0-9]+]], [[REG1]], 65280 153; CHECK: ori [[REG3:[0-9]+]], [[REG2]], 65535 154; CHECK: and 3, [[REG4]], [[REG3]] 155; CHECK: blr 156} 157 158define i64 @test64(i64 %x, i64 %y) #0 { 159entry: 160 %shr19 = lshr i64 %x, 56 161 %conv21 = trunc i64 %shr19 to i32 162 %shr43 = lshr i64 %y, 56 163 %conv45 = trunc i64 %shr43 to i32 164 %0 = xor i64 %y, %x 165 %1 = and i64 %0, 255 166 %cmp = icmp eq i64 %1, 0 167 %2 = and i64 %0, 65280 168 %cmp52 = icmp eq i64 %2, 0 169 %3 = and i64 %0, 16711680 170 %cmp58 = icmp eq i64 %3, 0 171 %4 = and i64 %0, 4278190080 172 %cmp64 = icmp eq i64 %4, 0 173 %5 = and i64 %0, 1095216660480 174 %cmp70 = icmp eq i64 %5, 0 175 %6 = and i64 %0, 280375465082880 176 %cmp76 = icmp eq i64 %6, 0 177 %7 = and i64 %0, 71776119061217280 178 %cmp82 = icmp eq i64 %7, 0 179 %cmp88 = icmp eq i32 %conv21, %conv45 180 %conv92 = select i1 %cmp, i64 255, i64 0 181 %conv93 = select i1 %cmp52, i64 65280, i64 0 182 %or = or i64 %conv92, %conv93 183 %conv95 = select i1 %cmp58, i64 16711680, i64 0 184 %or97 = or i64 %or, %conv95 185 %conv98 = select i1 %cmp64, i64 4278190080, i64 0 186 %or100 = or i64 %or97, %conv98 187 %conv101 = select i1 %cmp70, i64 1095216660480, i64 0 188 %or103 = or i64 %or100, %conv101 189 %conv104 = select i1 %cmp76, i64 280375465082880, i64 0 190 %or106 = or i64 %or103, %conv104 191 %conv107 = select i1 %cmp82, i64 71776119061217280, i64 0 192 %or109 = or i64 %or106, %conv107 193 %conv110 = select i1 %cmp88, i64 -72057594037927936, i64 0 194 %or112 = or i64 %or109, %conv110 195 ret i64 %or112 196 197; CHECK-LABEL: @test64 198; CHECK: cmpb 3, 3, 4 199; CHECK-NOT: rldicl 200; CHECK: blr 201} 202 203attributes #0 = { nounwind readnone } 204 205