1; Test sign extensions from a byte to an i32. 2; 3; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s 4 5; Test register extension, starting with an i32. 6define i32 @f1(i32 %a) { 7; CHECK-LABEL: f1: 8; CHECK: lbr %r2, %r2 9; CHECK: br %r14 10 %byte = trunc i32 %a to i8 11 %ext = sext i8 %byte to i32 12 ret i32 %ext 13} 14 15; ...and again with an i64. 16define i32 @f2(i64 %a) { 17; CHECK-LABEL: f2: 18; CHECK: lbr %r2, %r2 19; CHECK: br %r14 20 %byte = trunc i64 %a to i8 21 %ext = sext i8 %byte to i32 22 ret i32 %ext 23} 24 25; Check LB with no displacement. 26define i32 @f3(i8 *%src) { 27; CHECK-LABEL: f3: 28; CHECK: lb %r2, 0(%r2) 29; CHECK: br %r14 30 %byte = load i8 , i8 *%src 31 %ext = sext i8 %byte to i32 32 ret i32 %ext 33} 34 35; Check the high end of the LB range. 36define i32 @f4(i8 *%src) { 37; CHECK-LABEL: f4: 38; CHECK: lb %r2, 524287(%r2) 39; CHECK: br %r14 40 %ptr = getelementptr i8, i8 *%src, i64 524287 41 %byte = load i8 , i8 *%ptr 42 %ext = sext i8 %byte to i32 43 ret i32 %ext 44} 45 46; Check the next byte up, which needs separate address logic. 47; Other sequences besides this one would be OK. 48define i32 @f5(i8 *%src) { 49; CHECK-LABEL: f5: 50; CHECK: agfi %r2, 524288 51; CHECK: lb %r2, 0(%r2) 52; CHECK: br %r14 53 %ptr = getelementptr i8, i8 *%src, i64 524288 54 %byte = load i8 , i8 *%ptr 55 %ext = sext i8 %byte to i32 56 ret i32 %ext 57} 58 59; Check the high end of the negative LB range. 60define i32 @f6(i8 *%src) { 61; CHECK-LABEL: f6: 62; CHECK: lb %r2, -1(%r2) 63; CHECK: br %r14 64 %ptr = getelementptr i8, i8 *%src, i64 -1 65 %byte = load i8 , i8 *%ptr 66 %ext = sext i8 %byte to i32 67 ret i32 %ext 68} 69 70; Check the low end of the LB range. 71define i32 @f7(i8 *%src) { 72; CHECK-LABEL: f7: 73; CHECK: lb %r2, -524288(%r2) 74; CHECK: br %r14 75 %ptr = getelementptr i8, i8 *%src, i64 -524288 76 %byte = load i8 , i8 *%ptr 77 %ext = sext i8 %byte to i32 78 ret i32 %ext 79} 80 81; Check the next byte down, which needs separate address logic. 82; Other sequences besides this one would be OK. 83define i32 @f8(i8 *%src) { 84; CHECK-LABEL: f8: 85; CHECK: agfi %r2, -524289 86; CHECK: lb %r2, 0(%r2) 87; CHECK: br %r14 88 %ptr = getelementptr i8, i8 *%src, i64 -524289 89 %byte = load i8 , i8 *%ptr 90 %ext = sext i8 %byte to i32 91 ret i32 %ext 92} 93 94; Check that LB allows an index 95define i32 @f9(i64 %src, i64 %index) { 96; CHECK-LABEL: f9: 97; CHECK: lb %r2, 524287(%r3,%r2) 98; CHECK: br %r14 99 %add1 = add i64 %src, %index 100 %add2 = add i64 %add1, 524287 101 %ptr = inttoptr i64 %add2 to i8 * 102 %byte = load i8 , i8 *%ptr 103 %ext = sext i8 %byte to i32 104 ret i32 %ext 105} 106 107; Test a case where we spill the source of at least one LBR. We want 108; to use LB if possible. 109define void @f10(i32 *%ptr) { 110; CHECK-LABEL: f10: 111; CHECK: lb {{%r[0-9]+}}, 16{{[37]}}(%r15) 112; CHECK: br %r14 113 %val0 = load volatile i32 , i32 *%ptr 114 %val1 = load volatile i32 , i32 *%ptr 115 %val2 = load volatile i32 , i32 *%ptr 116 %val3 = load volatile i32 , i32 *%ptr 117 %val4 = load volatile i32 , i32 *%ptr 118 %val5 = load volatile i32 , i32 *%ptr 119 %val6 = load volatile i32 , i32 *%ptr 120 %val7 = load volatile i32 , i32 *%ptr 121 %val8 = load volatile i32 , i32 *%ptr 122 %val9 = load volatile i32 , i32 *%ptr 123 %val10 = load volatile i32 , i32 *%ptr 124 %val11 = load volatile i32 , i32 *%ptr 125 %val12 = load volatile i32 , i32 *%ptr 126 %val13 = load volatile i32 , i32 *%ptr 127 %val14 = load volatile i32 , i32 *%ptr 128 %val15 = load volatile i32 , i32 *%ptr 129 130 %trunc0 = trunc i32 %val0 to i8 131 %trunc1 = trunc i32 %val1 to i8 132 %trunc2 = trunc i32 %val2 to i8 133 %trunc3 = trunc i32 %val3 to i8 134 %trunc4 = trunc i32 %val4 to i8 135 %trunc5 = trunc i32 %val5 to i8 136 %trunc6 = trunc i32 %val6 to i8 137 %trunc7 = trunc i32 %val7 to i8 138 %trunc8 = trunc i32 %val8 to i8 139 %trunc9 = trunc i32 %val9 to i8 140 %trunc10 = trunc i32 %val10 to i8 141 %trunc11 = trunc i32 %val11 to i8 142 %trunc12 = trunc i32 %val12 to i8 143 %trunc13 = trunc i32 %val13 to i8 144 %trunc14 = trunc i32 %val14 to i8 145 %trunc15 = trunc i32 %val15 to i8 146 147 %ext0 = sext i8 %trunc0 to i32 148 %ext1 = sext i8 %trunc1 to i32 149 %ext2 = sext i8 %trunc2 to i32 150 %ext3 = sext i8 %trunc3 to i32 151 %ext4 = sext i8 %trunc4 to i32 152 %ext5 = sext i8 %trunc5 to i32 153 %ext6 = sext i8 %trunc6 to i32 154 %ext7 = sext i8 %trunc7 to i32 155 %ext8 = sext i8 %trunc8 to i32 156 %ext9 = sext i8 %trunc9 to i32 157 %ext10 = sext i8 %trunc10 to i32 158 %ext11 = sext i8 %trunc11 to i32 159 %ext12 = sext i8 %trunc12 to i32 160 %ext13 = sext i8 %trunc13 to i32 161 %ext14 = sext i8 %trunc14 to i32 162 %ext15 = sext i8 %trunc15 to i32 163 164 store volatile i32 %val0, i32 *%ptr 165 store volatile i32 %val1, i32 *%ptr 166 store volatile i32 %val2, i32 *%ptr 167 store volatile i32 %val3, i32 *%ptr 168 store volatile i32 %val4, i32 *%ptr 169 store volatile i32 %val5, i32 *%ptr 170 store volatile i32 %val6, i32 *%ptr 171 store volatile i32 %val7, i32 *%ptr 172 store volatile i32 %val8, i32 *%ptr 173 store volatile i32 %val9, i32 *%ptr 174 store volatile i32 %val10, i32 *%ptr 175 store volatile i32 %val11, i32 *%ptr 176 store volatile i32 %val12, i32 *%ptr 177 store volatile i32 %val13, i32 *%ptr 178 store volatile i32 %val14, i32 *%ptr 179 store volatile i32 %val15, i32 *%ptr 180 181 store volatile i32 %ext0, i32 *%ptr 182 store volatile i32 %ext1, i32 *%ptr 183 store volatile i32 %ext2, i32 *%ptr 184 store volatile i32 %ext3, i32 *%ptr 185 store volatile i32 %ext4, i32 *%ptr 186 store volatile i32 %ext5, i32 *%ptr 187 store volatile i32 %ext6, i32 *%ptr 188 store volatile i32 %ext7, i32 *%ptr 189 store volatile i32 %ext8, i32 *%ptr 190 store volatile i32 %ext9, i32 *%ptr 191 store volatile i32 %ext10, i32 *%ptr 192 store volatile i32 %ext11, i32 *%ptr 193 store volatile i32 %ext12, i32 *%ptr 194 store volatile i32 %ext13, i32 *%ptr 195 store volatile i32 %ext14, i32 *%ptr 196 store volatile i32 %ext15, i32 *%ptr 197 198 ret void 199} 200