1; Test 32-bit arithmetic shifts right. 2; 3; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s 4 5; Check the low end of the SRA range. 6define i32 @f1(i32 %a) { 7; CHECK-LABEL: f1: 8; CHECK: sra %r2, 1 9; CHECK: br %r14 10 %shift = ashr i32 %a, 1 11 ret i32 %shift 12} 13 14; Check the high end of the defined SRA range. 15define i32 @f2(i32 %a) { 16; CHECK-LABEL: f2: 17; CHECK: sra %r2, 31 18; CHECK: br %r14 19 %shift = ashr i32 %a, 31 20 ret i32 %shift 21} 22 23; We don't generate shifts by out-of-range values. 24define i32 @f3(i32 %a) { 25; CHECK-LABEL: f3: 26; CHECK-NOT: sra %r2, 32 27; CHECK: br %r14 28 %shift = ashr i32 %a, 32 29 ret i32 %shift 30} 31 32; Make sure that we don't generate negative shift amounts. 33define i32 @f4(i32 %a, i32 %amt) { 34; CHECK-LABEL: f4: 35; CHECK-NOT: sra %r2, -1{{.*}} 36; CHECK: br %r14 37 %sub = sub i32 %amt, 1 38 %shift = ashr i32 %a, %sub 39 ret i32 %shift 40} 41 42; Check variable shifts. 43define i32 @f5(i32 %a, i32 %amt) { 44; CHECK-LABEL: f5: 45; CHECK: sra %r2, 0(%r3) 46; CHECK: br %r14 47 %shift = ashr i32 %a, %amt 48 ret i32 %shift 49} 50 51; Check shift amounts that have a constant term. 52define i32 @f6(i32 %a, i32 %amt) { 53; CHECK-LABEL: f6: 54; CHECK: sra %r2, 10(%r3) 55; CHECK: br %r14 56 %add = add i32 %amt, 10 57 %shift = ashr i32 %a, %add 58 ret i32 %shift 59} 60 61; ...and again with a truncated 64-bit shift amount. 62define i32 @f7(i32 %a, i64 %amt) { 63; CHECK-LABEL: f7: 64; CHECK: sra %r2, 10(%r3) 65; CHECK: br %r14 66 %add = add i64 %amt, 10 67 %trunc = trunc i64 %add to i32 68 %shift = ashr i32 %a, %trunc 69 ret i32 %shift 70} 71 72; Check shift amounts that have the largest in-range constant term. We could 73; mask the amount instead. 74define i32 @f8(i32 %a, i32 %amt) { 75; CHECK-LABEL: f8: 76; CHECK: sra %r2, 4095(%r3) 77; CHECK: br %r14 78 %add = add i32 %amt, 4095 79 %shift = ashr i32 %a, %add 80 ret i32 %shift 81} 82 83; Check the next value up. Again, we could mask the amount instead. 84define i32 @f9(i32 %a, i32 %amt) { 85; CHECK-LABEL: f9: 86; CHECK: ahi %r3, 4096 87; CHECK: sra %r2, 0(%r3) 88; CHECK: br %r14 89 %add = add i32 %amt, 4096 90 %shift = ashr i32 %a, %add 91 ret i32 %shift 92} 93 94; Check that we don't try to generate "indexed" shifts. 95define i32 @f10(i32 %a, i32 %b, i32 %c) { 96; CHECK-LABEL: f10: 97; CHECK: ar {{%r3, %r4|%r4, %r3}} 98; CHECK: sra %r2, 0({{%r[34]}}) 99; CHECK: br %r14 100 %add = add i32 %b, %c 101 %shift = ashr i32 %a, %add 102 ret i32 %shift 103} 104 105; Check that the shift amount uses an address register. It cannot be in %r0. 106define i32 @f11(i32 %a, i32 *%ptr) { 107; CHECK-LABEL: f11: 108; CHECK: l %r1, 0(%r3) 109; CHECK: sra %r2, 0(%r1) 110; CHECK: br %r14 111 %amt = load i32 , i32 *%ptr 112 %shift = ashr i32 %a, %amt 113 ret i32 %shift 114} 115