1; Test v8i16 absolute. 2; 3; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s 4 5; Test with slt. 6define <8 x i16> @f1(<8 x i16> %val) { 7; CHECK-LABEL: f1: 8; CHECK: vlph %v24, %v24 9; CHECK: br %r14 10 %cmp = icmp slt <8 x i16> %val, zeroinitializer 11 %neg = sub <8 x i16> zeroinitializer, %val 12 %ret = select <8 x i1> %cmp, <8 x i16> %neg, <8 x i16> %val 13 ret <8 x i16> %ret 14} 15 16; Test with sle. 17define <8 x i16> @f2(<8 x i16> %val) { 18; CHECK-LABEL: f2: 19; CHECK: vlph %v24, %v24 20; CHECK: br %r14 21 %cmp = icmp sle <8 x i16> %val, zeroinitializer 22 %neg = sub <8 x i16> zeroinitializer, %val 23 %ret = select <8 x i1> %cmp, <8 x i16> %neg, <8 x i16> %val 24 ret <8 x i16> %ret 25} 26 27; Test with sgt. 28define <8 x i16> @f3(<8 x i16> %val) { 29; CHECK-LABEL: f3: 30; CHECK: vlph %v24, %v24 31; CHECK: br %r14 32 %cmp = icmp sgt <8 x i16> %val, zeroinitializer 33 %neg = sub <8 x i16> zeroinitializer, %val 34 %ret = select <8 x i1> %cmp, <8 x i16> %val, <8 x i16> %neg 35 ret <8 x i16> %ret 36} 37 38; Test with sge. 39define <8 x i16> @f4(<8 x i16> %val) { 40; CHECK-LABEL: f4: 41; CHECK: vlph %v24, %v24 42; CHECK: br %r14 43 %cmp = icmp sge <8 x i16> %val, zeroinitializer 44 %neg = sub <8 x i16> zeroinitializer, %val 45 %ret = select <8 x i1> %cmp, <8 x i16> %val, <8 x i16> %neg 46 ret <8 x i16> %ret 47} 48 49; Test that negative absolute uses VLPH too. There is no vector equivalent 50; of LOAD NEGATIVE. 51define <8 x i16> @f5(<8 x i16> %val) { 52; CHECK-LABEL: f5: 53; CHECK: vlph [[REG:%v[0-9]+]], %v24 54; CHECK: vlch %v24, [[REG]] 55; CHECK: br %r14 56 %cmp = icmp slt <8 x i16> %val, zeroinitializer 57 %neg = sub <8 x i16> zeroinitializer, %val 58 %abs = select <8 x i1> %cmp, <8 x i16> %neg, <8 x i16> %val 59 %ret = sub <8 x i16> zeroinitializer, %abs 60 ret <8 x i16> %ret 61} 62 63; Try another form of negative absolute (slt version). 64define <8 x i16> @f6(<8 x i16> %val) { 65; CHECK-LABEL: f6: 66; CHECK: vlph [[REG:%v[0-9]+]], %v24 67; CHECK: vlch %v24, [[REG]] 68; CHECK: br %r14 69 %cmp = icmp slt <8 x i16> %val, zeroinitializer 70 %neg = sub <8 x i16> zeroinitializer, %val 71 %ret = select <8 x i1> %cmp, <8 x i16> %val, <8 x i16> %neg 72 ret <8 x i16> %ret 73} 74 75; Test with sle. 76define <8 x i16> @f7(<8 x i16> %val) { 77; CHECK-LABEL: f7: 78; CHECK: vlph [[REG:%v[0-9]+]], %v24 79; CHECK: vlch %v24, [[REG]] 80; CHECK: br %r14 81 %cmp = icmp sle <8 x i16> %val, zeroinitializer 82 %neg = sub <8 x i16> zeroinitializer, %val 83 %ret = select <8 x i1> %cmp, <8 x i16> %val, <8 x i16> %neg 84 ret <8 x i16> %ret 85} 86 87; Test with sgt. 88define <8 x i16> @f8(<8 x i16> %val) { 89; CHECK-LABEL: f8: 90; CHECK: vlph [[REG:%v[0-9]+]], %v24 91; CHECK: vlch %v24, [[REG]] 92; CHECK: br %r14 93 %cmp = icmp sgt <8 x i16> %val, zeroinitializer 94 %neg = sub <8 x i16> zeroinitializer, %val 95 %ret = select <8 x i1> %cmp, <8 x i16> %neg, <8 x i16> %val 96 ret <8 x i16> %ret 97} 98 99; Test with sge. 100define <8 x i16> @f9(<8 x i16> %val) { 101; CHECK-LABEL: f9: 102; CHECK: vlph [[REG:%v[0-9]+]], %v24 103; CHECK: vlch %v24, [[REG]] 104; CHECK: br %r14 105 %cmp = icmp sge <8 x i16> %val, zeroinitializer 106 %neg = sub <8 x i16> zeroinitializer, %val 107 %ret = select <8 x i1> %cmp, <8 x i16> %neg, <8 x i16> %val 108 ret <8 x i16> %ret 109} 110 111; Test with an SRA-based boolean vector. 112define <8 x i16> @f10(<8 x i16> %val) { 113; CHECK-LABEL: f10: 114; CHECK: vlph %v24, %v24 115; CHECK: br %r14 116 %shr = ashr <8 x i16> %val, 117 <i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15> 118 %neg = sub <8 x i16> zeroinitializer, %val 119 %and1 = and <8 x i16> %shr, %neg 120 %not = xor <8 x i16> %shr, 121 <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1> 122 %and2 = and <8 x i16> %not, %val 123 %ret = or <8 x i16> %and1, %and2 124 ret <8 x i16> %ret 125} 126 127; ...and again in reverse 128define <8 x i16> @f11(<8 x i16> %val) { 129; CHECK-LABEL: f11: 130; CHECK: vlph [[REG:%v[0-9]+]], %v24 131; CHECK: vlch %v24, [[REG]] 132; CHECK: br %r14 133 %shr = ashr <8 x i16> %val, 134 <i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15> 135 %and1 = and <8 x i16> %shr, %val 136 %not = xor <8 x i16> %shr, 137 <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1> 138 %neg = sub <8 x i16> zeroinitializer, %val 139 %and2 = and <8 x i16> %not, %neg 140 %ret = or <8 x i16> %and1, %and2 141 ret <8 x i16> %ret 142} 143