1; RUN: llc < %s -mtriple=thumbv7-none-eabi -mcpu=cortex-m3 | FileCheck %s -check-prefix=CHECK -check-prefix=NONE 2; RUN: llc < %s -mtriple=thumbv7-none-eabihf -mcpu=cortex-m4 | FileCheck %s -check-prefix=CHECK -check-prefix=HARD -check-prefix=SP 3; RUN: llc < %s -mtriple=thumbv7-none-eabihf -mcpu=cortex-m7 | FileCheck %s -check-prefix=CHECK -check-prefix=HARD -check-prefix=DP 4; RUN: llc < %s -mtriple=thumbv7-none-eabihf -mcpu=cortex-a8 | FileCheck %s -check-prefix=CHECK -check-prefix=HARD -check-prefix=DP 5 6 7 8define i1 @cmp_f_false(float %a, float %b) { 9; CHECK-LABEL: cmp_f_false: 10; NONE: movs r0, #0 11; HARD: movs r0, #0 12 %1 = fcmp false float %a, %b 13 ret i1 %1 14} 15define i1 @cmp_f_oeq(float %a, float %b) { 16; CHECK-LABEL: cmp_f_oeq: 17; NONE: bl __aeabi_fcmpeq 18; HARD: vcmpe.f32 19; HARD: moveq r0, #1 20 %1 = fcmp oeq float %a, %b 21 ret i1 %1 22} 23define i1 @cmp_f_ogt(float %a, float %b) { 24; CHECK-LABEL: cmp_f_ogt: 25; NONE: bl __aeabi_fcmpgt 26; HARD: vcmpe.f32 27; HARD: movgt r0, #1 28 %1 = fcmp ogt float %a, %b 29 ret i1 %1 30} 31define i1 @cmp_f_oge(float %a, float %b) { 32; CHECK-LABEL: cmp_f_oge: 33; NONE: bl __aeabi_fcmpge 34; HARD: vcmpe.f32 35; HARD: movge r0, #1 36 %1 = fcmp oge float %a, %b 37 ret i1 %1 38} 39define i1 @cmp_f_olt(float %a, float %b) { 40; CHECK-LABEL: cmp_f_olt: 41; NONE: bl __aeabi_fcmplt 42; HARD: vcmpe.f32 43; HARD: movmi r0, #1 44 %1 = fcmp olt float %a, %b 45 ret i1 %1 46} 47define i1 @cmp_f_ole(float %a, float %b) { 48; CHECK-LABEL: cmp_f_ole: 49; NONE: bl __aeabi_fcmple 50; HARD: vcmpe.f32 51; HARD: movls r0, #1 52 %1 = fcmp ole float %a, %b 53 ret i1 %1 54} 55define i1 @cmp_f_one(float %a, float %b) { 56; CHECK-LABEL: cmp_f_one: 57; NONE: bl __aeabi_fcmpgt 58; NONE: bl __aeabi_fcmplt 59; HARD: vcmpe.f32 60; HARD: movmi r0, #1 61; HARD: movgt r0, #1 62 %1 = fcmp one float %a, %b 63 ret i1 %1 64} 65define i1 @cmp_f_ord(float %a, float %b) { 66; CHECK-LABEL: cmp_f_ord: 67; NONE: bl __aeabi_fcmpun 68; HARD: vcmpe.f32 69; HARD: movvc r0, #1 70 %1 = fcmp ord float %a, %b 71 ret i1 %1 72}define i1 @cmp_f_ueq(float %a, float %b) { 73; CHECK-LABEL: cmp_f_ueq: 74; NONE: bl __aeabi_fcmpeq 75; NONE: bl __aeabi_fcmpun 76; HARD: vcmpe.f32 77; HARD: moveq r0, #1 78; HARD: movvs r0, #1 79 %1 = fcmp ueq float %a, %b 80 ret i1 %1 81} 82define i1 @cmp_f_ugt(float %a, float %b) { 83; CHECK-LABEL: cmp_f_ugt: 84; NONE: bl __aeabi_fcmple 85; NONE: cmp r0, #0 86; NONE-NEXT: it eq 87; HARD: vcmpe.f32 88; HARD: movhi r0, #1 89 %1 = fcmp ugt float %a, %b 90 ret i1 %1 91} 92define i1 @cmp_f_uge(float %a, float %b) { 93; CHECK-LABEL: cmp_f_uge: 94; NONE: bl __aeabi_fcmplt 95; NONE: cmp r0, #0 96; NONE-NEXT: it eq 97; HARD: vcmpe.f32 98; HARD: movpl r0, #1 99 %1 = fcmp uge float %a, %b 100 ret i1 %1 101} 102define i1 @cmp_f_ult(float %a, float %b) { 103; CHECK-LABEL: cmp_f_ult: 104; NONE: bl __aeabi_fcmpge 105; NONE: cmp r0, #0 106; NONE-NEXT: it eq 107; HARD: vcmpe.f32 108; HARD: movlt r0, #1 109 %1 = fcmp ult float %a, %b 110 ret i1 %1 111} 112define i1 @cmp_f_ule(float %a, float %b) { 113; CHECK-LABEL: cmp_f_ule: 114; NONE: bl __aeabi_fcmpgt 115; NONE: cmp r0, #0 116; NONE-NEXT: it eq 117; HARD: vcmpe.f32 118; HARD: movle r0, #1 119 %1 = fcmp ule float %a, %b 120 ret i1 %1 121} 122define i1 @cmp_f_une(float %a, float %b) { 123; CHECK-LABEL: cmp_f_une: 124; NONE: bl __aeabi_fcmpeq 125; HARD: vcmpe.f32 126; HARD: movne r0, #1 127 %1 = fcmp une float %a, %b 128 ret i1 %1 129} 130define i1 @cmp_f_uno(float %a, float %b) { 131; CHECK-LABEL: cmp_f_uno: 132; NONE: bl __aeabi_fcmpun 133; HARD: vcmpe.f32 134; HARD: movvs r0, #1 135 %1 = fcmp uno float %a, %b 136 ret i1 %1 137} 138define i1 @cmp_f_true(float %a, float %b) { 139; CHECK-LABEL: cmp_f_true: 140; NONE: movs r0, #1 141; HARD: movs r0, #1 142 %1 = fcmp true float %a, %b 143 ret i1 %1 144} 145 146define i1 @cmp_d_false(double %a, double %b) { 147; CHECK-LABEL: cmp_d_false: 148; NONE: movs r0, #0 149; HARD: movs r0, #0 150 %1 = fcmp false double %a, %b 151 ret i1 %1 152} 153define i1 @cmp_d_oeq(double %a, double %b) { 154; CHECK-LABEL: cmp_d_oeq: 155; NONE: bl __aeabi_dcmpeq 156; SP: bl __aeabi_dcmpeq 157; DP: vcmpe.f64 158; DP: moveq r0, #1 159 %1 = fcmp oeq double %a, %b 160 ret i1 %1 161} 162define i1 @cmp_d_ogt(double %a, double %b) { 163; CHECK-LABEL: cmp_d_ogt: 164; NONE: bl __aeabi_dcmpgt 165; SP: bl __aeabi_dcmpgt 166; DP: vcmpe.f64 167; DP: movgt r0, #1 168 %1 = fcmp ogt double %a, %b 169 ret i1 %1 170} 171define i1 @cmp_d_oge(double %a, double %b) { 172; CHECK-LABEL: cmp_d_oge: 173; NONE: bl __aeabi_dcmpge 174; SP: bl __aeabi_dcmpge 175; DP: vcmpe.f64 176; DP: movge r0, #1 177 %1 = fcmp oge double %a, %b 178 ret i1 %1 179} 180define i1 @cmp_d_olt(double %a, double %b) { 181; CHECK-LABEL: cmp_d_olt: 182; NONE: bl __aeabi_dcmplt 183; SP: bl __aeabi_dcmplt 184; DP: vcmpe.f64 185; DP: movmi r0, #1 186 %1 = fcmp olt double %a, %b 187 ret i1 %1 188} 189define i1 @cmp_d_ole(double %a, double %b) { 190; CHECK-LABEL: cmp_d_ole: 191; NONE: bl __aeabi_dcmple 192; SP: bl __aeabi_dcmple 193; DP: vcmpe.f64 194; DP: movls r0, #1 195 %1 = fcmp ole double %a, %b 196 ret i1 %1 197} 198define i1 @cmp_d_one(double %a, double %b) { 199; CHECK-LABEL: cmp_d_one: 200; NONE: bl __aeabi_dcmpgt 201; NONE: bl __aeabi_dcmplt 202; SP: bl __aeabi_dcmpgt 203; SP: bl __aeabi_dcmplt 204; DP: vcmpe.f64 205; DP: movmi r0, #1 206; DP: movgt r0, #1 207 %1 = fcmp one double %a, %b 208 ret i1 %1 209} 210define i1 @cmp_d_ord(double %a, double %b) { 211; CHECK-LABEL: cmp_d_ord: 212; NONE: bl __aeabi_dcmpun 213; SP: bl __aeabi_dcmpun 214; DP: vcmpe.f64 215; DP: movvc r0, #1 216 %1 = fcmp ord double %a, %b 217 ret i1 %1 218} 219define i1 @cmp_d_ugt(double %a, double %b) { 220; CHECK-LABEL: cmp_d_ugt: 221; NONE: bl __aeabi_dcmple 222; SP: bl __aeabi_dcmple 223; DP: vcmpe.f64 224; DP: movhi r0, #1 225 %1 = fcmp ugt double %a, %b 226 ret i1 %1 227} 228 229define i1 @cmp_d_ult(double %a, double %b) { 230; CHECK-LABEL: cmp_d_ult: 231; NONE: bl __aeabi_dcmpge 232; SP: bl __aeabi_dcmpge 233; DP: vcmpe.f64 234; DP: movlt r0, #1 235 %1 = fcmp ult double %a, %b 236 ret i1 %1 237} 238 239 240define i1 @cmp_d_uno(double %a, double %b) { 241; CHECK-LABEL: cmp_d_uno: 242; NONE: bl __aeabi_dcmpun 243; SP: bl __aeabi_dcmpun 244; DP: vcmpe.f64 245; DP: movvs r0, #1 246 %1 = fcmp uno double %a, %b 247 ret i1 %1 248} 249define i1 @cmp_d_true(double %a, double %b) { 250; CHECK-LABEL: cmp_d_true: 251; NONE: movs r0, #1 252; HARD: movs r0, #1 253 %1 = fcmp true double %a, %b 254 ret i1 %1 255} 256define i1 @cmp_d_ueq(double %a, double %b) { 257; CHECK-LABEL: cmp_d_ueq: 258; NONE: bl __aeabi_dcmpeq 259; NONE: bl __aeabi_dcmpun 260; SP: bl __aeabi_dcmpeq 261; SP: bl __aeabi_dcmpun 262; DP: vcmpe.f64 263; DP: moveq r0, #1 264; DP: movvs r0, #1 265 %1 = fcmp ueq double %a, %b 266 ret i1 %1 267} 268 269define i1 @cmp_d_uge(double %a, double %b) { 270; CHECK-LABEL: cmp_d_uge: 271; NONE: bl __aeabi_dcmplt 272; SP: bl __aeabi_dcmplt 273; DP: vcmpe.f64 274; DP: movpl r0, #1 275 %1 = fcmp uge double %a, %b 276 ret i1 %1 277} 278 279define i1 @cmp_d_ule(double %a, double %b) { 280; CHECK-LABEL: cmp_d_ule: 281; NONE: bl __aeabi_dcmpgt 282; SP: bl __aeabi_dcmpgt 283; DP: vcmpe.f64 284; DP: movle r0, #1 285 %1 = fcmp ule double %a, %b 286 ret i1 %1 287} 288 289define i1 @cmp_d_une(double %a, double %b) { 290; CHECK-LABEL: cmp_d_une: 291; NONE: bl __aeabi_dcmpeq 292; SP: bl __aeabi_dcmpeq 293; DP: vcmpe.f64 294; DP: movne r0, #1 295 %1 = fcmp une double %a, %b 296 ret i1 %1 297} 298