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1# RUN: llc -run-pass x86-fixup-bw-insts -mtriple=x86_64-- -o - %s | FileCheck %s
2
3# Verify that we correctly deal with the flag edge cases when replacing
4# copies by bigger copies, which is a pretty unusual transform.
5
6--- |
7  target datalayout = "e-m:o-i64:64-f80:128-n8:16:32:64-S128"
8
9  define i8 @test_movb_killed(i8 %a0) {
10    ret i8 %a0
11  }
12
13  define i8 @test_movb_impuse(i8 %a0) {
14    ret i8 %a0
15  }
16
17  define i8 @test_movb_impdef_gr64(i8 %a0) {
18    ret i8 %a0
19  }
20
21  define i8 @test_movb_impdef_gr32(i8 %a0) {
22    ret i8 %a0
23  }
24
25  define i8 @test_movb_impdef_gr16(i8 %a0) {
26    ret i8 %a0
27  }
28
29  define i16 @test_movw_impdef_gr32(i16 %a0) {
30    ret i16 %a0
31  }
32
33  define i16 @test_movw_impdef_gr64(i16 %a0) {
34    ret i16 %a0
35  }
36
37...
38
39---
40name:            test_movb_killed
41allVRegsAllocated: true
42isSSA:           false
43tracksRegLiveness: true
44liveins:
45  - { reg: '%edi' }
46body:             |
47  bb.0 (%ir-block.0):
48    liveins: %edi
49
50    ; CHECK: %eax = MOV32rr undef %edi, implicit %dil
51    %al = MOV8rr killed %dil
52    RETQ killed %al
53
54...
55
56---
57name:            test_movb_impuse
58allVRegsAllocated: true
59isSSA:           false
60tracksRegLiveness: true
61liveins:
62  - { reg: '%edi' }
63body:             |
64  bb.0 (%ir-block.0):
65    liveins: %edi
66
67    ; CHECK: %eax = MOV32rr undef %edi, implicit %dil
68    %al = MOV8rr %dil, implicit %edi
69    RETQ killed %al
70
71...
72
73---
74name:            test_movb_impdef_gr64
75allVRegsAllocated: true
76isSSA:           false
77tracksRegLiveness: true
78liveins:
79  - { reg: '%edi' }
80body:             |
81  bb.0 (%ir-block.0):
82    liveins: %edi
83
84    ; CHECK: %eax = MOV32rr undef %edi, implicit %dil, implicit-def %rax
85    %al = MOV8rr %dil, implicit-def %rax
86    RETQ killed %al
87
88...
89
90---
91name:            test_movb_impdef_gr32
92allVRegsAllocated: true
93isSSA:           false
94tracksRegLiveness: true
95liveins:
96  - { reg: '%edi' }
97body:             |
98  bb.0 (%ir-block.0):
99    liveins: %edi
100
101    ; CHECK: %eax = MOV32rr undef %edi, implicit %dil
102    %al = MOV8rr %dil, implicit-def %eax
103    RETQ killed %al
104
105...
106
107---
108name:            test_movb_impdef_gr16
109allVRegsAllocated: true
110isSSA:           false
111tracksRegLiveness: true
112liveins:
113  - { reg: '%edi' }
114body:             |
115  bb.0 (%ir-block.0):
116    liveins: %edi
117
118    ; CHECK: %eax = MOV32rr undef %edi, implicit %dil
119    %al = MOV8rr %dil, implicit-def %ax
120    RETQ killed %al
121
122...
123
124---
125name:            test_movw_impdef_gr32
126allVRegsAllocated: true
127isSSA:           false
128tracksRegLiveness: true
129liveins:
130  - { reg: '%edi' }
131body:             |
132  bb.0 (%ir-block.0):
133    liveins: %edi
134
135    ; CHECK: %eax = MOV32rr undef %edi, implicit %di
136    %ax = MOV16rr %di, implicit-def %eax
137    RETQ killed %ax
138
139...
140
141---
142name:            test_movw_impdef_gr64
143allVRegsAllocated: true
144isSSA:           false
145tracksRegLiveness: true
146liveins:
147  - { reg: '%edi' }
148body:             |
149  bb.0 (%ir-block.0):
150    liveins: %edi
151
152    ; CHECK: %eax = MOV32rr undef %edi, implicit %di, implicit-def %rax
153    %ax = MOV16rr %di, implicit-def %rax
154    RETQ killed %ax
155
156...
157