1; RUN: llc < %s -mtriple=x86_64-unknown-unknown | FileCheck %s 2 3define i32 @shl48sar47(i64 %a) #0 { 4; CHECK-LABEL: shl48sar47: 5; CHECK: # BB#0: 6; CHECK-NEXT: movswq %di, %rax 7 %1 = shl i64 %a, 48 8 %2 = ashr exact i64 %1, 47 9 %3 = trunc i64 %2 to i32 10 ret i32 %3 11} 12 13define i32 @shl48sar49(i64 %a) #0 { 14; CHECK-LABEL: shl48sar49: 15; CHECK: # BB#0: 16; CHECK-NEXT: movswq %di, %rax 17 %1 = shl i64 %a, 48 18 %2 = ashr exact i64 %1, 49 19 %3 = trunc i64 %2 to i32 20 ret i32 %3 21} 22 23define i32 @shl56sar55(i64 %a) #0 { 24; CHECK-LABEL: shl56sar55: 25; CHECK: # BB#0: 26; CHECK-NEXT: movsbq %dil, %rax 27 %1 = shl i64 %a, 56 28 %2 = ashr exact i64 %1, 55 29 %3 = trunc i64 %2 to i32 30 ret i32 %3 31} 32 33define i32 @shl56sar57(i64 %a) #0 { 34; CHECK-LABEL: shl56sar57: 35; CHECK: # BB#0: 36; CHECK-NEXT: movsbq %dil, %rax 37 %1 = shl i64 %a, 56 38 %2 = ashr exact i64 %1, 57 39 %3 = trunc i64 %2 to i32 40 ret i32 %3 41} 42 43attributes #0 = { nounwind } 44