1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc < %s -mtriple=i386-apple-darwin10 -mcpu=corei7-avx -mattr=+avx | FileCheck %s 3; RUN: llc < %s -mtriple=i386-apple-darwin10 -mcpu=corei7-avx -mattr=+avx -x86-experimental-vector-widening-legalization | FileCheck %s --check-prefix=CHECK-WIDE 4 5define <8 x float> @foo1_8(<8 x i8> %src) { 6; CHECK-LABEL: foo1_8: 7; CHECK: ## BB#0: 8; CHECK-NEXT: vpunpckhwd {{.*#+}} xmm1 = xmm0[4,4,5,5,6,6,7,7] 9; CHECK-NEXT: vpmovzxwd {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero 10; CHECK-NEXT: vpslld $24, %xmm0, %xmm0 11; CHECK-NEXT: vpsrad $24, %xmm0, %xmm0 12; CHECK-NEXT: vpslld $24, %xmm1, %xmm1 13; CHECK-NEXT: vpsrad $24, %xmm1, %xmm1 14; CHECK-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0 15; CHECK-NEXT: vcvtdq2ps %ymm0, %ymm0 16; CHECK-NEXT: retl 17; 18; CHECK-WIDE-LABEL: foo1_8: 19; CHECK-WIDE: ## BB#0: 20; CHECK-WIDE-NEXT: vpmovsxbd %xmm0, %xmm1 21; CHECK-WIDE-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[1,1,2,3] 22; CHECK-WIDE-NEXT: vpmovsxbd %xmm0, %xmm0 23; CHECK-WIDE-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0 24; CHECK-WIDE-NEXT: vcvtdq2ps %ymm0, %ymm0 25; CHECK-WIDE-NEXT: retl 26 %res = sitofp <8 x i8> %src to <8 x float> 27 ret <8 x float> %res 28} 29 30define <4 x float> @foo1_4(<4 x i8> %src) { 31; CHECK-LABEL: foo1_4: 32; CHECK: ## BB#0: 33; CHECK-NEXT: vpslld $24, %xmm0, %xmm0 34; CHECK-NEXT: vpsrad $24, %xmm0, %xmm0 35; CHECK-NEXT: vcvtdq2ps %xmm0, %xmm0 36; CHECK-NEXT: retl 37; 38; CHECK-WIDE-LABEL: foo1_4: 39; CHECK-WIDE: ## BB#0: 40; CHECK-WIDE-NEXT: vpmovsxbd %xmm0, %xmm0 41; CHECK-WIDE-NEXT: vcvtdq2ps %xmm0, %xmm0 42; CHECK-WIDE-NEXT: retl 43 %res = sitofp <4 x i8> %src to <4 x float> 44 ret <4 x float> %res 45} 46 47define <8 x float> @foo2_8(<8 x i8> %src) { 48; CHECK-LABEL: foo2_8: 49; CHECK: ## BB#0: 50; CHECK-NEXT: vpand LCPI2_0, %xmm0, %xmm0 51; CHECK-NEXT: vpxor %xmm1, %xmm1, %xmm1 52; CHECK-NEXT: vpunpckhwd {{.*#+}} xmm1 = xmm0[4],xmm1[4],xmm0[5],xmm1[5],xmm0[6],xmm1[6],xmm0[7],xmm1[7] 53; CHECK-NEXT: vpmovzxwd {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero 54; CHECK-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0 55; CHECK-NEXT: vcvtdq2ps %ymm0, %ymm0 56; CHECK-NEXT: retl 57; 58; CHECK-WIDE-LABEL: foo2_8: 59; CHECK-WIDE: ## BB#0: 60; CHECK-WIDE-NEXT: vpmovzxbd {{.*#+}} xmm1 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero 61; CHECK-WIDE-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[1,1,2,3] 62; CHECK-WIDE-NEXT: vpmovzxbd {{.*#+}} xmm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero 63; CHECK-WIDE-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0 64; CHECK-WIDE-NEXT: vcvtdq2ps %ymm0, %ymm0 65; CHECK-WIDE-NEXT: retl 66 %res = uitofp <8 x i8> %src to <8 x float> 67 ret <8 x float> %res 68} 69 70define <4 x float> @foo2_4(<4 x i8> %src) { 71; CHECK-LABEL: foo2_4: 72; CHECK: ## BB#0: 73; CHECK-NEXT: vandps LCPI3_0, %xmm0, %xmm0 74; CHECK-NEXT: vcvtdq2ps %xmm0, %xmm0 75; CHECK-NEXT: retl 76; 77; CHECK-WIDE-LABEL: foo2_4: 78; CHECK-WIDE: ## BB#0: 79; CHECK-WIDE-NEXT: vpmovzxbd {{.*#+}} xmm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero 80; CHECK-WIDE-NEXT: vcvtdq2ps %xmm0, %xmm0 81; CHECK-WIDE-NEXT: retl 82 %res = uitofp <4 x i8> %src to <4 x float> 83 ret <4 x float> %res 84} 85 86define <8 x i8> @foo3_8(<8 x float> %src) { 87; CHECK-LABEL: foo3_8: 88; CHECK: ## BB#0: 89; CHECK-NEXT: vcvttps2dq %ymm0, %ymm0 90; CHECK-NEXT: vextractf128 $1, %ymm0, %xmm1 91; CHECK-NEXT: vmovdqa {{.*#+}} xmm2 = [0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15] 92; CHECK-NEXT: vpshufb %xmm2, %xmm1, %xmm1 93; CHECK-NEXT: vpshufb %xmm2, %xmm0, %xmm0 94; CHECK-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0] 95; CHECK-NEXT: vzeroupper 96; CHECK-NEXT: retl 97; 98; CHECK-WIDE-LABEL: foo3_8: 99; CHECK-WIDE: ## BB#0: 100; CHECK-WIDE-NEXT: vcvttss2si %xmm0, %eax 101; CHECK-WIDE-NEXT: vpinsrb $0, %eax, %xmm0, %xmm1 102; CHECK-WIDE-NEXT: vmovshdup {{.*#+}} xmm2 = xmm0[1,1,3,3] 103; CHECK-WIDE-NEXT: vcvttss2si %xmm2, %eax 104; CHECK-WIDE-NEXT: vpinsrb $1, %eax, %xmm1, %xmm1 105; CHECK-WIDE-NEXT: vpermilpd {{.*#+}} xmm2 = xmm0[1,0] 106; CHECK-WIDE-NEXT: vcvttss2si %xmm2, %eax 107; CHECK-WIDE-NEXT: vpinsrb $2, %eax, %xmm1, %xmm1 108; CHECK-WIDE-NEXT: vpermilps {{.*#+}} xmm2 = xmm0[3,1,2,3] 109; CHECK-WIDE-NEXT: vcvttss2si %xmm2, %eax 110; CHECK-WIDE-NEXT: vpinsrb $3, %eax, %xmm1, %xmm1 111; CHECK-WIDE-NEXT: vextractf128 $1, %ymm0, %xmm0 112; CHECK-WIDE-NEXT: vcvttss2si %xmm0, %eax 113; CHECK-WIDE-NEXT: vpinsrb $4, %eax, %xmm1, %xmm1 114; CHECK-WIDE-NEXT: vmovshdup {{.*#+}} xmm2 = xmm0[1,1,3,3] 115; CHECK-WIDE-NEXT: vcvttss2si %xmm2, %eax 116; CHECK-WIDE-NEXT: vpinsrb $5, %eax, %xmm1, %xmm1 117; CHECK-WIDE-NEXT: vpermilpd {{.*#+}} xmm2 = xmm0[1,0] 118; CHECK-WIDE-NEXT: vcvttss2si %xmm2, %eax 119; CHECK-WIDE-NEXT: vpinsrb $6, %eax, %xmm1, %xmm1 120; CHECK-WIDE-NEXT: vpermilps {{.*#+}} xmm0 = xmm0[3,1,2,3] 121; CHECK-WIDE-NEXT: vcvttss2si %xmm0, %eax 122; CHECK-WIDE-NEXT: vpinsrb $7, %eax, %xmm1, %xmm0 123; CHECK-WIDE-NEXT: vzeroupper 124; CHECK-WIDE-NEXT: retl 125 %res = fptosi <8 x float> %src to <8 x i8> 126 ret <8 x i8> %res 127} 128 129define <4 x i8> @foo3_4(<4 x float> %src) { 130; CHECK-LABEL: foo3_4: 131; CHECK: ## BB#0: 132; CHECK-NEXT: vcvttps2dq %xmm0, %xmm0 133; CHECK-NEXT: retl 134; 135; CHECK-WIDE-LABEL: foo3_4: 136; CHECK-WIDE: ## BB#0: 137; CHECK-WIDE-NEXT: vcvttss2si %xmm0, %eax 138; CHECK-WIDE-NEXT: vpinsrb $0, %eax, %xmm0, %xmm1 139; CHECK-WIDE-NEXT: vmovshdup {{.*#+}} xmm2 = xmm0[1,1,3,3] 140; CHECK-WIDE-NEXT: vcvttss2si %xmm2, %eax 141; CHECK-WIDE-NEXT: vpinsrb $1, %eax, %xmm1, %xmm1 142; CHECK-WIDE-NEXT: vpermilpd {{.*#+}} xmm2 = xmm0[1,0] 143; CHECK-WIDE-NEXT: vcvttss2si %xmm2, %eax 144; CHECK-WIDE-NEXT: vpinsrb $2, %eax, %xmm1, %xmm1 145; CHECK-WIDE-NEXT: vpermilps {{.*#+}} xmm0 = xmm0[3,1,2,3] 146; CHECK-WIDE-NEXT: vcvttss2si %xmm0, %eax 147; CHECK-WIDE-NEXT: vpinsrb $3, %eax, %xmm1, %xmm0 148; CHECK-WIDE-NEXT: retl 149 %res = fptosi <4 x float> %src to <4 x i8> 150 ret <4 x i8> %res 151} 152 153