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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc < %s -mcpu=x86-64 -mattr=-sse2 | FileCheck %s --check-prefix=SSE1
3
4target triple = "x86_64-unknown-unknown"
5
6define <4 x float> @shuffle_v4f32_0001(<4 x float> %a, <4 x float> %b) {
7; SSE1-LABEL: shuffle_v4f32_0001:
8; SSE1:       # BB#0:
9; SSE1-NEXT:    shufps {{.*#+}} xmm0 = xmm0[0,0,0,1]
10; SSE1-NEXT:    retq
11  %shuffle = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 0, i32 0, i32 0, i32 1>
12  ret <4 x float> %shuffle
13}
14define <4 x float> @shuffle_v4f32_0020(<4 x float> %a, <4 x float> %b) {
15; SSE1-LABEL: shuffle_v4f32_0020:
16; SSE1:       # BB#0:
17; SSE1-NEXT:    shufps {{.*#+}} xmm0 = xmm0[0,0,2,0]
18; SSE1-NEXT:    retq
19  %shuffle = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 0, i32 0, i32 2, i32 0>
20  ret <4 x float> %shuffle
21}
22define <4 x float> @shuffle_v4f32_0300(<4 x float> %a, <4 x float> %b) {
23; SSE1-LABEL: shuffle_v4f32_0300:
24; SSE1:       # BB#0:
25; SSE1-NEXT:    shufps {{.*#+}} xmm0 = xmm0[0,3,0,0]
26; SSE1-NEXT:    retq
27  %shuffle = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 0, i32 3, i32 0, i32 0>
28  ret <4 x float> %shuffle
29}
30define <4 x float> @shuffle_v4f32_1000(<4 x float> %a, <4 x float> %b) {
31; SSE1-LABEL: shuffle_v4f32_1000:
32; SSE1:       # BB#0:
33; SSE1-NEXT:    shufps {{.*#+}} xmm0 = xmm0[1,0,0,0]
34; SSE1-NEXT:    retq
35  %shuffle = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 1, i32 0, i32 0, i32 0>
36  ret <4 x float> %shuffle
37}
38define <4 x float> @shuffle_v4f32_2200(<4 x float> %a, <4 x float> %b) {
39; SSE1-LABEL: shuffle_v4f32_2200:
40; SSE1:       # BB#0:
41; SSE1-NEXT:    shufps {{.*#+}} xmm0 = xmm0[2,2,0,0]
42; SSE1-NEXT:    retq
43  %shuffle = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 2, i32 2, i32 0, i32 0>
44  ret <4 x float> %shuffle
45}
46define <4 x float> @shuffle_v4f32_3330(<4 x float> %a, <4 x float> %b) {
47; SSE1-LABEL: shuffle_v4f32_3330:
48; SSE1:       # BB#0:
49; SSE1-NEXT:    shufps {{.*#+}} xmm0 = xmm0[3,3,3,0]
50; SSE1-NEXT:    retq
51  %shuffle = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 3, i32 3, i32 3, i32 0>
52  ret <4 x float> %shuffle
53}
54define <4 x float> @shuffle_v4f32_3210(<4 x float> %a, <4 x float> %b) {
55; SSE1-LABEL: shuffle_v4f32_3210:
56; SSE1:       # BB#0:
57; SSE1-NEXT:    shufps {{.*#+}} xmm0 = xmm0[3,2,1,0]
58; SSE1-NEXT:    retq
59  %shuffle = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
60  ret <4 x float> %shuffle
61}
62define <4 x float> @shuffle_v4f32_0011(<4 x float> %a, <4 x float> %b) {
63; SSE1-LABEL: shuffle_v4f32_0011:
64; SSE1:       # BB#0:
65; SSE1-NEXT:    unpcklps {{.*#+}} xmm0 = xmm0[0,0,1,1]
66; SSE1-NEXT:    retq
67  %shuffle = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 0, i32 0, i32 1, i32 1>
68  ret <4 x float> %shuffle
69}
70define <4 x float> @shuffle_v4f32_2233(<4 x float> %a, <4 x float> %b) {
71; SSE1-LABEL: shuffle_v4f32_2233:
72; SSE1:       # BB#0:
73; SSE1-NEXT:    unpckhps {{.*#+}} xmm0 = xmm0[2,2,3,3]
74; SSE1-NEXT:    retq
75  %shuffle = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 2, i32 2, i32 3, i32 3>
76  ret <4 x float> %shuffle
77}
78define <4 x float> @shuffle_v4f32_0022(<4 x float> %a, <4 x float> %b) {
79; SSE1-LABEL: shuffle_v4f32_0022:
80; SSE1:       # BB#0:
81; SSE1-NEXT:    shufps {{.*#+}} xmm0 = xmm0[0,0,2,2]
82; SSE1-NEXT:    retq
83  %shuffle = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 0, i32 0, i32 2, i32 2>
84  ret <4 x float> %shuffle
85}
86define <4 x float> @shuffle_v4f32_1133(<4 x float> %a, <4 x float> %b) {
87; SSE1-LABEL: shuffle_v4f32_1133:
88; SSE1:       # BB#0:
89; SSE1-NEXT:    shufps {{.*#+}} xmm0 = xmm0[1,1,3,3]
90; SSE1-NEXT:    retq
91  %shuffle = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 1, i32 1, i32 3, i32 3>
92  ret <4 x float> %shuffle
93}
94define <4 x float> @shuffle_v4f32_0145(<4 x float> %a, <4 x float> %b) {
95; SSE1-LABEL: shuffle_v4f32_0145:
96; SSE1:       # BB#0:
97; SSE1-NEXT:    movlhps {{.*#+}} xmm0 = xmm0[0],xmm1[0]
98; SSE1-NEXT:    retq
99  %shuffle = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 0, i32 1, i32 4, i32 5>
100  ret <4 x float> %shuffle
101}
102define <4 x float> @shuffle_v4f32_6723(<4 x float> %a, <4 x float> %b) {
103; SSE1-LABEL: shuffle_v4f32_6723:
104; SSE1:       # BB#0:
105; SSE1-NEXT:    movhlps {{.*#+}} xmm0 = xmm1[1],xmm0[1]
106; SSE1-NEXT:    retq
107  %shuffle = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 6, i32 7, i32 2, i32 3>
108  ret <4 x float> %shuffle
109}
110
111define <4 x float> @shuffle_v4f32_4zzz(<4 x float> %a) {
112; SSE1-LABEL: shuffle_v4f32_4zzz:
113; SSE1:       # BB#0:
114; SSE1-NEXT:    xorps %xmm1, %xmm1
115; SSE1-NEXT:    movss {{.*#+}} xmm1 = xmm0[0],xmm1[1,2,3]
116; SSE1-NEXT:    movaps %xmm1, %xmm0
117; SSE1-NEXT:    retq
118  %shuffle = shufflevector <4 x float> zeroinitializer, <4 x float> %a, <4 x i32> <i32 4, i32 1, i32 2, i32 3>
119  ret <4 x float> %shuffle
120}
121
122define <4 x float> @shuffle_v4f32_z4zz(<4 x float> %a) {
123; SSE1-LABEL: shuffle_v4f32_z4zz:
124; SSE1:       # BB#0:
125; SSE1-NEXT:    xorps %xmm1, %xmm1
126; SSE1-NEXT:    shufps {{.*#+}} xmm0 = xmm0[0,0],xmm1[0,0]
127; SSE1-NEXT:    shufps {{.*#+}} xmm0 = xmm0[2,0],xmm1[2,3]
128; SSE1-NEXT:    retq
129  %shuffle = shufflevector <4 x float> zeroinitializer, <4 x float> %a, <4 x i32> <i32 2, i32 4, i32 3, i32 0>
130  ret <4 x float> %shuffle
131}
132
133define <4 x float> @shuffle_v4f32_zz4z(<4 x float> %a) {
134; SSE1-LABEL: shuffle_v4f32_zz4z:
135; SSE1:       # BB#0:
136; SSE1-NEXT:    xorps %xmm1, %xmm1
137; SSE1-NEXT:    shufps {{.*#+}} xmm0 = xmm0[0,0],xmm1[3,0]
138; SSE1-NEXT:    shufps {{.*#+}} xmm1 = xmm1[0,1],xmm0[0,2]
139; SSE1-NEXT:    movaps %xmm1, %xmm0
140; SSE1-NEXT:    retq
141  %shuffle = shufflevector <4 x float> zeroinitializer, <4 x float> %a, <4 x i32> <i32 0, i32 0, i32 4, i32 0>
142  ret <4 x float> %shuffle
143}
144
145define <4 x float> @shuffle_v4f32_zuu4(<4 x float> %a) {
146; SSE1-LABEL: shuffle_v4f32_zuu4:
147; SSE1:       # BB#0:
148; SSE1-NEXT:    xorps %xmm1, %xmm1
149; SSE1-NEXT:    shufps {{.*#+}} xmm1 = xmm1[0,1],xmm0[2,0]
150; SSE1-NEXT:    movaps %xmm1, %xmm0
151; SSE1-NEXT:    retq
152  %shuffle = shufflevector <4 x float> zeroinitializer, <4 x float> %a, <4 x i32> <i32 0, i32 undef, i32 undef, i32 4>
153  ret <4 x float> %shuffle
154}
155
156define <4 x float> @shuffle_v4f32_zzz7(<4 x float> %a) {
157; SSE1-LABEL: shuffle_v4f32_zzz7:
158; SSE1:       # BB#0:
159; SSE1-NEXT:    xorps %xmm1, %xmm1
160; SSE1-NEXT:    shufps {{.*#+}} xmm0 = xmm0[3,0],xmm1[2,0]
161; SSE1-NEXT:    shufps {{.*#+}} xmm1 = xmm1[0,1],xmm0[2,0]
162; SSE1-NEXT:    movaps %xmm1, %xmm0
163; SSE1-NEXT:    retq
164  %shuffle = shufflevector <4 x float> zeroinitializer, <4 x float> %a, <4 x i32> <i32 0, i32 1, i32 2, i32 7>
165  ret <4 x float> %shuffle
166}
167
168define <4 x float> @shuffle_v4f32_z6zz(<4 x float> %a) {
169; SSE1-LABEL: shuffle_v4f32_z6zz:
170; SSE1:       # BB#0:
171; SSE1-NEXT:    xorps %xmm1, %xmm1
172; SSE1-NEXT:    shufps {{.*#+}} xmm0 = xmm0[2,0],xmm1[0,0]
173; SSE1-NEXT:    shufps {{.*#+}} xmm0 = xmm0[2,0],xmm1[2,3]
174; SSE1-NEXT:    retq
175  %shuffle = shufflevector <4 x float> zeroinitializer, <4 x float> %a, <4 x i32> <i32 0, i32 6, i32 2, i32 3>
176  ret <4 x float> %shuffle
177}
178
179define <4 x float> @insert_reg_and_zero_v4f32(float %a) {
180; SSE1-LABEL: insert_reg_and_zero_v4f32:
181; SSE1:       # BB#0:
182; SSE1-NEXT:    xorps %xmm1, %xmm1
183; SSE1-NEXT:    movss {{.*#+}} xmm1 = xmm0[0],xmm1[1,2,3]
184; SSE1-NEXT:    movaps %xmm1, %xmm0
185; SSE1-NEXT:    retq
186  %v = insertelement <4 x float> undef, float %a, i32 0
187  %shuffle = shufflevector <4 x float> %v, <4 x float> zeroinitializer, <4 x i32> <i32 0, i32 5, i32 6, i32 7>
188  ret <4 x float> %shuffle
189}
190
191define <4 x float> @insert_mem_and_zero_v4f32(float* %ptr) {
192; SSE1-LABEL: insert_mem_and_zero_v4f32:
193; SSE1:       # BB#0:
194; SSE1-NEXT:    movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
195; SSE1-NEXT:    retq
196  %a = load float, float* %ptr
197  %v = insertelement <4 x float> undef, float %a, i32 0
198  %shuffle = shufflevector <4 x float> %v, <4 x float> zeroinitializer, <4 x i32> <i32 0, i32 5, i32 6, i32 7>
199  ret <4 x float> %shuffle
200}
201
202define <4 x float> @insert_mem_lo_v4f32(<2 x float>* %ptr, <4 x float> %b) {
203; SSE1-LABEL: insert_mem_lo_v4f32:
204; SSE1:       # BB#0:
205; SSE1-NEXT:    movq (%rdi), %rax
206; SSE1-NEXT:    movl %eax, -{{[0-9]+}}(%rsp)
207; SSE1-NEXT:    shrq $32, %rax
208; SSE1-NEXT:    movl %eax, -{{[0-9]+}}(%rsp)
209; SSE1-NEXT:    movss {{.*#+}} xmm1 = mem[0],zero,zero,zero
210; SSE1-NEXT:    movss {{.*#+}} xmm2 = mem[0],zero,zero,zero
211; SSE1-NEXT:    unpcklps {{.*#+}} xmm1 = xmm1[0],xmm2[0],xmm1[1],xmm2[1]
212; SSE1-NEXT:    xorps %xmm2, %xmm2
213; SSE1-NEXT:    movlhps {{.*#+}} xmm1 = xmm1[0],xmm2[0]
214; SSE1-NEXT:    shufps {{.*#+}} xmm1 = xmm1[0,1],xmm0[2,3]
215; SSE1-NEXT:    movaps %xmm1, %xmm0
216; SSE1-NEXT:    retq
217  %a = load <2 x float>, <2 x float>* %ptr
218  %v = shufflevector <2 x float> %a, <2 x float> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef>
219  %shuffle = shufflevector <4 x float> %v, <4 x float> %b, <4 x i32> <i32 0, i32 1, i32 6, i32 7>
220  ret <4 x float> %shuffle
221}
222
223define <4 x float> @insert_mem_hi_v4f32(<2 x float>* %ptr, <4 x float> %b) {
224; SSE1-LABEL: insert_mem_hi_v4f32:
225; SSE1:       # BB#0:
226; SSE1-NEXT:    movq (%rdi), %rax
227; SSE1-NEXT:    movl %eax, -{{[0-9]+}}(%rsp)
228; SSE1-NEXT:    shrq $32, %rax
229; SSE1-NEXT:    movl %eax, -{{[0-9]+}}(%rsp)
230; SSE1-NEXT:    movss {{.*#+}} xmm1 = mem[0],zero,zero,zero
231; SSE1-NEXT:    movss {{.*#+}} xmm2 = mem[0],zero,zero,zero
232; SSE1-NEXT:    unpcklps {{.*#+}} xmm1 = xmm1[0],xmm2[0],xmm1[1],xmm2[1]
233; SSE1-NEXT:    xorps %xmm2, %xmm2
234; SSE1-NEXT:    movlhps {{.*#+}} xmm1 = xmm1[0],xmm2[0]
235; SSE1-NEXT:    movlhps {{.*#+}} xmm0 = xmm0[0],xmm1[0]
236; SSE1-NEXT:    retq
237  %a = load <2 x float>, <2 x float>* %ptr
238  %v = shufflevector <2 x float> %a, <2 x float> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef>
239  %shuffle = shufflevector <4 x float> %v, <4 x float> %b, <4 x i32> <i32 4, i32 5, i32 0, i32 1>
240  ret <4 x float> %shuffle
241}
242
243define <4 x float> @shuffle_mem_v4f32_3210(<4 x float>* %ptr) {
244; SSE1-LABEL: shuffle_mem_v4f32_3210:
245; SSE1:       # BB#0:
246; SSE1-NEXT:    movaps (%rdi), %xmm0
247; SSE1-NEXT:    shufps {{.*#+}} xmm0 = xmm0[3,2,1,0]
248; SSE1-NEXT:    retq
249  %a = load <4 x float>, <4 x float>* %ptr
250  %shuffle = shufflevector <4 x float> %a, <4 x float> undef, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
251  ret <4 x float> %shuffle
252}
253define <4 x float> @shuffle_mem_v4f32_0145(<4 x float> %a, <4 x float>* %pb) {
254; SSE1-LABEL: shuffle_mem_v4f32_0145:
255; SSE1:       # BB#0:
256; SSE1-NEXT:    movhps (%rdi), %xmm0
257; SSE1-NEXT:    retq
258  %b = load <4 x float>, <4 x float>* %pb, align 16
259  %shuffle = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 0, i32 1, i32 4, i32 5>
260  ret <4 x float> %shuffle
261}
262define <4 x float> @shuffle_mem_v4f32_6723(<4 x float> %a, <4 x float>* %pb) {
263; SSE1-LABEL: shuffle_mem_v4f32_6723:
264; SSE1:       # BB#0:
265; SSE1-NEXT:    movlps 8(%rdi), %xmm0
266; SSE1-NEXT:    retq
267  %b = load <4 x float>, <4 x float>* %pb, align 16
268  %shuffle = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 6, i32 7, i32 2, i32 3>
269  ret <4 x float> %shuffle
270}
271