1// RUN: llvm-tblgen %s | FileCheck %s 2// XFAIL: vg_leak 3 4class ValueType<int size, int value> { 5 int Size = size; 6 int Value = value; 7} 8 9def f32 : ValueType<32, 1>; // 2 x i64 vector value 10 11class Intrinsic<string name> { 12 string Name = name; 13} 14 15class Inst<bits<8> opcode, dag oopnds, dag iopnds, string asmstr, 16 list<dag> pattern> { 17 bits<8> Opcode = opcode; 18 dag OutOperands = oopnds; 19 dag InOperands = iopnds; 20 string AssemblyString = asmstr; 21 list<dag> Pattern = pattern; 22} 23 24def ops; 25def outs; 26def ins; 27 28def set; 29 30// Define registers 31class Register<string n> { 32 string Name = n; 33} 34 35class RegisterClass<list<ValueType> regTypes, list<Register> regList> { 36 list<ValueType> RegTypes = regTypes; 37 list<Register> MemberList = regList; 38} 39 40def XMM0: Register<"xmm0">; 41def XMM1: Register<"xmm1">; 42def XMM2: Register<"xmm2">; 43def XMM3: Register<"xmm3">; 44def XMM4: Register<"xmm4">; 45def XMM5: Register<"xmm5">; 46def XMM6: Register<"xmm6">; 47def XMM7: Register<"xmm7">; 48def XMM8: Register<"xmm8">; 49def XMM9: Register<"xmm9">; 50def XMM10: Register<"xmm10">; 51def XMM11: Register<"xmm11">; 52def XMM12: Register<"xmm12">; 53def XMM13: Register<"xmm13">; 54def XMM14: Register<"xmm14">; 55def XMM15: Register<"xmm15">; 56 57def FR32 : RegisterClass<[f32], 58 [XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7, 59 XMM8, XMM9, XMM10, XMM11, 60 XMM12, XMM13, XMM14, XMM15]>; 61 62class SDNode {} 63def not : SDNode; 64 65multiclass scalar<bits<8> opcode, string asmstr = "", list<list<dag>> patterns = []> { 66 def SSrr : Inst<opcode, (outs FR32:$dst), (ins FR32:$src), 67 !strconcat(asmstr, "\t$dst, $src"), 68 !if(!empty(patterns),[]<dag>,patterns[0])>; 69 def SSrm : Inst<opcode, (outs FR32:$dst), (ins FR32:$src), 70 !strconcat(asmstr, "\t$dst, $src"), 71 !if(!empty(patterns),[]<dag>,!if(!empty(!tail(patterns)),patterns[0],patterns[1]))>; 72} 73 74multiclass vscalar<bits<8> opcode, string asmstr = "", list<list<dag>> patterns = []> { 75 def V#NAME#SSrr : Inst<opcode, (outs FR32:$dst), (ins FR32:$src), 76 !strconcat(asmstr, "\t$dst, $src"), 77 !if(!empty(patterns),[]<dag>,patterns[0])>; 78 def V#NAME#SSrm : Inst<opcode, (outs FR32:$dst), (ins FR32:$src), 79 !strconcat(asmstr, "\t$dst, $src"), 80 !if(!empty(patterns),[]<dag>,!if(!empty(!tail(patterns)),patterns[0],patterns[1]))>; 81} 82 83multiclass myscalar<bits<8> opcode, string asmstr = "", list<list<dag>> patterns = []> : 84 scalar<opcode, asmstr, patterns>, 85 vscalar<opcode, asmstr, patterns>; 86 87defm NOT : myscalar<0x10, "not", [[], [(set FR32:$dst, (f32 (not FR32:$src)))]]>; 88 89// CHECK: Pattern = [(set FR32:$dst, (f32 (not FR32:$src)))]; 90// CHECK: Pattern = []; 91// CHECK: Pattern = [(set FR32:$dst, (f32 (not FR32:$src)))]; 92// CHECK: Pattern = []; 93