1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23 #include "r600_pipe.h"
24 #include "r600_public.h"
25 #include "r600_isa.h"
26 #include "evergreen_compute.h"
27 #include "r600d.h"
28
29 #include "sb/sb_public.h"
30
31 #include <errno.h>
32 #include "pipe/p_shader_tokens.h"
33 #include "util/u_debug.h"
34 #include "util/u_memory.h"
35 #include "util/u_simple_shaders.h"
36 #include "util/u_upload_mgr.h"
37 #include "util/u_math.h"
38 #include "vl/vl_decoder.h"
39 #include "vl/vl_video_buffer.h"
40 #include "radeon/radeon_video.h"
41 #include "radeon/radeon_uvd.h"
42 #include "os/os_time.h"
43
44 static const struct debug_named_value r600_debug_options[] = {
45 /* features */
46 { "nocpdma", DBG_NO_CP_DMA, "Disable CP DMA" },
47
48 /* shader backend */
49 { "nosb", DBG_NO_SB, "Disable sb backend for graphics shaders" },
50 { "sbcl", DBG_SB_CS, "Enable sb backend for compute shaders" },
51 { "sbdry", DBG_SB_DRY_RUN, "Don't use optimized bytecode (just print the dumps)" },
52 { "sbstat", DBG_SB_STAT, "Print optimization statistics for shaders" },
53 { "sbdump", DBG_SB_DUMP, "Print IR dumps after some optimization passes" },
54 { "sbnofallback", DBG_SB_NO_FALLBACK, "Abort on errors instead of fallback" },
55 { "sbdisasm", DBG_SB_DISASM, "Use sb disassembler for shader dumps" },
56 { "sbsafemath", DBG_SB_SAFEMATH, "Disable unsafe math optimizations" },
57
58 DEBUG_NAMED_VALUE_END /* must be last */
59 };
60
61 /*
62 * pipe_context
63 */
64
r600_destroy_context(struct pipe_context * context)65 static void r600_destroy_context(struct pipe_context *context)
66 {
67 struct r600_context *rctx = (struct r600_context *)context;
68 unsigned sh;
69
70 r600_isa_destroy(rctx->isa);
71
72 r600_sb_context_destroy(rctx->sb_context);
73
74 r600_resource_reference(&rctx->dummy_cmask, NULL);
75 r600_resource_reference(&rctx->dummy_fmask, NULL);
76
77 for (sh = 0; sh < PIPE_SHADER_TYPES; sh++) {
78 rctx->b.b.set_constant_buffer(&rctx->b.b, sh, R600_BUFFER_INFO_CONST_BUFFER, NULL);
79 free(rctx->driver_consts[sh].constants);
80 }
81
82 if (rctx->fixed_func_tcs_shader)
83 rctx->b.b.delete_tcs_state(&rctx->b.b, rctx->fixed_func_tcs_shader);
84
85 if (rctx->dummy_pixel_shader) {
86 rctx->b.b.delete_fs_state(&rctx->b.b, rctx->dummy_pixel_shader);
87 }
88 if (rctx->custom_dsa_flush) {
89 rctx->b.b.delete_depth_stencil_alpha_state(&rctx->b.b, rctx->custom_dsa_flush);
90 }
91 if (rctx->custom_blend_resolve) {
92 rctx->b.b.delete_blend_state(&rctx->b.b, rctx->custom_blend_resolve);
93 }
94 if (rctx->custom_blend_decompress) {
95 rctx->b.b.delete_blend_state(&rctx->b.b, rctx->custom_blend_decompress);
96 }
97 if (rctx->custom_blend_fastclear) {
98 rctx->b.b.delete_blend_state(&rctx->b.b, rctx->custom_blend_fastclear);
99 }
100 util_unreference_framebuffer_state(&rctx->framebuffer.state);
101
102 if (rctx->blitter) {
103 util_blitter_destroy(rctx->blitter);
104 }
105 if (rctx->allocator_fetch_shader) {
106 u_suballocator_destroy(rctx->allocator_fetch_shader);
107 }
108
109 r600_release_command_buffer(&rctx->start_cs_cmd);
110
111 FREE(rctx->start_compute_cs_cmd.buf);
112
113 r600_common_context_cleanup(&rctx->b);
114 FREE(rctx);
115 }
116
r600_create_context(struct pipe_screen * screen,void * priv,unsigned flags)117 static struct pipe_context *r600_create_context(struct pipe_screen *screen,
118 void *priv, unsigned flags)
119 {
120 struct r600_context *rctx = CALLOC_STRUCT(r600_context);
121 struct r600_screen* rscreen = (struct r600_screen *)screen;
122 struct radeon_winsys *ws = rscreen->b.ws;
123
124 if (!rctx)
125 return NULL;
126
127 rctx->b.b.screen = screen;
128 rctx->b.b.priv = priv;
129 rctx->b.b.destroy = r600_destroy_context;
130 rctx->b.set_atom_dirty = (void *)r600_set_atom_dirty;
131
132 if (!r600_common_context_init(&rctx->b, &rscreen->b, flags))
133 goto fail;
134
135 rctx->screen = rscreen;
136 LIST_INITHEAD(&rctx->texture_buffers);
137
138 r600_init_blit_functions(rctx);
139
140 if (rscreen->b.info.has_uvd) {
141 rctx->b.b.create_video_codec = r600_uvd_create_decoder;
142 rctx->b.b.create_video_buffer = r600_video_buffer_create;
143 } else {
144 rctx->b.b.create_video_codec = vl_create_decoder;
145 rctx->b.b.create_video_buffer = vl_video_buffer_create;
146 }
147
148 r600_init_common_state_functions(rctx);
149
150 switch (rctx->b.chip_class) {
151 case R600:
152 case R700:
153 r600_init_state_functions(rctx);
154 r600_init_atom_start_cs(rctx);
155 rctx->custom_dsa_flush = r600_create_db_flush_dsa(rctx);
156 rctx->custom_blend_resolve = rctx->b.chip_class == R700 ? r700_create_resolve_blend(rctx)
157 : r600_create_resolve_blend(rctx);
158 rctx->custom_blend_decompress = r600_create_decompress_blend(rctx);
159 rctx->has_vertex_cache = !(rctx->b.family == CHIP_RV610 ||
160 rctx->b.family == CHIP_RV620 ||
161 rctx->b.family == CHIP_RS780 ||
162 rctx->b.family == CHIP_RS880 ||
163 rctx->b.family == CHIP_RV710);
164 break;
165 case EVERGREEN:
166 case CAYMAN:
167 evergreen_init_state_functions(rctx);
168 evergreen_init_atom_start_cs(rctx);
169 evergreen_init_atom_start_compute_cs(rctx);
170 rctx->custom_dsa_flush = evergreen_create_db_flush_dsa(rctx);
171 rctx->custom_blend_resolve = evergreen_create_resolve_blend(rctx);
172 rctx->custom_blend_decompress = evergreen_create_decompress_blend(rctx);
173 rctx->custom_blend_fastclear = evergreen_create_fastclear_blend(rctx);
174 rctx->has_vertex_cache = !(rctx->b.family == CHIP_CEDAR ||
175 rctx->b.family == CHIP_PALM ||
176 rctx->b.family == CHIP_SUMO ||
177 rctx->b.family == CHIP_SUMO2 ||
178 rctx->b.family == CHIP_CAICOS ||
179 rctx->b.family == CHIP_CAYMAN ||
180 rctx->b.family == CHIP_ARUBA);
181 break;
182 default:
183 R600_ERR("Unsupported chip class %d.\n", rctx->b.chip_class);
184 goto fail;
185 }
186
187 rctx->b.gfx.cs = ws->cs_create(rctx->b.ctx, RING_GFX,
188 r600_context_gfx_flush, rctx);
189 rctx->b.gfx.flush = r600_context_gfx_flush;
190
191 rctx->allocator_fetch_shader = u_suballocator_create(&rctx->b.b, 64 * 1024,
192 0, PIPE_USAGE_DEFAULT, FALSE);
193 if (!rctx->allocator_fetch_shader)
194 goto fail;
195
196 rctx->isa = calloc(1, sizeof(struct r600_isa));
197 if (!rctx->isa || r600_isa_init(rctx, rctx->isa))
198 goto fail;
199
200 if (rscreen->b.debug_flags & DBG_FORCE_DMA)
201 rctx->b.b.resource_copy_region = rctx->b.dma_copy;
202
203 rctx->blitter = util_blitter_create(&rctx->b.b);
204 if (rctx->blitter == NULL)
205 goto fail;
206 util_blitter_set_texture_multisample(rctx->blitter, rscreen->has_msaa);
207 rctx->blitter->draw_rectangle = r600_draw_rectangle;
208
209 r600_begin_new_cs(rctx);
210 r600_query_init_backend_mask(&rctx->b); /* this emits commands and must be last */
211
212 rctx->dummy_pixel_shader =
213 util_make_fragment_cloneinput_shader(&rctx->b.b, 0,
214 TGSI_SEMANTIC_GENERIC,
215 TGSI_INTERPOLATE_CONSTANT);
216 rctx->b.b.bind_fs_state(&rctx->b.b, rctx->dummy_pixel_shader);
217
218 return &rctx->b.b;
219
220 fail:
221 r600_destroy_context(&rctx->b.b);
222 return NULL;
223 }
224
225 /*
226 * pipe_screen
227 */
228
r600_get_param(struct pipe_screen * pscreen,enum pipe_cap param)229 static int r600_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
230 {
231 struct r600_screen *rscreen = (struct r600_screen *)pscreen;
232 enum radeon_family family = rscreen->b.family;
233
234 switch (param) {
235 /* Supported features (boolean caps). */
236 case PIPE_CAP_NPOT_TEXTURES:
237 case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
238 case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
239 case PIPE_CAP_TWO_SIDED_STENCIL:
240 case PIPE_CAP_ANISOTROPIC_FILTER:
241 case PIPE_CAP_POINT_SPRITE:
242 case PIPE_CAP_OCCLUSION_QUERY:
243 case PIPE_CAP_TEXTURE_SHADOW_MAP:
244 case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
245 case PIPE_CAP_BLEND_EQUATION_SEPARATE:
246 case PIPE_CAP_TEXTURE_SWIZZLE:
247 case PIPE_CAP_DEPTH_CLIP_DISABLE:
248 case PIPE_CAP_SHADER_STENCIL_EXPORT:
249 case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
250 case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
251 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
252 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
253 case PIPE_CAP_SM3:
254 case PIPE_CAP_SEAMLESS_CUBE_MAP:
255 case PIPE_CAP_PRIMITIVE_RESTART:
256 case PIPE_CAP_CONDITIONAL_RENDER:
257 case PIPE_CAP_TEXTURE_BARRIER:
258 case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
259 case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
260 case PIPE_CAP_TGSI_INSTANCEID:
261 case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
262 case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
263 case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
264 case PIPE_CAP_USER_INDEX_BUFFERS:
265 case PIPE_CAP_USER_CONSTANT_BUFFERS:
266 case PIPE_CAP_START_INSTANCE:
267 case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
268 case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
269 case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
270 case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
271 case PIPE_CAP_TEXTURE_MULTISAMPLE:
272 case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
273 case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
274 case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
275 case PIPE_CAP_SAMPLE_SHADING:
276 case PIPE_CAP_CLIP_HALFZ:
277 case PIPE_CAP_POLYGON_OFFSET_CLAMP:
278 case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
279 case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
280 case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
281 case PIPE_CAP_TGSI_TXQS:
282 case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
283 case PIPE_CAP_INVALIDATE_BUFFER:
284 case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
285 case PIPE_CAP_QUERY_MEMORY_INFO:
286 case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
287 case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED:
288 case PIPE_CAP_CLEAR_TEXTURE:
289 return 1;
290
291 case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
292 return rscreen->b.info.drm_major == 2 && rscreen->b.info.drm_minor >= 43;
293
294 case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
295 return !R600_BIG_ENDIAN && rscreen->b.info.has_userptr;
296
297 case PIPE_CAP_COMPUTE:
298 return rscreen->b.chip_class > R700;
299
300 case PIPE_CAP_TGSI_TEXCOORD:
301 return 0;
302
303 case PIPE_CAP_FAKE_SW_MSAA:
304 return 0;
305
306 case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
307 return MIN2(rscreen->b.info.max_alloc_size, INT_MAX);
308
309 case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
310 return R600_MAP_BUFFER_ALIGNMENT;
311
312 case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
313 return 256;
314
315 case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
316 return 1;
317
318 case PIPE_CAP_GLSL_FEATURE_LEVEL:
319 if (family >= CHIP_CEDAR)
320 return 410;
321 /* pre-evergreen geom shaders need newer kernel */
322 if (rscreen->b.info.drm_minor >= 37)
323 return 330;
324 return 140;
325
326 /* Supported except the original R600. */
327 case PIPE_CAP_INDEP_BLEND_ENABLE:
328 case PIPE_CAP_INDEP_BLEND_FUNC:
329 /* R600 doesn't support per-MRT blends */
330 return family == CHIP_R600 ? 0 : 1;
331
332 /* Supported on Evergreen. */
333 case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
334 case PIPE_CAP_CUBE_MAP_ARRAY:
335 case PIPE_CAP_TEXTURE_GATHER_SM5:
336 case PIPE_CAP_TEXTURE_QUERY_LOD:
337 case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
338 case PIPE_CAP_SAMPLER_VIEW_TARGET:
339 case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
340 return family >= CHIP_CEDAR ? 1 : 0;
341 case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
342 return family >= CHIP_CEDAR ? 4 : 0;
343 case PIPE_CAP_DRAW_INDIRECT:
344 /* kernel command checker support is also required */
345 return family >= CHIP_CEDAR && rscreen->b.info.drm_minor >= 41;
346
347 case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
348 return family >= CHIP_CEDAR ? 0 : 1;
349
350 /* Unsupported features. */
351 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
352 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
353 case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
354 case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
355 case PIPE_CAP_VERTEX_COLOR_CLAMPED:
356 case PIPE_CAP_USER_VERTEX_BUFFERS:
357 case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
358 case PIPE_CAP_VERTEXID_NOBASE:
359 case PIPE_CAP_DEPTH_BOUNDS_TEST:
360 case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
361 case PIPE_CAP_SHAREABLE_SHADERS:
362 case PIPE_CAP_DRAW_PARAMETERS:
363 case PIPE_CAP_MULTI_DRAW_INDIRECT:
364 case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
365 case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
366 case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
367 case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
368 case PIPE_CAP_GENERATE_MIPMAP:
369 case PIPE_CAP_STRING_MARKER:
370 case PIPE_CAP_QUERY_BUFFER_OBJECT:
371 case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
372 case PIPE_CAP_CULL_DISTANCE:
373 case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES:
374 case PIPE_CAP_TGSI_VOTE:
375 case PIPE_CAP_MAX_WINDOW_RECTANGLES:
376 case PIPE_CAP_TGSI_ARRAY_COMPONENTS:
377 case PIPE_CAP_TGSI_CAN_READ_OUTPUTS:
378 case PIPE_CAP_NATIVE_FENCE_FD:
379 case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY:
380 case PIPE_CAP_TGSI_FS_FBFETCH:
381 return 0;
382
383 case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
384 if (family >= CHIP_CEDAR)
385 return 30;
386 else
387 return 0;
388 /* Stream output. */
389 case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
390 return rscreen->b.has_streamout ? 4 : 0;
391 case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
392 case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS:
393 return rscreen->b.has_streamout ? 1 : 0;
394 case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
395 case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
396 return 32*4;
397
398 /* Geometry shader output. */
399 case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
400 return 1024;
401 case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
402 return 16384;
403 case PIPE_CAP_MAX_VERTEX_STREAMS:
404 return family >= CHIP_CEDAR ? 4 : 1;
405
406 case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
407 return 2047;
408
409 /* Texturing. */
410 case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
411 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
412 if (family >= CHIP_CEDAR)
413 return 15;
414 else
415 return 14;
416 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
417 /* textures support 8192, but layered rendering supports 2048 */
418 return 12;
419 case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
420 /* textures support 8192, but layered rendering supports 2048 */
421 return 2048;
422
423 /* Render targets. */
424 case PIPE_CAP_MAX_RENDER_TARGETS:
425 /* XXX some r6xx are buggy and can only do 4 */
426 return 8;
427
428 case PIPE_CAP_MAX_VIEWPORTS:
429 return R600_MAX_VIEWPORTS;
430 case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS:
431 return 8;
432
433 /* Timer queries, present when the clock frequency is non zero. */
434 case PIPE_CAP_QUERY_TIME_ELAPSED:
435 return rscreen->b.info.clock_crystal_freq != 0;
436 case PIPE_CAP_QUERY_TIMESTAMP:
437 return rscreen->b.info.drm_minor >= 20 &&
438 rscreen->b.info.clock_crystal_freq != 0;
439
440 case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
441 case PIPE_CAP_MIN_TEXEL_OFFSET:
442 return -8;
443
444 case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
445 case PIPE_CAP_MAX_TEXEL_OFFSET:
446 return 7;
447
448 case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
449 return PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_R600;
450 case PIPE_CAP_ENDIANNESS:
451 return PIPE_ENDIAN_LITTLE;
452
453 case PIPE_CAP_VENDOR_ID:
454 return ATI_VENDOR_ID;
455 case PIPE_CAP_DEVICE_ID:
456 return rscreen->b.info.pci_id;
457 case PIPE_CAP_ACCELERATED:
458 return 1;
459 case PIPE_CAP_VIDEO_MEMORY:
460 return rscreen->b.info.vram_size >> 20;
461 case PIPE_CAP_UMA:
462 return 0;
463 case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
464 return rscreen->b.chip_class >= R700;
465 case PIPE_CAP_PCI_GROUP:
466 return rscreen->b.info.pci_domain;
467 case PIPE_CAP_PCI_BUS:
468 return rscreen->b.info.pci_bus;
469 case PIPE_CAP_PCI_DEVICE:
470 return rscreen->b.info.pci_dev;
471 case PIPE_CAP_PCI_FUNCTION:
472 return rscreen->b.info.pci_func;
473 }
474 return 0;
475 }
476
r600_get_shader_param(struct pipe_screen * pscreen,unsigned shader,enum pipe_shader_cap param)477 static int r600_get_shader_param(struct pipe_screen* pscreen, unsigned shader, enum pipe_shader_cap param)
478 {
479 struct r600_screen *rscreen = (struct r600_screen *)pscreen;
480
481 switch(shader)
482 {
483 case PIPE_SHADER_FRAGMENT:
484 case PIPE_SHADER_VERTEX:
485 case PIPE_SHADER_COMPUTE:
486 break;
487 case PIPE_SHADER_GEOMETRY:
488 if (rscreen->b.family >= CHIP_CEDAR)
489 break;
490 /* pre-evergreen geom shaders need newer kernel */
491 if (rscreen->b.info.drm_minor >= 37)
492 break;
493 return 0;
494 case PIPE_SHADER_TESS_CTRL:
495 case PIPE_SHADER_TESS_EVAL:
496 if (rscreen->b.family >= CHIP_CEDAR)
497 break;
498 default:
499 return 0;
500 }
501
502 switch (param) {
503 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
504 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
505 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
506 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
507 return 16384;
508 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
509 return 32;
510 case PIPE_SHADER_CAP_MAX_INPUTS:
511 return shader == PIPE_SHADER_VERTEX ? 16 : 32;
512 case PIPE_SHADER_CAP_MAX_OUTPUTS:
513 return shader == PIPE_SHADER_FRAGMENT ? 8 : 32;
514 case PIPE_SHADER_CAP_MAX_TEMPS:
515 return 256; /* Max native temporaries. */
516 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
517 if (shader == PIPE_SHADER_COMPUTE) {
518 uint64_t max_const_buffer_size;
519 pscreen->get_compute_param(pscreen, PIPE_SHADER_IR_TGSI,
520 PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE,
521 &max_const_buffer_size);
522 return MIN2(max_const_buffer_size, INT_MAX);
523
524 } else {
525 return R600_MAX_CONST_BUFFER_SIZE;
526 }
527 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
528 return R600_MAX_USER_CONST_BUFFERS;
529 case PIPE_SHADER_CAP_MAX_PREDS:
530 return 0; /* nothing uses this */
531 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
532 return 1;
533 case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
534 return 1;
535 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
536 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
537 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
538 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
539 return 1;
540 case PIPE_SHADER_CAP_SUBROUTINES:
541 return 0;
542 case PIPE_SHADER_CAP_INTEGERS:
543 case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
544 return 1;
545 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
546 case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
547 return 16;
548 case PIPE_SHADER_CAP_PREFERRED_IR:
549 if (shader == PIPE_SHADER_COMPUTE) {
550 return PIPE_SHADER_IR_NATIVE;
551 } else {
552 return PIPE_SHADER_IR_TGSI;
553 }
554 case PIPE_SHADER_CAP_SUPPORTED_IRS:
555 return 0;
556 case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
557 case PIPE_SHADER_CAP_DOUBLES:
558 if (rscreen->b.family == CHIP_ARUBA ||
559 rscreen->b.family == CHIP_CAYMAN ||
560 rscreen->b.family == CHIP_CYPRESS ||
561 rscreen->b.family == CHIP_HEMLOCK)
562 return 1;
563 return 0;
564 case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
565 case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
566 case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
567 case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
568 case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
569 return 0;
570 case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
571 /* due to a bug in the shader compiler, some loops hang
572 * if they are not unrolled, see:
573 * https://bugs.freedesktop.org/show_bug.cgi?id=86720
574 */
575 return 255;
576 }
577 return 0;
578 }
579
r600_destroy_screen(struct pipe_screen * pscreen)580 static void r600_destroy_screen(struct pipe_screen* pscreen)
581 {
582 struct r600_screen *rscreen = (struct r600_screen *)pscreen;
583
584 if (!rscreen)
585 return;
586
587 if (!rscreen->b.ws->unref(rscreen->b.ws))
588 return;
589
590 if (rscreen->global_pool) {
591 compute_memory_pool_delete(rscreen->global_pool);
592 }
593
594 r600_destroy_common_screen(&rscreen->b);
595 }
596
r600_resource_create(struct pipe_screen * screen,const struct pipe_resource * templ)597 static struct pipe_resource *r600_resource_create(struct pipe_screen *screen,
598 const struct pipe_resource *templ)
599 {
600 if (templ->target == PIPE_BUFFER &&
601 (templ->bind & PIPE_BIND_GLOBAL))
602 return r600_compute_global_buffer_create(screen, templ);
603
604 return r600_resource_create_common(screen, templ);
605 }
606
r600_screen_create(struct radeon_winsys * ws)607 struct pipe_screen *r600_screen_create(struct radeon_winsys *ws)
608 {
609 struct r600_screen *rscreen = CALLOC_STRUCT(r600_screen);
610
611 if (!rscreen) {
612 return NULL;
613 }
614
615 /* Set functions first. */
616 rscreen->b.b.context_create = r600_create_context;
617 rscreen->b.b.destroy = r600_destroy_screen;
618 rscreen->b.b.get_param = r600_get_param;
619 rscreen->b.b.get_shader_param = r600_get_shader_param;
620 rscreen->b.b.resource_create = r600_resource_create;
621
622 if (!r600_common_screen_init(&rscreen->b, ws)) {
623 FREE(rscreen);
624 return NULL;
625 }
626
627 if (rscreen->b.info.chip_class >= EVERGREEN) {
628 rscreen->b.b.is_format_supported = evergreen_is_format_supported;
629 } else {
630 rscreen->b.b.is_format_supported = r600_is_format_supported;
631 }
632
633 rscreen->b.debug_flags |= debug_get_flags_option("R600_DEBUG", r600_debug_options, 0);
634 if (debug_get_bool_option("R600_DEBUG_COMPUTE", FALSE))
635 rscreen->b.debug_flags |= DBG_COMPUTE;
636 if (debug_get_bool_option("R600_DUMP_SHADERS", FALSE))
637 rscreen->b.debug_flags |= DBG_FS | DBG_VS | DBG_GS | DBG_PS | DBG_CS | DBG_TCS | DBG_TES;
638 if (!debug_get_bool_option("R600_HYPERZ", TRUE))
639 rscreen->b.debug_flags |= DBG_NO_HYPERZ;
640
641 if (rscreen->b.family == CHIP_UNKNOWN) {
642 fprintf(stderr, "r600: Unknown chipset 0x%04X\n", rscreen->b.info.pci_id);
643 FREE(rscreen);
644 return NULL;
645 }
646
647 /* Figure out streamout kernel support. */
648 switch (rscreen->b.chip_class) {
649 case R600:
650 if (rscreen->b.family < CHIP_RS780) {
651 rscreen->b.has_streamout = rscreen->b.info.drm_minor >= 14;
652 } else {
653 rscreen->b.has_streamout = rscreen->b.info.drm_minor >= 23;
654 }
655 break;
656 case R700:
657 rscreen->b.has_streamout = rscreen->b.info.drm_minor >= 17;
658 break;
659 case EVERGREEN:
660 case CAYMAN:
661 rscreen->b.has_streamout = rscreen->b.info.drm_minor >= 14;
662 break;
663 default:
664 rscreen->b.has_streamout = FALSE;
665 break;
666 }
667
668 /* MSAA support. */
669 switch (rscreen->b.chip_class) {
670 case R600:
671 case R700:
672 rscreen->has_msaa = rscreen->b.info.drm_minor >= 22;
673 rscreen->has_compressed_msaa_texturing = false;
674 break;
675 case EVERGREEN:
676 rscreen->has_msaa = rscreen->b.info.drm_minor >= 19;
677 rscreen->has_compressed_msaa_texturing = rscreen->b.info.drm_minor >= 24;
678 break;
679 case CAYMAN:
680 rscreen->has_msaa = rscreen->b.info.drm_minor >= 19;
681 rscreen->has_compressed_msaa_texturing = true;
682 break;
683 default:
684 rscreen->has_msaa = FALSE;
685 rscreen->has_compressed_msaa_texturing = false;
686 }
687
688 rscreen->b.has_cp_dma = rscreen->b.info.drm_minor >= 27 &&
689 !(rscreen->b.debug_flags & DBG_NO_CP_DMA);
690
691 rscreen->b.barrier_flags.cp_to_L2 =
692 R600_CONTEXT_INV_VERTEX_CACHE |
693 R600_CONTEXT_INV_TEX_CACHE |
694 R600_CONTEXT_INV_CONST_CACHE;
695 rscreen->b.barrier_flags.compute_to_L2 = R600_CONTEXT_PS_PARTIAL_FLUSH;
696
697 rscreen->global_pool = compute_memory_pool_new(rscreen);
698
699 /* Create the auxiliary context. This must be done last. */
700 rscreen->b.aux_context = rscreen->b.b.context_create(&rscreen->b.b, NULL, 0);
701
702 #if 0 /* This is for testing whether aux_context and buffer clearing work correctly. */
703 struct pipe_resource templ = {};
704
705 templ.width0 = 4;
706 templ.height0 = 2048;
707 templ.depth0 = 1;
708 templ.array_size = 1;
709 templ.target = PIPE_TEXTURE_2D;
710 templ.format = PIPE_FORMAT_R8G8B8A8_UNORM;
711 templ.usage = PIPE_USAGE_DEFAULT;
712
713 struct r600_resource *res = r600_resource(rscreen->screen.resource_create(&rscreen->screen, &templ));
714 unsigned char *map = ws->buffer_map(res->buf, NULL, PIPE_TRANSFER_WRITE);
715
716 memset(map, 0, 256);
717
718 r600_screen_clear_buffer(rscreen, &res->b.b, 4, 4, 0xCC);
719 r600_screen_clear_buffer(rscreen, &res->b.b, 8, 4, 0xDD);
720 r600_screen_clear_buffer(rscreen, &res->b.b, 12, 4, 0xEE);
721 r600_screen_clear_buffer(rscreen, &res->b.b, 20, 4, 0xFF);
722 r600_screen_clear_buffer(rscreen, &res->b.b, 32, 20, 0x87);
723
724 ws->buffer_wait(res->buf, RADEON_USAGE_WRITE);
725
726 int i;
727 for (i = 0; i < 256; i++) {
728 printf("%02X", map[i]);
729 if (i % 16 == 15)
730 printf("\n");
731 }
732 #endif
733
734 if (rscreen->b.debug_flags & DBG_TEST_DMA)
735 r600_test_dma(&rscreen->b);
736
737 return &rscreen->b.b;
738 }
739