1//===- Alpha.td - Describe the Alpha Target Machine --------*- tablegen -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// 11//===----------------------------------------------------------------------===// 12 13// Get the target-independent interfaces which we are implementing... 14// 15include "llvm/Target/Target.td" 16 17//Alpha is little endian 18 19//===----------------------------------------------------------------------===// 20// Subtarget Features 21//===----------------------------------------------------------------------===// 22 23def FeatureCIX : SubtargetFeature<"cix", "HasCT", "true", 24 "Enable CIX extensions">; 25 26//===----------------------------------------------------------------------===// 27// Register File Description 28//===----------------------------------------------------------------------===// 29 30include "AlphaRegisterInfo.td" 31 32//===----------------------------------------------------------------------===// 33// Calling Convention Description 34//===----------------------------------------------------------------------===// 35 36include "AlphaCallingConv.td" 37 38//===----------------------------------------------------------------------===// 39// Schedule Description 40//===----------------------------------------------------------------------===// 41 42include "AlphaSchedule.td" 43 44//===----------------------------------------------------------------------===// 45// Instruction Descriptions 46//===----------------------------------------------------------------------===// 47 48include "AlphaInstrInfo.td" 49 50def AlphaInstrInfo : InstrInfo; 51 52//===----------------------------------------------------------------------===// 53// Alpha Processor Definitions 54//===----------------------------------------------------------------------===// 55 56def : Processor<"generic", Alpha21264Itineraries, []>; 57def : Processor<"ev6" , Alpha21264Itineraries, []>; 58def : Processor<"ev67" , Alpha21264Itineraries, [FeatureCIX]>; 59 60//===----------------------------------------------------------------------===// 61// The Alpha Target 62//===----------------------------------------------------------------------===// 63 64 65def Alpha : Target { 66 // Pull in Instruction Info: 67 let InstructionSet = AlphaInstrInfo; 68} 69