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1//===-- CellSDKIntrinsics.td - Cell SDK Intrinsics ---------*- tablegen -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9
10///--==-- Arithmetic ops intrinsics --==--
11def CellSDKah:
12    RR_Int_v8i16<0b00010011000, "ah", IntegerOp, int_spu_si_ah>;
13def CellSDKahi:
14    RI10_Int_v8i16<0b00010011000, "ahi", IntegerOp, int_spu_si_ahi>;
15def CellSDKa:
16    RR_Int_v4i32<0b00000011000, "a", IntegerOp, int_spu_si_a>;
17def CellSDKai:
18    RI10_Int_v4i32<0b00111000, "ai", IntegerOp, int_spu_si_ai>;
19def CellSDKsfh:
20    RR_Int_v8i16<0b00010010000, "sfh", IntegerOp, int_spu_si_sfh>;
21def CellSDKsfhi:
22    RI10_Int_v8i16<0b10110000, "sfhi", IntegerOp, int_spu_si_sfhi>;
23def CellSDKsf:
24    RR_Int_v4i32<0b00000010000, "sf", IntegerOp, int_spu_si_sf>;
25def CellSDKsfi:
26    RI10_Int_v4i32<0b00110000, "sfi", IntegerOp, int_spu_si_sfi>;
27def CellSDKaddx:
28    RR_Int_v4i32<0b00000010110, "addx", IntegerOp, int_spu_si_addx>;
29def CellSDKcg:
30    RR_Int_v4i32<0b0100001100, "cg", IntegerOp, int_spu_si_cg>;
31def CellSDKcgx:
32    RR_Int_v4i32<0b01000010110, "cgx", IntegerOp, int_spu_si_cgx>;
33def CellSDKsfx:
34    RR_Int_v4i32<0b10000010110, "sfx", IntegerOp, int_spu_si_sfx>;
35def CellSDKbg:
36    RR_Int_v4i32<0b01000010000, "bg", IntegerOp, int_spu_si_bg>;
37def CellSDKbgx:
38    RR_Int_v4i32<0b11000010110, "bgx", IntegerOp, int_spu_si_bgx>;
39
40def CellSDKmpy:
41    RRForm<0b00100011110, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
42      "mpy $rT, $rA, $rB", IntegerMulDiv,
43      [(set (v4i32 VECREG:$rT), (int_spu_si_mpy (v8i16 VECREG:$rA),
44                                                (v8i16 VECREG:$rB)))]>;
45
46def CellSDKmpyu:
47    RRForm<0b00110011110, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
48      "mpyu $rT, $rA, $rB", IntegerMulDiv,
49      [(set (v4i32 VECREG:$rT), (int_spu_si_mpyu (v8i16 VECREG:$rA),
50                                                 (v8i16 VECREG:$rB)))] >;
51
52def CellSDKmpyi:
53    RI10Form<0b00101110, (outs VECREG:$rT), (ins VECREG:$rA, s10imm:$val),
54      "mpyi $rT, $rA, $val", IntegerMulDiv,
55      [(set (v4i32 VECREG:$rT), (int_spu_si_mpyi (v8i16 VECREG:$rA),
56                                                 i16ImmSExt10:$val))]>;
57
58def CellSDKmpyui:
59    RI10Form<0b10101110, (outs VECREG:$rT), (ins VECREG:$rA, s10imm:$val),
60      "mpyui $rT, $rA, $val", IntegerMulDiv,
61      [(set (v4i32 VECREG:$rT), (int_spu_si_mpyui (v8i16 VECREG:$rA),
62                                                  i16ImmSExt10:$val))]>;
63
64def CellSDKmpya:
65    RRRForm<0b0011, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB, VECREG:$rC),
66      "mpya $rT, $rA, $rB, $rC", IntegerMulDiv,
67      [(set (v4i32 VECREG:$rT), (int_spu_si_mpya (v8i16 VECREG:$rA),
68                                                 (v8i16 VECREG:$rB),
69                                                 (v8i16 VECREG:$rC)))]>;
70
71def CellSDKmpyh:
72    RRForm<0b10100011110, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
73      "mpyh $rT, $rA, $rB", IntegerMulDiv,
74      [(set (v4i32 VECREG:$rT), (int_spu_si_mpyh (v4i32 VECREG:$rA),
75                                                 (v8i16 VECREG:$rB)))]>;
76
77def CellSDKmpys:
78    RRForm<0b11100011110, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
79      "mpys $rT, $rA, $rB", IntegerMulDiv,
80      [(set (v4i32 VECREG:$rT), (int_spu_si_mpys (v8i16 VECREG:$rA),
81                                                 (v8i16 VECREG:$rB)))]>;
82
83def CellSDKmpyhh:
84    RRForm<0b01100011110, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
85      "mpyhh $rT, $rA, $rB", IntegerMulDiv,
86      [(set (v4i32 VECREG:$rT), (int_spu_si_mpyhh (v8i16 VECREG:$rA),
87                                                  (v8i16 VECREG:$rB)))]>;
88
89def CellSDKmpyhha:
90    RRForm<0b01100010110, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
91      "mpyhha $rT, $rA, $rB", IntegerMulDiv,
92      [(set (v4i32 VECREG:$rT), (int_spu_si_mpyhha (v8i16 VECREG:$rA),
93                                                   (v8i16 VECREG:$rB)))]>;
94
95// Not sure how to match a (set $rT, (add $rT (mpyhh $rA, $rB)))... so leave
96// as an intrinsic for the time being
97def CellSDKmpyhhu:
98    RRForm<0b01110011110, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
99      "mpyhhu $rT, $rA, $rB", IntegerMulDiv,
100      [(set (v4i32 VECREG:$rT), (int_spu_si_mpyhhu (v8i16 VECREG:$rA),
101                                                   (v8i16 VECREG:$rB)))]>;
102
103def CellSDKmpyhhau:
104    RRForm<0b01110010110, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
105      "mpyhhau $rT, $rA, $rB", IntegerMulDiv,
106      [(set (v4i32 VECREG:$rT), (int_spu_si_mpyhhau (v8i16 VECREG:$rA),
107                                                    (v8i16 VECREG:$rB)))]>;
108
109def CellSDKand:
110        RRForm<0b1000011000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
111          "and\t $rT, $rA, $rB", IntegerOp,
112          [(set (v4i32 VECREG:$rT),
113                (int_spu_si_and (v4i32 VECREG:$rA), (v4i32 VECREG:$rB)))]>;
114
115def CellSDKandc:
116        RRForm<0b10000011010, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
117          "andc\t $rT, $rA, $rB", IntegerOp,
118          [(set (v4i32 VECREG:$rT),
119                (int_spu_si_andc (v4i32 VECREG:$rA), (v4i32 VECREG:$rB)))]>;
120
121def CellSDKandbi:
122     RI10Form<0b01101000, (outs VECREG:$rT), (ins VECREG:$rA, u10imm_i8:$val),
123       "andbi\t $rT, $rA, $val", BranchResolv,
124       [(set (v16i8 VECREG:$rT),
125             (int_spu_si_andbi (v16i8 VECREG:$rA), immU8:$val))]>;
126
127def CellSDKandhi:
128     RI10Form<0b10101000, (outs VECREG:$rT), (ins VECREG:$rA, s10imm:$val),
129           "andhi\t $rT, $rA, $val", BranchResolv,
130       [(set (v8i16 VECREG:$rT),
131             (int_spu_si_andhi (v8i16 VECREG:$rA), i16ImmSExt10:$val))]>;
132
133def CellSDKandi:
134     RI10Form<0b00101000, (outs VECREG:$rT), (ins VECREG:$rA, s10imm:$val),
135           "andi\t $rT, $rA, $val", BranchResolv,
136       [(set (v4i32 VECREG:$rT),
137             (int_spu_si_andi (v4i32 VECREG:$rA), i32ImmSExt10:$val))]>;
138
139def CellSDKor:
140        RRForm<0b10000010000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
141          "or\t $rT, $rA, $rB", IntegerOp,
142          [(set (v4i32 VECREG:$rT),
143                (int_spu_si_or (v4i32 VECREG:$rA), (v4i32 VECREG:$rB)))]>;
144
145def CellSDKorc:
146        RRForm<0b10010011010, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
147          "addc\t $rT, $rA, $rB", IntegerOp,
148          [(set (v4i32 VECREG:$rT),
149                (int_spu_si_orc (v4i32 VECREG:$rA), (v4i32 VECREG:$rB)))]>;
150
151def CellSDKorbi:
152     RI10Form<0b01100000, (outs VECREG:$rT), (ins VECREG:$rA, u10imm_i8:$val),
153       "orbi\t $rT, $rA, $val", BranchResolv,
154       [(set (v16i8 VECREG:$rT),
155             (int_spu_si_orbi (v16i8 VECREG:$rA), immU8:$val))]>;
156
157def CellSDKorhi:
158     RI10Form<0b10100000, (outs VECREG:$rT), (ins VECREG:$rA, s10imm:$val),
159           "orhi\t $rT, $rA, $val", BranchResolv,
160       [(set (v8i16 VECREG:$rT),
161             (int_spu_si_orhi (v8i16 VECREG:$rA), i16ImmSExt10:$val))]>;
162
163def CellSDKori:
164     RI10Form<0b00100000, (outs VECREG:$rT), (ins VECREG:$rA, s10imm:$val),
165           "ori\t $rT, $rA, $val", BranchResolv,
166       [(set (v4i32 VECREG:$rT),
167             (int_spu_si_ori (v4i32 VECREG:$rA), i32ImmSExt10:$val))]>;
168
169def CellSDKxor:
170        RRForm<0b10000010000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
171          "xor\t $rT, $rA, $rB", IntegerOp,
172          [(set (v4i32 VECREG:$rT),
173                (int_spu_si_xor (v4i32 VECREG:$rA), (v4i32 VECREG:$rB)))]>;
174
175def CellSDKxorbi:
176     RI10Form<0b01100000, (outs VECREG:$rT), (ins VECREG:$rA, u10imm_i8:$val),
177       "xorbi\t $rT, $rA, $val", BranchResolv,
178       [(set (v16i8 VECREG:$rT), (int_spu_si_xorbi (v16i8 VECREG:$rA), immU8:$val))]>;
179
180def CellSDKxorhi:
181     RI10Form<0b10100000, (outs VECREG:$rT), (ins VECREG:$rA, s10imm:$val),
182       "xorhi\t $rT, $rA, $val", BranchResolv,
183       [(set (v8i16 VECREG:$rT),
184             (int_spu_si_xorhi (v8i16 VECREG:$rA), i16ImmSExt10:$val))]>;
185
186def CellSDKxori:
187     RI10Form<0b00100000, (outs VECREG:$rT), (ins VECREG:$rA, s10imm:$val),
188           "xori\t $rT, $rA, $val", BranchResolv,
189       [(set (v4i32 VECREG:$rT),
190             (int_spu_si_xori (v4i32 VECREG:$rA), i32ImmSExt10:$val))]>;
191
192def CellSDKnor:
193        RRForm<0b10000010000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
194          "nor\t $rT, $rA, $rB", IntegerOp,
195          [(set (v4i32 VECREG:$rT),
196                (int_spu_si_nor (v4i32 VECREG:$rA), (v4i32 VECREG:$rB)))]>;
197
198def CellSDKnand:
199        RRForm<0b10000010000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
200          "nand\t $rT, $rA, $rB", IntegerOp,
201          [(set (v4i32 VECREG:$rT),
202                (int_spu_si_nand (v4i32 VECREG:$rA), (v4i32 VECREG:$rB)))]>;
203
204//===----------------------------------------------------------------------===//
205// Shift/rotate intrinsics:
206//===----------------------------------------------------------------------===//
207
208def CellSDKshli:
209  Pat<(int_spu_si_shli (v4i32 VECREG:$rA), uimm7:$val),
210      (SHLIv4i32 VECREG:$rA, (TO_IMM32 imm:$val))>;
211
212def CellSDKshlqbi:
213  Pat<(int_spu_si_shlqbi VECREG:$rA, R32C:$rB),
214      (SHLQBIv16i8 VECREG:$rA, R32C:$rB)>;
215
216def CellSDKshlqii:
217  Pat<(int_spu_si_shlqbii VECREG:$rA, uimm7:$val),
218      (SHLQBIIv16i8 VECREG:$rA, (TO_IMM32 imm:$val))>;
219
220def CellSDKshlqby:
221  Pat<(int_spu_si_shlqby VECREG:$rA, R32C:$rB),
222      (SHLQBYv16i8 VECREG:$rA, R32C:$rB)>;
223
224def CellSDKshlqbyi:
225  Pat<(int_spu_si_shlqbyi VECREG:$rA, uimm7:$val),
226      (SHLQBYIv16i8 VECREG:$rA, (TO_IMM32 imm:$val))>;
227
228
229//===----------------------------------------------------------------------===//
230// Branch/compare intrinsics:
231//===----------------------------------------------------------------------===//
232
233def CellSDKceq:
234  RRForm<0b00000011110, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
235        "ceq\t $rT, $rA, $rB", BranchResolv,
236        [(set (v4i32 VECREG:$rT),
237              (int_spu_si_ceq (v4i32 VECREG:$rA), (v4i32 VECREG:$rB)))]>;
238
239def CellSDKceqi:
240  RI10Form<0b00111110, (outs VECREG:$rT), (ins VECREG:$rA, s10imm:$val),
241        "ceqi\t $rT, $rA, $val", BranchResolv,
242    [(set (v4i32 VECREG:$rT),
243          (int_spu_si_ceqi (v4i32 VECREG:$rA), i32ImmSExt10:$val))]>;
244
245def CellSDKceqb:
246  RRForm<0b00001011110, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
247        "ceqb\t $rT, $rA, $rB", BranchResolv,
248        [(set (v16i8 VECREG:$rT),
249              (int_spu_si_ceqb (v16i8 VECREG:$rA), (v16i8 VECREG:$rB)))]>;
250
251def CellSDKceqbi:
252  RI10Form<0b01111110, (outs VECREG:$rT), (ins VECREG:$rA, u10imm_i8:$val),
253        "ceqbi\t $rT, $rA, $val", BranchResolv,
254    [(set (v16i8 VECREG:$rT), (int_spu_si_ceqbi (v16i8 VECREG:$rA), immU8:$val))]>;
255
256def CellSDKceqh:
257  RRForm<0b00010011110, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
258        "ceqh\t $rT, $rA, $rB", BranchResolv,
259        [(set (v8i16 VECREG:$rT),
260              (int_spu_si_ceqh (v8i16 VECREG:$rA), (v8i16 VECREG:$rB)))]>;
261
262def CellSDKceqhi:
263  RI10Form<0b10111110, (outs VECREG:$rT), (ins VECREG:$rA, s10imm:$val),
264        "ceqhi\t $rT, $rA, $val", BranchResolv,
265    [(set (v8i16 VECREG:$rT),
266          (int_spu_si_ceqhi (v8i16 VECREG:$rA), i16ImmSExt10:$val))]>;
267def CellSDKcgth:
268  RRForm<0b00010011110, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
269    "cgth\t $rT, $rA, $rB", BranchResolv,
270        [(set (v8i16 VECREG:$rT),
271              (int_spu_si_cgth (v8i16 VECREG:$rA), (v8i16 VECREG:$rB)))]>;
272
273def CellSDKcgthi:
274  RI10Form<0b10111110, (outs VECREG:$rT), (ins VECREG:$rA, s10imm:$val),
275    "cgthi\t $rT, $rA, $val", BranchResolv,
276        [(set (v8i16 VECREG:$rT),
277              (int_spu_si_cgthi (v8i16 VECREG:$rA), i16ImmSExt10:$val))]>;
278
279def CellSDKcgt:
280  RRForm<0b00000010010, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
281    "cgt\t $rT, $rA, $rB", BranchResolv,
282        [(set (v4i32 VECREG:$rT),
283              (int_spu_si_cgt (v4i32 VECREG:$rA), (v4i32 VECREG:$rB)))]>;
284
285def CellSDKcgti:
286  RI10Form<0b00110010, (outs VECREG:$rT), (ins VECREG:$rA, s10imm:$val),
287    "cgti\t $rT, $rA, $val", BranchResolv,
288        [(set (v4i32 VECREG:$rT),
289              (int_spu_si_cgti (v4i32 VECREG:$rA), i32ImmSExt10:$val))]>;
290
291def CellSDKcgtb:
292  RRForm<0b00001010010, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
293    "cgtb\t $rT, $rA, $rB", BranchResolv,
294        [(set (v16i8 VECREG:$rT),
295              (int_spu_si_cgtb (v16i8 VECREG:$rA), (v16i8 VECREG:$rB)))]>;
296
297def CellSDKcgtbi:
298  RI10Form<0b01110010, (outs VECREG:$rT), (ins VECREG:$rA, u10imm_i8:$val),
299    "cgtbi\t $rT, $rA, $val", BranchResolv,
300        [(set (v16i8 VECREG:$rT), (int_spu_si_cgtbi (v16i8 VECREG:$rA), immU8:$val))]>;
301
302def CellSDKclgth:
303  RRForm<0b00010011010, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
304    "clgth\t $rT, $rA, $rB", BranchResolv,
305        [(set (v8i16 VECREG:$rT),
306              (int_spu_si_clgth (v8i16 VECREG:$rA), (v8i16 VECREG:$rB)))]>;
307
308def CellSDKclgthi:
309  RI10Form<0b10111010, (outs VECREG:$rT), (ins VECREG:$rA, s10imm:$val),
310    "clgthi\t $rT, $rA, $val", BranchResolv,
311        [(set (v8i16 VECREG:$rT),
312              (int_spu_si_clgthi (v8i16 VECREG:$rA), i16ImmSExt10:$val))]>;
313
314def CellSDKclgt:
315  RRForm<0b00000011010, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
316    "clgt\t $rT, $rA, $rB", BranchResolv,
317        [(set (v4i32 VECREG:$rT),
318              (int_spu_si_clgt (v4i32 VECREG:$rA), (v4i32 VECREG:$rB)))]>;
319
320def CellSDKclgti:
321  RI10Form<0b00111010, (outs VECREG:$rT), (ins VECREG:$rA, s10imm:$val),
322    "clgti\t $rT, $rA, $val", BranchResolv,
323        [(set (v4i32 VECREG:$rT),
324              (int_spu_si_clgti (v4i32 VECREG:$rA), i32ImmSExt10:$val))]>;
325
326def CellSDKclgtb:
327  RRForm<0b00001011010, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
328    "clgtb\t $rT, $rA, $rB", BranchResolv,
329    [(set (v16i8 VECREG:$rT),
330          (int_spu_si_clgtb (v16i8 VECREG:$rA), (v16i8 VECREG:$rB)))]>;
331
332def CellSDKclgtbi:
333  RI10Form<0b01111010, (outs VECREG:$rT), (ins VECREG:$rA, u10imm_i8:$val),
334    "clgtbi\t $rT, $rA, $val", BranchResolv,
335    [(set (v16i8 VECREG:$rT),
336          (int_spu_si_clgtbi (v16i8 VECREG:$rA), immU8:$val))]>;
337
338//===----------------------------------------------------------------------===//
339// Floating-point intrinsics:
340//===----------------------------------------------------------------------===//
341
342def CellSDKfa:
343  RRForm<0b00100011010, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
344    "fa\t $rT, $rA, $rB", SPrecFP,
345        [(set (v4f32 VECREG:$rT), (int_spu_si_fa (v4f32 VECREG:$rA),
346                                                 (v4f32 VECREG:$rB)))]>;
347
348def CellSDKfs:
349  RRForm<0b10100011010, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
350    "fs\t $rT, $rA, $rB", SPrecFP,
351        [(set (v4f32 VECREG:$rT), (int_spu_si_fs (v4f32 VECREG:$rA),
352                                                 (v4f32 VECREG:$rB)))]>;
353
354def CellSDKfm:
355  RRForm<0b01100011010, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
356    "fm\t $rT, $rA, $rB", SPrecFP,
357        [(set (v4f32 VECREG:$rT), (int_spu_si_fm (v4f32 VECREG:$rA),
358                                                 (v4f32 VECREG:$rB)))]>;
359
360def CellSDKfceq:
361  RRForm<0b01000011110, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
362    "fceq\t $rT, $rA, $rB", SPrecFP,
363        [(set (v4f32 VECREG:$rT), (int_spu_si_fceq (v4f32 VECREG:$rA),
364                                                   (v4f32 VECREG:$rB)))]>;
365
366def CellSDKfcgt:
367  RRForm<0b01000011010, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
368    "fcgt\t $rT, $rA, $rB", SPrecFP,
369        [(set (v4f32 VECREG:$rT), (int_spu_si_fcgt (v4f32 VECREG:$rA),
370                                                   (v4f32 VECREG:$rB)))]>;
371
372def CellSDKfcmeq:
373  RRForm<0b01010011110, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
374    "fcmeq\t $rT, $rA, $rB", SPrecFP,
375        [(set (v4f32 VECREG:$rT), (int_spu_si_fcmeq (v4f32 VECREG:$rA),
376                                                    (v4f32 VECREG:$rB)))]>;
377
378def CellSDKfcmgt:
379  RRForm<0b01010011010, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
380    "fcmgt\t $rT, $rA, $rB", SPrecFP,
381        [(set (v4f32 VECREG:$rT), (int_spu_si_fcmgt (v4f32 VECREG:$rA),
382                                                    (v4f32 VECREG:$rB)))]>;
383
384def CellSDKfma:
385  RRRForm<0b0111, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB, VECREG:$rC),
386    "fma\t $rT, $rA, $rB, $rC", SPrecFP,
387        [(set (v4f32 VECREG:$rT), (int_spu_si_fma (v4f32 VECREG:$rA),
388                                                  (v4f32 VECREG:$rB),
389                                                  (v4f32 VECREG:$rC)))]>;
390
391def CellSDKfnms:
392  RRRForm<0b1011, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB, VECREG:$rC),
393    "fnms\t $rT, $rA, $rB, $rC", SPrecFP,
394        [(set (v4f32 VECREG:$rT), (int_spu_si_fnms (v4f32 VECREG:$rA),
395                                                   (v4f32 VECREG:$rB),
396                                                   (v4f32 VECREG:$rC)))]>;
397
398def CellSDKfms:
399  RRRForm<0b1111, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB, VECREG:$rC),
400    "fms\t $rT, $rA, $rB, $rC", SPrecFP,
401        [(set (v4f32 VECREG:$rT), (int_spu_si_fms (v4f32 VECREG:$rA),
402                                                  (v4f32 VECREG:$rB),
403                                                  (v4f32 VECREG:$rC)))]>;
404
405//===----------------------------------------------------------------------===//
406// Double precision floating-point intrinsics:
407//===----------------------------------------------------------------------===//
408
409def CellSDKdfa:
410  RRForm<0b00110011010, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
411    "dfa\t $rT, $rA, $rB", DPrecFP,
412        [(set (v2f64 VECREG:$rT), (int_spu_si_dfa (v2f64 VECREG:$rA),
413                                                  (v2f64 VECREG:$rB)))]>;
414
415def CellSDKdfs:
416  RRForm<0b10110011010, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
417    "dfs\t $rT, $rA, $rB", DPrecFP,
418        [(set (v2f64 VECREG:$rT), (int_spu_si_dfs (v2f64 VECREG:$rA),
419                                                  (v2f64 VECREG:$rB)))]>;
420
421def CellSDKdfm:
422  RRForm<0b01110011010, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
423    "dfm\t $rT, $rA, $rB", DPrecFP,
424        [(set (v2f64 VECREG:$rT), (int_spu_si_dfm (v2f64 VECREG:$rA),
425                                                  (v2f64 VECREG:$rB)))]>;
426
427def CellSDKdfma:
428  RRForm<0b00111010110, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
429    "dfma\t $rT, $rA, $rB", DPrecFP,
430        [(set (v2f64 VECREG:$rT), (int_spu_si_dfma (v2f64 VECREG:$rA),
431                                                   (v2f64 VECREG:$rB)))]>;
432
433def CellSDKdfnma:
434  RRForm<0b11111010110, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
435    "dfnma\t $rT, $rA, $rB", DPrecFP,
436        [(set (v2f64 VECREG:$rT), (int_spu_si_dfnma (v2f64 VECREG:$rA),
437                                                    (v2f64 VECREG:$rB)))]>;
438
439def CellSDKdfnms:
440  RRForm<0b01111010110, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
441    "dfnms\t $rT, $rA, $rB", DPrecFP,
442        [(set (v2f64 VECREG:$rT), (int_spu_si_dfnms (v2f64 VECREG:$rA),
443                                                    (v2f64 VECREG:$rB)))]>;
444
445def CellSDKdfms:
446  RRForm<0b10111010110, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
447    "dfms\t $rT, $rA, $rB", DPrecFP,
448        [(set (v2f64 VECREG:$rT), (int_spu_si_dfms (v2f64 VECREG:$rA),
449                                                   (v2f64 VECREG:$rB)))]>;
450