1//===- Mips.td - Describe the Mips Target Machine ----------*- tablegen -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// This is the top level entry point for the Mips target. 10//===----------------------------------------------------------------------===// 11 12//===----------------------------------------------------------------------===// 13// Target-independent interfaces 14//===----------------------------------------------------------------------===// 15 16include "llvm/Target/Target.td" 17 18//===----------------------------------------------------------------------===// 19// Register File, Calling Conv, Instruction Descriptions 20//===----------------------------------------------------------------------===// 21 22include "MipsRegisterInfo.td" 23include "MipsSchedule.td" 24include "MipsInstrInfo.td" 25include "MipsCallingConv.td" 26 27def MipsInstrInfo : InstrInfo; 28 29//===----------------------------------------------------------------------===// 30// Mips Subtarget features // 31//===----------------------------------------------------------------------===// 32 33def FeatureGP64Bit : SubtargetFeature<"gp64", "IsGP64bit", "true", 34 "General Purpose Registers are 64-bit wide.">; 35def FeatureFP64Bit : SubtargetFeature<"fp64", "IsFP64bit", "true", 36 "Support 64-bit FP registers.">; 37def FeatureSingleFloat : SubtargetFeature<"single-float", "IsSingleFloat", 38 "true", "Only supports single precision float">; 39def FeatureO32 : SubtargetFeature<"o32", "MipsABI", "O32", 40 "Enable o32 ABI">; 41def FeatureN32 : SubtargetFeature<"n32", "MipsABI", "N32", 42 "Enable n32 ABI">; 43def FeatureN64 : SubtargetFeature<"n64", "MipsABI", "N64", 44 "Enable n64 ABI">; 45def FeatureEABI : SubtargetFeature<"eabi", "MipsABI", "EABI", 46 "Enable eabi ABI">; 47def FeatureVFPU : SubtargetFeature<"vfpu", "HasVFPU", 48 "true", "Enable vector FPU instructions.">; 49def FeatureSEInReg : SubtargetFeature<"seinreg", "HasSEInReg", "true", 50 "Enable 'signext in register' instructions.">; 51def FeatureCondMov : SubtargetFeature<"condmov", "HasCondMov", "true", 52 "Enable 'conditional move' instructions.">; 53def FeatureMulDivAdd : SubtargetFeature<"muldivadd", "HasMulDivAdd", "true", 54 "Enable 'multiply add/sub' instructions.">; 55def FeatureMinMax : SubtargetFeature<"minmax", "HasMinMax", "true", 56 "Enable 'min/max' instructions.">; 57def FeatureSwap : SubtargetFeature<"swap", "HasSwap", "true", 58 "Enable 'byte/half swap' instructions.">; 59def FeatureBitCount : SubtargetFeature<"bitcount", "HasBitCount", "true", 60 "Enable 'count leading bits' instructions.">; 61def FeatureMips32 : SubtargetFeature<"mips32", "MipsArchVersion", "Mips32", 62 "Mips32 ISA Support", 63 [FeatureCondMov, FeatureBitCount]>; 64def FeatureMips32r2 : SubtargetFeature<"mips32r2", "MipsArchVersion", 65 "Mips32r2", "Mips32r2 ISA Support", 66 [FeatureMips32, FeatureSEInReg]>; 67def FeatureMips64 : SubtargetFeature<"mips64", "MipsArchVersion", 68 "Mips64", "Mips64 ISA Support", 69 [FeatureGP64Bit, FeatureFP64Bit, 70 FeatureMips32]>; 71def FeatureMips64r2 : SubtargetFeature<"mips64r2", "MipsArchVersion", 72 "Mips64r2", "Mips64r2 ISA Support", 73 [FeatureMips64, FeatureMips32r2]>; 74 75//===----------------------------------------------------------------------===// 76// Mips processors supported. 77//===----------------------------------------------------------------------===// 78 79class Proc<string Name, list<SubtargetFeature> Features> 80 : Processor<Name, MipsGenericItineraries, Features>; 81 82def : Proc<"mips32r1", [FeatureMips32]>; 83def : Proc<"4ke", [FeatureMips32r2]>; 84def : Proc<"mips64r1", [FeatureMips64]>; 85def : Proc<"mips64r2", [FeatureMips64r2]>; 86 87def MipsAsmWriter : AsmWriter { 88 string AsmWriterClassName = "InstPrinter"; 89 bit isMCAsmWriter = 1; 90} 91 92def Mips : Target { 93 let InstructionSet = MipsInstrInfo; 94 95 let AssemblyWriters = [MipsAsmWriter]; 96} 97 98