1; RUN: llc < %s -march=arm -mattr=+v6 | FileCheck %s -check-prefix=V6 2; RUN: llc < %s -march=arm | FileCheck %s -check-prefix=V4 3; RUN: llc < %s -march=thumb -mcpu=cortex-m3 | FileCheck %s -check-prefix=M3 4 5define i32 @smulhi(i32 %x, i32 %y) nounwind { 6; V6: smulhi: 7; V6: smmul 8 9; V4: smulhi: 10; V4: smull 11 12; M3: smulhi: 13; M3: smull 14 %tmp = sext i32 %x to i64 ; <i64> [#uses=1] 15 %tmp1 = sext i32 %y to i64 ; <i64> [#uses=1] 16 %tmp2 = mul i64 %tmp1, %tmp ; <i64> [#uses=1] 17 %tmp3 = lshr i64 %tmp2, 32 ; <i64> [#uses=1] 18 %tmp3.upgrd.1 = trunc i64 %tmp3 to i32 ; <i32> [#uses=1] 19 ret i32 %tmp3.upgrd.1 20} 21 22define i32 @umulhi(i32 %x, i32 %y) nounwind { 23; V6: umulhi: 24; V6: umull 25 26; V4: umulhi: 27; V4: umull 28 29; M3: umulhi: 30; M3: umull 31 %tmp = zext i32 %x to i64 ; <i64> [#uses=1] 32 %tmp1 = zext i32 %y to i64 ; <i64> [#uses=1] 33 %tmp2 = mul i64 %tmp1, %tmp ; <i64> [#uses=1] 34 %tmp3 = lshr i64 %tmp2, 32 ; <i64> [#uses=1] 35 %tmp3.upgrd.2 = trunc i64 %tmp3 to i32 ; <i32> [#uses=1] 36 ret i32 %tmp3.upgrd.2 37} 38 39; rdar://r10152911 40define i32 @t3(i32 %a) nounwind { 41; V6: t3: 42; V6: smmla 43 44; V4: t3: 45; V4: smull 46 47; M3: t3: 48; M3-NOT: smmla 49; M3: smull 50entry: 51 %tmp1 = mul nsw i32 %a, 3 52 %tmp2 = sdiv i32 %tmp1, 23 53 ret i32 %tmp2 54} 55